ABSTRACT. Mixture-of-Experts (MoE) models activate only a small subset of experts per token. Speculative decoding, however, verifies multiple draft tokens together, expanding the verification working set and increasing expert accesses. On a memory-limited GPU running an offloaded MoE model, these accesses become additional expert transfers on the critical path, so conventional fixed-horizon MoE speculative decoding can lose its latency benefit. Existing expert caching and demand-loading mechanisms react to these transfers, but do not decide whether a round should speculate or use draft progress to prepare the following verification. We present AHEAD, a dynamic draft-verify coordination system with three coordinated components. (A) A target-derived, expert-constructed self-draft avoids a separate draft model. (B) A no-probe round controller uses synchronized target and draft logits to select target-only Direct execution or dynamically choose the speculative token horizon. (C) The first draft token's route hint triggers at most one deadline- and capacity-feasible expert prefetch during the remaining draft interval. Target routing and fallback demand loading remain authoritative, preserving exact greedy output. On a single NVIDIA RTX 4090 24 GB GPU, AHEAD reduces post-prefill request-completion latency relative to target-only MoE inference by 20.5% and 19.5% on Mixtral-8x7B and Qwen3-30B-A3B, respectively. It achieves 1.65x and 2.24x speedups over the corresponding equal-budget fixed-horizon MoE speculative decoding baseline.

ABSTRACT. Autoregressive LLM decoding is bottlenecked by key-value (KV) memory bandwidth: at each step, the model must stream the entire KV cache from high-bandwidth memory (HBM), incurring O(S) traffic for a context of length S. Sparse attention methods reduce this to O(K) by selecting a subset of K << S positions, but existing oracles either use static structural patterns or retrospective eviction scores that reflect past usefulness, not the token relevance the current query will need.

We identify a third path: attention patterns in autoregressive decoding are predictable. We prove and empirically verify that the set of tokens that will receive significant attention at step t can be reliably forecast from the current query together with a compact running access-history sketch. Building on this insight, we present SVR (Speculate-Verify-Repeat), a closed-loop sparse-attention framework: Speculate: a per-head predictor pi_theta selects the active set A_hat_t and restricts attention to it as the fast path. Verify: every V_t steps, a lightweight residual probe samples the complement C_t, producing a low-cost miss-rate estimate m_hat_t and labeling missed and falsely selected positions. Repeat: a single Perceptron-style update on the labels refines pi_theta and reduces future miss rates; the period V_t grows as m_t falls, amortizing verification cost.

On LLaMA-3-8B/70B, Mistral-7B, and Qwen-2-7B across LongBench, RULER, and SCROLLS, SVR drives miss rate below 3% at K = 12%S after fewer than 200 warm-up steps, achieving 2.8x decode throughput over Full-KV and 1.7x over the best competing method, DuoAttention, while SVR-token matches full-attention accuracy within 0.9 percentage points on aggregate LongBench/RULER/SCROLLS scores.

ABSTRACT. Mixture-of-Experts (MoE) models scale capacity through sparse activation, making them a natural fit for edge CPU-GPU systems. However, per-token expert traffic dominates decoding latency, leaving MoE inference severely bandwidth-bound. Low-bit quantization can cut this traffic at the source, yet its practical deployment is limited by the excessive overhead of supplying mixed precision under memory constraints, the suboptimal criteria for assigning expert precision under dynamic activation, and the inefficient utilization of heterogeneous compute under shared bandwidth. To address these limitations, this paper proposes TriM, a software-hardware co-designed framework that generates, assigns, and executes mixed-precision experts on demand. First, a register-resident fused quantization (RFQ) kernel is proposed to eliminate the memory spill that dominates online quantization, generating low-bit experts at near-zero cost. Second, a sensitivity guided co-scheduling (SGCS) strategy is developed to assign expert precision by measured output sensitivity, and to map expert execution onto the asymmetric CPU cores and the GPU. Implemented in llama.cpp, TriM is extensively evaluated on four modern MoE models, achieving average end-to-end speedups of 9.43× over the standard GPU-DIMM baseline and 3.37× over a state-of-the-art offloading solution built on near-data processing, with negligible accuracy degradation.

ABSTRACT. Test-Time Scaling (TTS), an Large Language Model (LLM) inference approach, improves solution quality by increasing inference-time compute rather than model size or training cost. Existing work primarily improves the algorithmic efficiency of TTS, while the connection between its workload dynamics and hardware efficiency remains underexplored. We show that decreasing beam counts degrade general matrix multiplication (GEMM) efficiency and attention parallelism, while growing contexts progressively shift latency dominance toward attention. Guided by these findings, we propose AccTTS, a computational optimization framework with two complementary adaptations, beam-adaptive GEMM execution and adaptive context parallelization. Offline profiling identifies the hardware-dependent configurations required by these adaptations. Integrated into vLLM, AccTTS achieves up to a $1.43\times$ end-to-end speedup across datasets, models, compute budgets, and TTS algorithms. We open-source AccTTS in this \href{https://anonymous.4open.science/r/AccTTS-anonymous-EFFA/}{\underline{anonymous repository}}.

ABSTRACT. Large Language Models (LLMs) have posed a large pressure on the memory subsystem of today's GPUs and AI accelerators. Although more advanced high-bandwidth memories (HBMs) consistently increase off-chip bandwidth, the insufficient NoC and L2 cache bandwidth has not attracted enough attention. To alleviate NoC and L2 cache congestion, both industrial products and academic works have introduced coalescers that capture intra-cluster data reuse. We notice the number of such reuse is known at programming time in many of today's applications, so we leverage this information to guide the coalescers. Experiments show that our dataflow-aided coalescer performs far better than current designs under large GEMM (1.22x) and FlashAttention (2.08x) workloads, and is equally performant for smaller workloads and attention in coding. Interestingly, in systems with a sufficient L2 capacity, our coalescer can still outperform conventional ones by achieving a higher DRAM bandwidth utilization, even when both cases have the same number of DRAM accesses, a phenomenon never revealed before. Since these designs involve a tradeoff between load balance and concurrency of the cores, we suggest that a practical design should include both working modes so that programmers can select the mode that fits their application.

ABSTRACT. Edge devices increasingly run a mix of neural networks on one chip, all competing for a single energy and real-time budget. Meeting that budget efficiently demands an accelerator specialized to the whole model mix. However, current accelerator design flows separate hardware implementation from compiler support or rely on fixed architectural templates, so the deployed model mix cannot shape the accelerator architecture.

We close this gap with compiler-driven hardware generation, which turns the deployment compiler into the generator that designs an accelerator optimized for the target model mix. Instead of targeting a predefined accelerator or a fixed-function datapath, the compiler searches a hardware design space using its mapping and PPA cost infrastructure and derives a programmable accelerator together with the deployment artifacts. Applied to the MLPerf Tiny benchmark and a medical scenario, the compiler adapts the generated accelerators to the model composition, execution rate, optimization objective, and real-time constraint, and lowers energy per MAC by 12\% over a hand-tuned design.

ABSTRACT. This paper addresses the any-angle die-to-die (D2D) routing problem under advanced packaging constraints, including teardrop and offset-via structures. These manufacturability-driven features substantially reduce the effective routing resources and tightly couple routing topology with geometric feasibility, making scalable optimization challenging. To address this challenge, we propose a concurrent routing framework based on Lagrangian relaxation that transforms topology generation into a sequence-based optimization problem, enabling efficient global optimization under non-crossing constraints. By relaxing the routing-capacity constraints, the layer-assignment problem is reduced to a heaviest increasing subsequence (HIS) formulation, allowing efficient selection of routable nets while preserving the global routing structure. To support valid and flexible teardrop and offset-via placement, we introduce a projection-based interval propagation scheme that determines feasible via and teardrop configurations and enforces geometric consistency across layers. This scheme dynamically adapts via orientations to the optimized routing topology with low overhead. Experimental results show that the proposed framework reduces both layer usage and total wirelength while achieving a 45.709× runtime speedup.

ABSTRACT. Modern printed circuit boards are essential for enabling heterogeneous integration in AI and high-performance computing applications. However, the fiber weave effect necessitates any-angle routing to maintain signal integrity, while ultra-high-speed signaling requires the handling of complex design rules. Consequently, any-angle routing capable of satisfying complex differential pair requirements has become essential. Despite this need, existing automation tools struggle to address these requirements simultaneously, leaving engineers dependent on slow, manual design cycles. To bridge this gap, we propose ARC, the first any-angle routing framework for high-speed differential pairs that integrates complex design rules and obstacle avoidance. We propose a unified mathematical programming model to simultaneously optimize wirelength and ensure sufficient spacing for snaking patterns while strictly satisfying complex design rules. By employing length matching estimation and binary variable pruning techniques, our framework significantly reduces computational complexity. Experimental results demonstrate that our proposed framework consistently produces DRC clean solutions for complex benchmarks in only minutes, a process that typically requires hours or days of manual effort and thus dramatically accelerates the design cycle.

ABSTRACT. In modern printed circuit board (PCB) designs, legalization must re- solve overlaps among heterogeneous, irregularly shaped, and arbitrarily oriented components on double-sided boards while minimizing design rule violations (DRVs) and preserving placement quality. Existing con- straint graph-based methods rely on mixed-integer quadratic program- ming (MIQP), which treats geometric feasibility, clearance satisfaction, and displacement minimization as a single tightly coupled problem; this suffers from scalability limitations and, when no globally feasible so- lution is found within the runtime budget, often leaves the placement essentially unchanged in high-density designs. This paper proposes a consensus-optimization framework for progressive clearance-aware PCB legalization that decomposes the tightly coupled problem into coordinated subproblems—displacement minimization, geometric feasibility, and pad- level clearance enforcement—and drives them toward a globally consistent legal placement. The framework is realized through an Alternating Direc- tion Method of Multipliers (ADMM) scheme, in which a quadratic program minimizes displacement while a SAT-based minimum translation vector (MTV) subproblem resolves collisions and enforces net-aware, per-pad clearance directly on exact irregular geometries. Experimental results on industrial PCB benchmarks demonstrate that the proposed framework reduces geometric violations by 55.72% in overlap and 21.61% in clearance on average, significantly outperforming MIQP-based approaches and con- tinuing to improve highly congested cases where the discrete baseline stagnates. Although this comes at the cost of larger displacement and a moderate wirelength increase, the framework preserves placement quality and achieves lower average runtime.

ABSTRACT. Design rule checking (DRC) is essential for ensuring the manufacturability, yield, and reliability of modern VLSI layouts, yet accelerating DRC on large-scale designs remains challenging. In particular, efficient GPU acceleration of DRC for edge-to-edge distance checking is difficult, because existing methods still rely on edge-wise spatial range queries, whose highly irregular workloads are poorly matched to conventional GPU compute cores. In this paper, we present RT-DRC, a high-performance distance checking approach that leverages GPU ray-tracing (RT) cores, exploiting their specialization for such inherently irregular workloads. Our key insight is a local geometric formulation of distance checking that depends only on local edge geometry rather than global polygon topology, reducing the problem to an endpoint-in-strip test together with a non-trivial overlap test. Using this formulation, we map the 2D endpoint-in-strip test to a 3D ray-AABB query on GPU RT cores, thereby enabling an RT-core-driven pipeline for practical checks such as spacing and enclosure. To the best of our knowledge, RT-DRC is the first work to employ RT cores in the electronic design automation domain. Experimental results show that RT-DRC achieves 100% accuracy and delivers up to 10.02X speedup in spacing check and 3.32X in enclosure check over the state-of-the-art GPU baseline.

ABSTRACT. Multiple patterning lithography (MPL) is widely used in advanced technology nodes to improve patterning resolution and feature density. A critical step in MPL is layout decomposition, which assigns closely spaced features to different masks. Since layout decomposition for triple patterning lithography (TPL) and beyond is NP-hard, existing methods struggle to scale to large, dense layouts without sacrificing solution quality. To address this, we propose a novel layout decomposition framework based on unsatisfiable cores, which identify subsets of constraints that cannot be satisfied simultaneously. Our framework reuses and progressively minimizes these cores to localize regions that inevitably incur decomposition cost, and combines our proposed graph partitioning and refinement scheme for scalable handling of large layouts. Experimental results show that our framework outperforms state-of-the-art methods in solution quality and convergence speed, achieving up to an $80\times$ speedup over exact approaches.

ABSTRACT. Early digital bring-up is difficult when the process design kit (PDK) is incomplete and the target standard-cell library is unavailable or partially enabled. In this setting, the implementation flow cannot run reliably without a usable PDK, while library development cannot proceed effectively without an executable initial library. Existing methods usually assume one of these prerequisites and therefore do not directly address early bring-up under coupled PDK and library incompleteness. This paper formulates the problem as staged enablement and presents a design-technology co-optimization (DTCO)-oriented framework with three components: foundational cleanup for establishing a stable PDK baseline, minimal enablement for constructing an initial library, and progressive augmentation for budgeted library expansion under incomplete characterization. Experimental results show that the minimal enablement libraries use only 8.2\% of the cells in the full reference library on average, while limiting worst negative slack (WNS) degradation to at most 0.06~ns; four augmentation rounds further improve average post-P\&R WNS by 0.15~ns. These results indicate that early digital bring-up can start before target-library completion.

ABSTRACT. Chiplet integration enables scalable systems, but connecting independently designed Networks-on-Chip (NoCs) can introduce system-level deadlock. Virtual Network (VN) separation is flexible across protocols and topologies, yet global separation wastes virtual-channel and buffer resources. We present Minimal Virtual Network Separation (MinVNS), a configurable modular NoC framework that separates traffic only on links where inter-chip dependencies may arise. A VN-preserving allocation policy prevents inter-VN packet exchange and enables efficient non-atomic buffers. For deterministic routing, MinVNS derives the critical-link set offline; for path-uncertain routing, it conservatively uses global separation. We prove deadlock freedom compositionally and show that critical links are sparse in XY-routed meshes. Across three chiplet systems, relative to a prior VN-separation baseline, non-atomic buffering improves buffer utilization by up to 113.7 and, in VN-allocation-limited cases, saturation throughput by 8.3-13.6, while selective separation adds up to 65 throughput and 50.5 utilization over the global-separation baseline. Overall, MinVNS improves throughput over the prior VN-separation baseline by up to 68.8 and utilization by up to 197. Post-synthesis, MinVNS has 1.8 less area and 4.3 more power than a hardware baseline at comparable frequency.

ABSTRACT. Time-Division Multiplexing (TDM)-based circuit-switched networkson-chip (NoCs) provide predictable data movement, but their connectionsetup phase is highly vulnerable to runtime link unavailability. Before source-side ACK commitment secures a connection, an unavailable link can invalidate a probe’s tentative spatial path and temporally constrained slot sequence, traditionally forcing a costly source-side restart. We present RESCUE (Router-Enabled Setup Continuity Under Exceptions), a microarchitecture that provides bounded setup resilience by preserving and locally repairing precommit progress. RESCUE uses phase gating to reduce contention, allows in-flight branches to locally detour around unavailable links within a bounded budget, and shifts spatially feasible continuations to nearby future slots during setup when current slots are busy. Under high setup pressure and sustained link unavailability, RESCUE substantially outperforms parallel probing (PP) baselines. Compared with a launch-shaped PP baseline, full RESCUE improves the post-disruption setup-establishment rate by 13× (from 0.27% to 3.51%), increases Post-Disruption Committed Effective Throughput (ET) from 4.00 to 28.93 Gbps, and reduces control-packet overhead per successful setup by 83%. Furthermore, 28 nm RTL synthesis of a five-port RESCUE router achieves a maximum frequency of approximately 855 MHz with 19.19 mW total power, demonstrating the hardware feasibility of router-local setup recovery.

ABSTRACT. Quasi-Delay-Insensitive(QDI) Networks-on-Chip(NoC) offer robustness and energy efficiency for nanoscale chips, yet their adoption is hindered by the lack of high-fidelity, fast simulators for early-stage Design Space Exploration (DSE): existing synchronous/bundled-data simulators fail to capture QDI-specific timing behaviors, while post-layout simulations incur prohibitive runtime. To bridge this gap, this paper proposes a circuit-parameter-calibrated high-fidelity QDI NoC simulator as the core of our Q-COMPASS framework. First, to supply accurate physical parameters for simulator calibration, we optimize a heterogeneous QDI router design flow that supports fast module-level extraction of timing and power metrics without full backend implementation. Second, leveraging the calibrated simulator, we construct a two-stage fast architecture screening flow: candidate configurations are rapidly filtered using synthesis-level parameters, followed by post-layout validation of top candidates. Experiments on a 4×4 Mesh NoC show the simulator achieves > 94% accuracy in throughput and power estimation against post-layout results, with 50–200× speedup over traditional physical simulations. The screening flow preserves performance ranking consistency across 5 topology/routing combinations and varying VC/buffer configurations, reducing DSE turnaround from weeks to hours. This work transforms QDI NoC exploration from experience-driven guesswork to calibration-driven rapid screening.

ABSTRACT. Declared event semantics provide a low-cost hardware/software (HW/SW) interface for memory-hierarchy management in latency-critical systems with explicit typed event paths. Software knows which event a memory access serves, while the last-level cache (LLC) and memory controller cannot distinguish the stream. We preserve that boundary as a 5-bit event tag and evaluate two complementary consumers: a B+Tree isolates reuse-oriented LLC insertion, while real high-frequency trading traces exercise urgency-oriented memory-controller arbitration. At the LLC, EventSemRP maps the tag to an insertion priority using an 8-byte table. On a B+Tree it improves hit rate by 7.2 and 3.6 points over LRU and DRRIP at unchanged instructions per cycle (IPC), and reaches the widely used SHiP-PC baseline. The same fixed table remains robust across held-out distributions without retuning and applies from the first access, leading SHiP-PC by 11 points during predictor warm-up. At the memory controller, a 4-byte priority table uses the same tag to protect the critical EXECUTE event. Against a controller without quality of service (QoS), it changes throughput by at most ±0.35%, reduces packet-to-decision p99 latency by a mean of 9.5% across seven symbol-day traces, and lowers p99.9 on all seven. It matches per-core/requestor QoS at finer event granularity, while a selectivity probe avoids that baseline's IPC and noncritical-event penalties. The policy tables require 8 bytes per LLC and 4 bytes per controller (16 bytes in the evaluated one-LLC, two-controller system). The 5-bit sideband occupies bounded in-flight request state, adds no cache-line or coherence state, and turns an existing software distinction into a reusable memory-system interface.

ABSTRACT. Multi-core and many-core processors are widely deployed in servers and data centers, where mitigating coherence directory area overhead has long been a key challenge. Many prior studies have reduced directory overhead by optimizing sharer storage to shrink directory entry width. State-of-the-art sharer-storage optimization schemes rely on sufficiently provisioned directory entries, as they exploit underutilized directory space for compact sharer encoding. However, this premise no longer holds in entry-limited directory designs, where the number of directory entries is deliberately reduced to lower directory overhead. Under such constrained directory-entry budgets, existing sharer-storage optimization schemes incur substantial performance and bandwidth overhead due to severe directory-space contention, preventing the expected orthogonal benefits from being realized. The key challenge, therefore, is to enable efficient sharer tracking under constrained directory entries. In this paper, we observe that directory invalidation-triggering events tend to occur on recently shared cachelines. Based on this observation, we propose a novel directory structure, called the S-cache directory, to efficiently track sharers under limited directory entries. We further propose two sharer-precising mechanisms to minimize the additional bandwidth overhead of the S-cache directory. Experimental results show that, in a 64-core system with a 1/16⨉ directory scale, the S-cache directory reduces directory area overhead by 55.44% while incurring only 2.57% additional network traffic and negligible performance degradation relative to a full bit-vector directory. With the same area overhead, the S-cache directory significantly outperforms state-of-the-art designs in both performance and bandwidth.

ABSTRACT. Static Random Access Memory (SRAM) scaling in advanced nodes has stagnated with sharply rising cost, limiting on-chip cache capacity and worsening the “memory wall” in multicore processors. Chiplet-based heterogeneous integration enables cost-effective cache expansion, but die-to-die (D2D) latency, bandwidth limits, and interconnect congestion introduce unavoidable “Chiplet Tax” that degrades baseline performance. This work presents UACC (Universal Auxiliary Cache Chiplet), a partially decoupled auxiliary cache architecture that uses mature-process SRAM chiplets to scale capacity without sacrificing baseline speed. UACC keeps a latency-critical on-host cache for fast access and only allocates remote auxiliary capacity to workloads with net performance gain. To suppress the Chiplet Tax, we propose a congestion-aware 2D lookahead algorithm that dynamically allocates auxiliary cache by jointly assessing access patterns, D2D congestion, and workload utility. Evaluated on ChampSim across various cache budgets, D2D interfaces, and core scales, UACC delivers 86%–147% more high-speed cache at equal silicon cost relative to advanced-node monolithic designs. It improves performance by 8.92% on balanced workloads and up to 27.36% on cache-sensitive workloads, while outperforming state-of-the-art cache partitioning schemes and preserving baseline performance under light pressure.

ABSTRACT. Gate-level time-based power analysis must retain timestamped waveform events to localize glitches and attribute switching, internal, and leakage energy to reporting windows. Processing hundreds of millions to billions of value changes makes repeated analysis costly, while existing academic accelerators either discard event timing or stop at waveform ingestion. We present Anonymous, to our knowledge the first CPU-GPU heterogeneous engine for glitch-aware time-based gate-level power analysis with both VCD and FSDB inputs. Our engine resolves raw changes into ordered per-bit transitions, handles X states and same-timestamp updates, scales glitches by pulse width, and performs causal Liberty-arc attribution before assigning dynamic events and leakage intervals to windows. Format-specific CPU frontends converge into semantic-preserving tiles that bound the working set and feed shared GPU preparation, component kernels, and a deterministic five-stage internal-attribution chain with two-slot host--device overlap. Across industrial-scale benchmarks, the mean absolute relative error (MARE) of gate-cycle total energy against PrimeTime~PX is at most 0.008%, with a 99th-percentile error of at most 0.090%; the corresponding design-cycle MARE remains at most 0.001%. Our engine achieves average speedups of 54.0x for VCD and 15.5x for FSDB, even against PrimeTime PX's eight-process concurrent FSDB mode.

ABSTRACT. Accurate power estimation is a critical bottleneck in modern VLSI design flows, yet existing approaches face a fundamental trade-off between simulation accuracy and runtime. Graph neural networks (GNN)-based switching activity estimators have recently emerged as a way to obtain transferable average power estimation without gate-level simulation, but their inference throughput is constrained by the inherent sequentiality of levelized message passing through combinational logic. In this paper, we present GRACE, a novel GNN based switching activity estimator that addresses this bottleneck through a key contribution: a novel netlist representation paired with a dedicated GNN architecture that together replace sequential level-by-level propagation with a configurable parallel-first inference scheme. Like state-of-the-art GRANNITE, our approach represents gate-level netlists as graphs and infers combinational logic toggle rates directly from RTL simulation traces, remaining fully transferable to unseen netlists without retraining. Evaluated on a diverse set of benchmark circuits, GRACE achieves a combinational average power estimation error of 14.55% compared to 11.05% for GRANNITE, corresponding to 7.19% and 5.48% error on total average power respectively. However, GRACE significantly improves inference throughput, including a ~5.5X speedup on a RISC-V processor core, making it well suited for fast and scalable power estimation.

ABSTRACT. In this work, a flip-flop architecture enabling true in‑situ per‑bit clock gating, referred to as the Clock‑Gating Flip‑Flop (CGFF), is proposed. CGFF extends the classical 7474 topology while preserving its inherent advantage of single-phase clock (no requirements of clock-inverters), augmenting it with in-situ XOR clock-gating along with a scan de-racer. The proposed design achieves up to 77\% reduction in dynamic capacitance ($C_{dyn}$) compared with conventional transmission‑gate flip‑flops (TGFF). System‑level evaluations demonstrate up to 9\% reduction in block‑level power consumption when selectively converting only a subset of flip‑flops (those lacking explicit clock gating) to CGFF.

ABSTRACT. Flexible electronics enable conformable, disposable, sustainable, and ultra-low-cost computing platforms for smart patches, wearable health monitors, and intelligent packaging—features unattainable with rigid silicon CMOS. To retain programmability, state of the art is implementing general-purpose flexible RISC-V processors. Although flexible technologies offer limited computing capabilities, such applications require low data rates and thus require frequencies of only a few kilohertz. However, the costly memory cells in flexible electronics cause the register file (RF) to dominate processor area and power. We propose an RF based on compact, power-efficient DRAM-like gain cells (e.g., 3T1C), whose limited retention, however, may cause values to be lost during execution. Our refresh-aware compiler inserts refreshes as “dummy” instructions and formulates instruction scheduling as a constraint-programming problem, eliminating refresh circuitry. Compared to a state-of-the-art flexible microprocessor that uses a typical RF, the same micro- processor using our RF consumes 2.8×6 less power and area while across 46 benchmarks at 10 kHz, FlexRF ensures correct execution with approximately 2.65% latency overhead.

ABSTRACT. Maintaining power intent after an RTL ECO is laborious and error-prone. LLM agents increasingly use executable feedback to generate and repair design artifacts, but post-ECO power intent remains underexplored. One hierarchy change can invalidate domain bindings, crossing policies, retained state, and transition order at once; a latest-draft repair loop can also erase constraints that passed on an earlier turn. We propose \system, a checked LLM repair system for compound power-intent ECOs. \system constrains each proposal to bounded edits, returns the passed verification prefix and first unresolved contract, and admits a candidate only when deterministic checks preserve or extend verified progress. \bench evaluates the system on compact controls and a frozen 21-task Scale Track grounded in 1.4--9.9k lines of related public RTL per task. On 18 held-out ECOs, GLM-5.2 \system closes 12 tasks, versus 3 for a coding agent, 1 for an adapted AutoChip baseline, and 2 for a whole-IR control. DeepSeek-V4-Pro reproduces the direction at 7 versus 2. Compact controls reverse the action-size ranking, showing that PowerPilot's advantage appears in compound, large-context repair rather than from bounded edits alone.

ABSTRACT. As semiconductor technology scales down to the nanometer regime, the aging effect causes performance to degrade over time, making the characterization of the aging timing library crucial to robust circuit design. While machine learning (ML)-based methods have gained traction to mitigate the computational bottlenecks of exhaustive SPICE simulations, purely data-driven approaches require immense computational effort to generate training data. Furthermore, they inherently suffer from severe instability during extrapolation to unseen mission profiles. To overcome these fundamental bottlenecks, this paper proposes a novel physics-informed methodology to model complex aging-induced degradation, combined with a generative neural network approach. By fully exploiting the inherent similarities among different timing arcs, our framework achieves an average MAPE of 0.64% using only around 5% of the dataset, demonstrating superior extrapolation accuracy over conventional ML baselines, which lacks physics-informed constraints. In particular, this integration of physical priors demonstrates the capability of AI-driven solutions for characterization and timing applications.