Conference Room 4

Technical Session

Session 1E-1 (Jan 25 13:30-14:30) Die-to-Die and Board-Level Routing
Session 1E-2 (Jan 25 14:30-15:30) Manufacturing-Aware Design and Physical Verification
Session 2E (Jan 25 15:50-17:50) Low-Power Design, Power Estimation, and Power-Intent Optimization
Session 3E (Jan 26 11:00-12:00) Processor Architectures, Fault Injection, and System Security
Session 4E (Jan 26 13:00-15:00) Power Delivery, IR Drop, and Backside Design
Session 5E (Jan 26 15:20-17:20) 3D IC Floorplanning, Clocking, and Integration
Session 7E (Jan 27 10:20-12:20) Thermal and Mechanical Analysis and Optimization for 3D ICs and Advanced Packaging
Session 8E (Jan 27 13:20-15:20) Physical Unclonable Functions (PUFs) and Hardware Authentication
Session 9E (Jan 27 15:40-17:40) Reliable Heterogeneous Integration and Resilient AI Systems
Session 10E (Jan 28 10:20-12:20) Chiplet and Advanced Packaging Co-Optimization
Session 11E (Jan 28 13:20-15:20) LLM Agents and Algorithm Evolution for Physical Design
Session 12E (Jan 28 15:40-17:40) Timing Analysis, Prediction, and Optimization