ASP-DAC 2027: 32ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE

This page contains an index consisting of author-provided keywords.

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2.5D IC	PI-Aware Co-Layer Signal Routing and Power Plane Synthesis for Chiplet Interposers
2.5D ICs	SpectraPlace2.5D: Thermal-aware Chiplet Placement via Topology-guided MILP and Spectral Thermal Modeling
2.5D Integration	A Time-Encoded Analog Photonic Interposer for Energy-Efficient Integration of Analog Vision Sensors and Analog Accelerators
2.5D/3D IC	ThTrace: A High-Efficiency Displacement Field Simulator for Advanced Packaging
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3D Architecture	ATLAS: A Thermal-Aware 3D-Stacked Heterogeneous Architecture For LLM Multi-Turn Dialogue Serving DREAM:3D-stacked Token-wise Caching Diffusion Accelerator with Resource-Aware Mapping
3D diffusion policy	3DToMe: A Morton-Local and Interaction-Aware Token-Merging Accelerator for Efficient 3D Diffusion Policy Inference
3D IC	Logic Resynthesis for Cross-Die Dependencies in Hybrid Bonded 3D ICs A Comprehensive Clock Tree Synthesis with Useful Skew for 3D ICs DiffTherm: A Differentiable Thermal Formulation for Cell-Via Co-Optimization in 3D ICs A Two Stage Learning-Based Thermal-Aware Framework for 3D Fixed-Outline Soft-Module Floorplanning across Chip Sizes
3D integrated circuits	NaCo3D: Native and Compact 3D Floorplanning via Reinforcement Learning
3D integration	STRIDE: Sparse Thermal Reconstruction-Informed Differential Encoding for Thermally Stable 3D-Integrated Analog CIM
3D Macro Placement	MoL-PAM: Joint P/G TSV Planning and Macro Refinement for Memory-on-Logic 3D ICs via a Benders-Type Decomposition Heuristic
3D Memory	CCD-KV: Exploiting High-Density 3D Charge-Coupled Device Memory for Efficient On-Device LLM KV Caches
3D NAND Flash Memory	Reducing Read Retries by Skipping Similar Adjacent Read Voltage Parameters in 3D TLC NAND Flash
3D Printing	3D-VASE: Volumetric-Aware Scalable and Efficient Multi-Layer Design Synthesis for 3D-Printed Microfluidics
3D Reconstruction	HB-VGGT: Exploiting Head-Wise Complementary Redundancy for Efficient VGGT Inference on Hybrid-Bonded Architecture
3D Stacked Architecture	HB-VGGT: Exploiting Head-Wise Complementary Redundancy for Efficient VGGT Inference on Hybrid-Bonded Architecture
3D-stacked memory	Security-Aware Runtime Control for Mitigating Token-Acceptance Side Channels in PIM/3D-Memory Speculative LLM Inference Architectures
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4D Gaussian Splatting	TempoGS: Temporal Binning and Expiration-Aware Gaussian Loading for Memory-Efficient 4D Gaussian Splatting Acceleration
5
5G	Accelerating 5G NR Channel Estimation with a Complex-Arithmetic RISC-V Vector Extension
6
6T-Cell	NVM-in-Cache: Repurposing Commodity 6T SRAM Cache into NVM Analog Processing-in-Memory Engine using a Novel Compute-on-Powerline Scheme
A
Acceleration	Speculate, Verify, Repeat: Faster Decoding via Speculative KV Access and Verification Feedback DRS: Unified Fully Homomorphic Encryption Hardware Accelerator with Scheme-Switching MARCO: Markov Decision-based Adaptive Path Selection for Dynamic Layer Skipping
Accelerator	GD-PIM: A Low-Cost Gustavson Dataflow-Based Processing-in-Memory Architecture for SpGEMM TempoGS: Temporal Binning and Expiration-Aware Gaussian Loading for Memory-Efficient 4D Gaussian Splatting Acceleration ACED: An Algorithm–Hardware Co-Designed VLA Accelerator Exploiting Dynamic Weight-Precision Switching
access point co-optimization	APPlace: Co-Optimizing Device Locations and Access Points for Routing-Aware Analog Placement
ACIM exposure allocation	From Isolate to Co-Deployment Risk: Coupling-Aware Mapping for ACIM-Digital AI Accelerator
ACIM-digital heterogenous accelerator	From Isolate to Co-Deployment Risk: Coupling-Aware Mapping for ACIM-Digital AI Accelerator
Activity-Aware	Nexus: Activity-Aware Capacity-Constrained Neuron Partitioning for Multicore SNN Accelerators
Adaptation	Sample-Efficient Neural Compact Modeling for Design-Technology Co-Optimization Based on Process-Aware Adaptation
Adaptive effort scheduling	ARES: Adaptive Reasoning-Effort Steering for PPA- and Cost-Aware RTL Optimization with LLM Agents
Adaptive Exploration	GLARE: Generalizable Large-scale Analog Sizing via Reinforcement Learning with Covariance-Guided Exploration
Adaptive Inference	SHARD: Sub-Transformer Harnessing for Adaptive Resource-Aware Deployment
adaptive mutation	CircuitsDNA: Discovering Unconventional Multi-Accuracy Arithmetic Circuits via Evolutionary Synthesis
Adaptive Resource Orchestration	MAESTRO: Memo-Augmented Multi-Agent Engine for Self-Testing RTL Code Generation with Resource Orchestration
admission control	Reducing Cascaded Speech-to-Speech Latency via Speculative Prefilling and Incremental Cache Recovery
advance package	Network Flow Guided Routing and Force Directed Offset Via Placement for Advanced Chiplet Interconnect
advance packaging	A HeteroGNN-Based Hierarchical Co-Optimization Framework for Floorplanning and Routing in Advanced Packaging
Advanced Packaging	Encoding Symmetries into Operator Learning: Towards Accurate Multi-Physics Simulation in Advanced Packaging ThTrace: A High-Efficiency Displacement Field Simulator for Advanced Packaging SPLIT-MOR: Fast and Accurate Model Order Reduction for Nonlinear Transient Thermal Simulation of 2.5D/3D ICs
Agent Evolution	LU-Evolve: Agent-Based Algorithm Exploration for Sparse LU Solvers
Agentic AI	SCALE: Self-Supervised Constraint-Aware Layout Generation for Local P&R DRV Fixing at Advanced Nodes
Agentic EDA	AgenticPD: A Stage-Aware Agentic Framework for Closed-Loop Physical Design Optimization
Agentic hardware design	HINT: Toward an Executable Hardware-Intent Intermediate Representation Layer for LLM-Driven RTL Generation
Agentic-AI	CABAgent: A Cross-Stage Agentic Framework for Generating PDK-Compatible and Layout-Verified Analog Circuit Benchmarks
Agile EDA Framework	AutoIsing: An Automated Compiler for Programmable Ising Machine
Aging	Physics-Informed Generative Model Based Aging Library Characterization
Aging status estimation	TRAIT: Trajectory-based Robust Aging-aware Chip Identification for Traceability
Aging Trajectory	TRAIT: Trajectory-based Robust Aging-aware Chip Identification for Traceability
aging-aware timing	Cross-Family Graph Learning for Sparse Aging-Aware Timing Characterization of Standard-Cell Libraries
AI Accelerator	DFAC: Dataflow-Aided Intra-cluster Coalescer for AI Accelerators DSEAgent: Agentic AI Accelerator Design Space Exploration via Expert-level Reinforcement Learning
AI Accelerators	IMPACT: Constraint-Aware Search for Imperfectly Factorized Accelerator Mappings
AI Engine	CHAIDO: Open-Source Simulation-Based Fault Injection for the AMD Versal AI Engine
AI for EDA	HINT: Toward an Executable Hardware-Intent Intermediate Representation Layer for LLM-Driven RTL Generation
AI4EDA	DeepResub: Towards Learned Logic Optimization Operators PP2Tree: Learning-Guided Frontier Partitioning for Scalable Parallel Logic Synthesis
AIG	DeepResub: Towards Learned Logic Optimization Operators
Algorithm Discovery	VPR-Evolve: Multi-Agent-Driven Algorithm Evolution for FPGA Place and Route
Algorithm Hardware Co-Design	Cross-Layer Co-Designed In-Memory Hyperdimensional Computing Accelerator for Proteomics at the Edge
Algorithm-Based Fault Tolerance (ABFT)	Observability-Aware Runtime Reliability for MZI-Based Optical Neural Networks
Algorithm-Hardware Co-Optimization	ScaleLUT: A Fully-Parallel Configurable LUT-Based Accelerator for Real-Time Multi-Scale Super-Resolution
Alignment-Aware Quantization	AlignQuant: Alignment First Two-Stage Integer Microscaling Format for Systolic Native LLM Inference
Alternating Direction Method of Multipliers	A Consensus-Optimization Framework for Progressive Clearance-Aware PCB Legalization with Irregular Components
Alternative to PUFs	Lightweight Key-Based Hardware Device-ID Authentication: A Reliable, ML-Resistant Alternative to PUFs
Analog & Mixed-Signal Design	CAS: A Ferroelectric Compute-in-Memory Annealer for Sparse Combinatorial Optimization Problems
Analog Accelerator	A Time-Encoded Analog Photonic Interposer for Energy-Efficient Integration of Analog Vision Sensors and Analog Accelerators
Analog Circuit	CktHVR: A Convergence-Aware GNN-VLM Hypothesize-Verify-Refine Framework for Analog Circuit Topology Rectification
Analog circuit design automation	CABAgent: A Cross-Stage Agentic Framework for Generating PDK-Compatible and Layout-Verified Analog Circuit Benchmarks
Analog circuit sizing	Archive-Guided MOEA/D for Constrained Many-Objective Analog Circuit Sizing LMSACO: LLM-Guided Multi-Objective State-Adaptive Analog Circuit Sizing Optimization GLARE: Generalizable Large-scale Analog Sizing via Reinforcement Learning with Covariance-Guided Exploration
Analog compute-in-memory	ABNAT: Attention-Based Noise-Aware Training for Robust Transformers on Analog Compute-in-Memory Systems NANQ: Noise-Aware Mixed-Precision Non-Uniform Quantization for Neural Networks on Analog Compute-in-Memory STRIDE: Sparse Thermal Reconstruction-Informed Differential Encoding for Thermally Stable 3D-Integrated Analog CIM InfoCIM: An Information-Theoretic Framework for Modeling and Design of Noise-Limited Analog CIM
Analog design automation	Archive-Guided MOEA/D for Constrained Many-Objective Analog Circuit Sizing ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Exploration
Analog design optimization	CRAFT: Constraint-Guided Region-Adaptive Search over Broad Design Spaces for High-Dimensional Analog Circuit Sizing
Analog in-memory computing	NVM-in-Cache: Repurposing Commodity 6T SRAM Cache into NVM Analog Processing-in-Memory Engine using a Novel Compute-on-Powerline Scheme
Analog Layout	An Explainable Analog/Mixed-Signal Routing Agent using Deterministic Constraint-Conflict Diagnosis
analog layout automation	APPlace: Co-Optimizing Device Locations and Access Points for Routing-Aware Analog Placement
analog noise	From Isolate to Co-Deployment Risk: Coupling-Aware Mapping for ACIM-Digital AI Accelerator
Analog Photonic Interposer	A Time-Encoded Analog Photonic Interposer for Energy-Efficient Integration of Analog Vision Sensors and Analog Accelerators
analog placement	APPlace: Co-Optimizing Device Locations and Access Points for Routing-Aware Analog Placement
analog-to-digital converter	CalNet: Temperature-Robust ADC Calibration via Learned BGR Behavior and LUT Correction
Analog-to-Digital Converter (ADC)	OMNI-DC: One-shot Multi-input Neural-Inference-Based Data Converter for Analog Computation-in-Memory
Analog/Mixed-Signal Design Automation	GLARE: Generalizable Large-scale Analog Sizing via Reinforcement Learning with Covariance-Guided Exploration
analytical placement	Structure-Preserving Density Modeling for Electrostatics-Based Analytical Placement APPlace: Co-Optimizing Device Locations and Access Points for Routing-Aware Analog Placement From Communities to Coordinates: Hierarchical Clustering–Guided Placement for Large-Scale FPGAs
Ancilla allocation	Reducing T-depth in quantum circuits through adaptive allocation of ancillae between T-par and H-gadgets
and-inverter graph	Node Reduction via Targeted ODC-Based Wire Additions for AIG Optimization Inverter Redistribution through Self-Dual and Self-Anti-Dual Function Transformation
And-Inverter Graphs	aigverse: A Unified Infrastructure for Machine Learning-Driven Logic Synthesis DeepResub: Towards Learned Logic Optimization Operators
ANF	TensorLUT: Exact Batched RTL Simulation via ANF-Lifted Tensor-Core GEMM
Anomaly detection	PARFuzzer: Path-Aware RTL Fuzzing with Controlled BTB Conflict Injection for Branch-Predictor Security Validation
Anonymization	Multi-Feature Demographic Decoupling via LPC Cross-Synthesis for Privacy-Preserving Audio Anonymization
Any-Angle PCB Routing	ARC: Any-Angle PCB Routing with Obstacle Avoidance under Complex Design Rules
Approximate circuits	AX-AGENT: Contract-Driven Closed-Loop Framework for Error-Bounded PPA-Aware Approximate RTL Generation SWAPPER: Dynamic Operand Swapping in Non-commutative Approximate Circuits for Online Error Reduction
Approximate Computing	MATE: Model-Assisted Trade-off Exploration for Quality-Aware Approximate Matrix Computing Cross-Layer Co-Designed In-Memory Hyperdimensional Computing Accelerator for Proteomics at the Edge SWAPPER: Dynamic Operand Swapping in Non-commutative Approximate Circuits for Online Error Reduction CircuitsDNA: Discovering Unconventional Multi-Accuracy Arithmetic Circuits via Evolutionary Synthesis
Approximate Nearest-Neighbor Search	HAVEN: High-Bandwidth Flash Augmented Vector ENgine for Large-Scale Approximate Nearest-Neighbor Search Acceleration
Architecture & System Design	CAS: A Ferroelectric Compute-in-Memory Annealer for Sparse Combinatorial Optimization Problems
Architecture Description Languages(ADL)	Multi-modal LLM-Driven Generation of Processor Performance Simulators from Datasheet Specifications
architecture search	TADA: Technology Aware DNN Accelerator Performance and Energy Estimator
Architecture Stealing	TraceMorph: Real-Trace-Guided Execution-Level Obfuscation for RAPL-Based DNN Architecture Protection
area-energy tradeoff	TADA: Technology Aware DNN Accelerator Performance and Energy Estimator
Arithmetic Optimization	GA2-CT: GPU-Accelerated Genetic Algorithm for Low-Power Compression-Tree Rewiring
Artificial intelligence	Enabling Efficient Quantized LLM Inference on Floating-Point CGRAs via Lightweight Integer Extensions UniCASE: A Unified 16-bit Floating Point Format with Criticality-Aware Selective ECC for Efficient DNN Protection
assembly order	Chiplet Assembly and Pre-Bond Qualification Planning for Heterogeneous Integrated Systems
Associative search	Low-Power Approximate MRAM CAM with Dynamic-Reference for HDC Associative Search
Asymmetric Numeral Systems	Efficient End-to-End Hyperprior-Based Learned Image Compression on Edge GPUs via Thread-Level Parallel Entropy Coding
Asynchronous NoC	Q-COMPASS: A Circuit-Calibrated Simulation Framework for QDI NoC Architecture Exploration
Attention Acceleration	SSR-VAR: Exploiting Spatial- and Scale-aware Redundancy for Lightweight Inference of Visual Autoregressive Models DeferKV: Long-Context LLM Attention Acceleration with Per-Token Scale Folding and Bank-Local Softmax on PIM
Attention Distillation	ABNAT: Attention-Based Noise-Aware Training for Robust Transformers on Analog Compute-in-Memory Systems
Attention Sparsity	PSD-CIM:A Computing-In-Memory Attention Accelerator with Predictor-Free Sparsity search and Distribution Shaping
audio-based pain detection	Multi-Feature Demographic Decoupling via LPC Cross-Synthesis for Privacy-Preserving Audio Anonymization
Authentication	Lightweight Key-Based Hardware Device-ID Authentication: A Reliable, ML-Resistant Alternative to PUFs
Automated Hardware Debugging	WaveAce: Analyzing the Root Cause of SoC Test Failures via LLMs' Direct Waveform Inspection
Automated RTL Code Generation	MAESTRO: Memo-Augmented Multi-Agent Engine for Self-Testing RTL Code Generation with Resource Orchestration
Autonomous LLM	HLSClaw: Bringing Vibe Coding to High-Level Synthesis through Skill-Based Agentic Harness
AX-AGENT	AX-AGENT: Contract-Driven Closed-Loop Framework for Error-Bounded PPA-Aware Approximate RTL Generation
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Backside clock mesh	Clock Distribution Network with Backside Clock Mesh in BSPDN Architecture
backside metal	Grad-BSS: Differentiable Optimization for Full-Stack Backside Signal Routing
backside power distribution network	Power Network Topology Optimization for Top Dies in Backside-Powered F2F 3D ICs
bandgap reference	CalNet: Temperature-Robust ADC Calibration via Learned BGR Behavior and LUT Correction
Batch normalization	BLINK: Batch NormaLization-based INtegrity ChecKpoints for In-Situ Detection and Mitigation of Diverse Weight Corruptions in DNN Accelerators
battery management systems	CalNet: Temperature-Robust ADC Calibration via Learned BGR Behavior and LUT Correction
Bayesian neural networks	SURE-AI: Single-pass Uncertainty Estimation for Reliable Edge AI Accelerators
Bayesian optimization	LMSACO: LLM-Guided Multi-Objective State-Adaptive Analog Circuit Sizing Optimization
Beam-search	Operation-Aware Twisting of Folded Bit-Lines for Crosstalk Cancellation in Wafer-Bonded DRAM
behavioral divergence	SpecLens: LLM-Based Verilog Generation with Specification-Derived Constraints via Behavioral Divergence
Benchmark generation	CABAgent: A Cross-Stage Agentic Framework for Generating PDK-Compatible and Layout-Verified Analog Circuit Benchmarks
Binary Attention	PSD-CIM:A Computing-In-Memory Attention Accelerator with Predictor-Free Sparsity search and Distribution Shaping
Biochips	3D-VASE: Volumetric-Aware Scalable and Efficient Multi-Layer Design Synthesis for 3D-Printed Microfluidics
bioinspired AI	CABLE: A Cached Bidirectional and Multi-lane Item Memory\\for Efficient Hyperdimensional Computing
Bit-flip attack	BLINK: Batch NormaLization-based INtegrity ChecKpoints for In-Situ Detection and Mitigation of Diverse Weight Corruptions in DNN Accelerators
Block-scaled quantization	MX-like Tensor Core for LLM Inference with NPU Integration via Hardware-Software Co-Design Exploration
Bottleneck analysis	A System-Level Typed-Graph Environment for Traceable Cycle-Level Co-Design of Heterogeneous AI Accelerators
Budget-aware search	SymbOperon: Composable and Cost-Efficient Symbolic Reasoning Operators for Neuro-Symbolic Edge Perception
Buffering	Obstacle-Aware Timing-Driven Buffer Insertion via Feasible Shallow-Light Topology Reconstruction
Bump-level Dynamic IR drop prediction	A Dual-Branch GAT-MLP Framework for Efficient Bump-Level Dynamic IR Drop Prediction in Flip-Chip Packages
Burn-in test	TRAIT: Trajectory-based Robust Aging-aware Chip Identification for Traceability
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C++	aigverse: A Unified Infrastructure for Machine Learning-Driven Logic Synthesis
Cache	DFAC: Dataflow-Aided Intra-cluster Coalescer for AI Accelerators
cache coherence	S-cache Directory: Efficient Sharer Tracking for Entry-Constrained Coherence Directories
cache replacement	Declared Event Semantics: Cross-Layer Memory-Hierarchy Co-Design for Latency-Critical Systems
Caching Diffusion	DREAM:3D-stacked Token-wise Caching Diffusion Accelerator with Resource-Aware Mapping
calibration	CalNet: Temperature-Robust ADC Calibration via Learned BGR Behavior and LUT Correction
Capacity-Constrained	Nexus: Activity-Aware Capacity-Constrained Neuron Partitioning for Multicore SNN Accelerators
Cascaded diffusion model	SiliDiff: Post-Silicon Thermal and Power Reconstruction from Sparse Sensing with a Cascaded Conditional Diffusion Model
cell clustering	Placement Guidance Generation via Timing-Aware Hypergraph Partitioning and Multi-Criteria Cluster Selection
Certified machine learning	CertIR: Certified Static IR-Drop Estimation with Physics-Anchored Neural Correction
CFMB	3D-VASE: Volumetric-Aware Scalable and Efficient Multi-Layer Design Synthesis for 3D-Printed Microfluidics
CGRA	Enabling Efficient Quantized LLM Inference on Floating-Point CGRAs via Lightweight Integer Extensions Resource-Efficient Heterogeneous CGRA for Kernels with Control Flow
Channel Estimation	Accelerating 5G NR Channel Estimation with a Complex-Arithmetic RISC-V Vector Extension
Channel modeling	InfoCIM: An Information-Theoretic Framework for Modeling and Design of Noise-Limited Analog CIM
Charge-Coupled Device	CCD-KV: Exploiting High-Density 3D Charge-Coupled Device Memory for Efficient On-Device LLM KV Caches
Chemically Amplified Resist	ResistONet: Cascade Operator Network for Photoresist Simulation
Chip identification	TRAIT: Trajectory-based Robust Aging-aware Chip Identification for Traceability
Chiplet	QoS Analysis for UCIe-based Cross-die Communication using Network Calculus SpectraPlace2.5D: Thermal-aware Chiplet Placement via Topology-guided MILP and Spectral Thermal Modeling Network Flow Guided Routing and Force Directed Offset Via Placement for Advanced Chiplet Interconnect PI-Aware Co-Layer Signal Routing and Power Plane Synthesis for Chiplet Interposers UACC: A Chiplet-Based Auxiliary Cache for Cost-Effective Performance Scaling in Multicore Processors ActRAM: A Hybrid Analog/Digital Action-Expert Accelerator Architecture for Vision-Language-Action Models
chiplet placement	Thermal-Aware Chiplet Placement Integrating Evolutionary Reinforcement Learning and Monte Carlo Tree Search Thermal-Aware Chiplet Placement and Shape Co-Optimization under D2D Interconnect Constraints for 2.5D Integration
Chiplet-based System	MinVNS: Minimal Virtual Network Separation for Deadlock Avoidance in Modular Network-on-Chip
chiplets	Chiplet Assembly and Pre-Bond Qualification Planning for Heterogeneous Integrated Systems
CiM Simulator	UnO-NeSy: Optimizing Neuro-Symbolic Computing with Unified FeFET Based In-Memory System
Circuit Block Diagram Parsing	FlowMapper: Detection-Guided Topology Reconstruction of Circuit Block Diagrams
circuit design	A Resource-Efficient Quantum Circuit for Fixed-Point Logarithm Operations with Analytical Error Bounds
Circuit Simulation	LU-Evolve: Agent-Based Algorithm Exploration for Sparse LU Solvers
Circuit switching	RESCUE: Runtime Setup Resilience for TDM-Based Circuit-Switched NoCs
Circuit verification	GAS: GPU Accelerated Schema Aware Exact Subcircuit Matching for Large-Scale Circuits
CKKS	PFHE: Partial Fully Homomorphic Encryption on CNN Inference
Clearance Constraints	A Consensus-Optimization Framework for Progressive Clearance-Aware PCB Legalization with Irregular Components
Clifford+T	A Resource-Efficient Quantum Circuit for Fixed-Point Logarithm Operations with Analytical Error Bounds
Clock Gating	Anonymous: Fast Clock-Aware Timing Propagation for Complex Clock Logic and Constraints with State Flow Graph Abstraction
clock skew scheduling	A Comprehensive Clock Tree Synthesis with Useful Skew for 3D ICs
clock tree synthesis	XCTS: Cross-Tier-Aware Differentiable Clock Tree Synthesis for 3D Integrated Circuits A Comprehensive Clock Tree Synthesis with Useful Skew for 3D ICs
Clock-Aware Timing Propagation	Anonymous: Fast Clock-Aware Timing Propagation for Complex Clock Logic and Constraints with State Flow Graph Abstraction
Clock-Gating	An In-situ Self Clock-Gated 7474 Style Scan-Mux-D Low Power Flip-Flop
CNN	Learning-Guided Adaptive Cell-Wise Optimization for Mixed-Size Global Placement MemFLoRA: Memory-Floor LoRA for CNN Adaptation at the Edge PFHE: Partial Fully Homomorphic Encryption on CNN Inference
CNN–GNN co-design	ACCORD-IC: Contract-Checked Relation Transactions for Low-Bit Dynamic CNN–GNN Inference
Co-optimization	Device-Circuit Co-Optimization of SOT-MRAM with Accurate PPA Evaluation for Edge AI Training
co-packaged optics	MIBIFI: Differentiable Electronic–Photonic–Thermal Co-Simulation for Co-Packaged Optics Designs
Coarse-grained reconfigurable architectures	From Compiler to Silicon: A Co-Design Approach to High-Performance CGRAs
Compact Model	Sample-Efficient Neural Compact Modeling for Design-Technology Co-Optimization Based on Process-Aware Adaptation
Compilation	Resource-Efficient Heterogeneous CGRA for Kernels with Control Flow
Compiler	Fine-Grained Compiler-Assisted Hardening via Tolerant-Output Analysis for SDC–Runtime Trade-offs
compiler optimization	Compiler-driven Optimizations for Efficient Host and Near-DRAM Co-Execution
Computation-in-Memory (CIM)	OMNI-DC: One-shot Multi-input Neural-Inference-Based Data Converter for Analog Computation-in-Memory
Computational Lithography	MaxIM: A Plug-and-Play Maxwellian Engine via Interface Modification for Thick-Mask Lithography
compute near memory	Compiler-driven Optimizations for Efficient Host and Near-DRAM Co-Execution
compute-in-memory	NOVA-CIM: Noise- and Correlation-Tolerant Stochastic Interfaces for Analog Compute-in-Memory ASSERT: Adaptive Stochastic Sampling for Robust Diffusion Models on Analog Compute-in-Memory Hardware RACE-FFN: Runtime-Adaptive Co-Execution in a Heterogeneous SA-CIM Architecture for Efficient MoE-FFN Acceleration A XNOR-SRAM-Based Computing-in-Memory Macro for Memory-Augmented Neural Networks SURE-AI: Single-pass Uncertainty Estimation for Reliable Edge AI Accelerators ActRAM: A Hybrid Analog/Digital Action-Expert Accelerator Architecture for Vision-Language-Action Models
Compute-in-memory (CiM)	UnO-NeSy: Optimizing Neuro-Symbolic Computing with Unified FeFET Based In-Memory System An Area-Efficient CIM-Based Ising Annealer with Folded Mapping and Cooling-Scheduled Parallel Swaps Strategy for Large-Scale Traveling Salesman Problem
Compute-near-Memory	CCD-KV: Exploiting High-Density 3D Charge-Coupled Device Memory for Efficient On-Device LLM KV Caches
Computing-in-memory	PSD-CIM:A Computing-In-Memory Attention Accelerator with Predictor-Free Sparsity search and Distribution Shaping TACO: Topology-Aware Compression via Hardware–Software Co-Design for Robust CiM-Accelerated Edge RAG Retrieval
Conductance based neuron model	SpikeFold: An FPGA-based Neuromorphic Processor with DSP Optimization and Parallel Weight Update STDP
Configurable accelerator	ScaleLUT: A Fully-Parallel Configurable LUT-Based Accelerator for Real-Time Multi-Scale Super-Resolution
configurable accuracy	CircuitsDNA: Discovering Unconventional Multi-Accuracy Arithmetic Circuits via Evolutionary Synthesis
Constrained many-objective optimization	Archive-Guided MOEA/D for Constrained Many-Objective Analog Circuit Sizing
Constrained multi-objective optimization	LMSACO: LLM-Guided Multi-Objective State-Adaptive Analog Circuit Sizing Optimization
Constrained Optimization	ARC: Any-Angle PCB Routing with Obstacle Avoidance under Complex Design Rules
Constraint Learning	Decompose Transform Refine Verify: A new approach for scalable formal verification
Constraint programming	From Compiler to Silicon: A Co-Design Approach to High-Performance CGRAs
Constraint solving	Hardware-Retargetable Grammar-Based NAS from Declarative Device Specifications
Constraint-driven Routing	An Explainable Analog/Mixed-Signal Routing Agent using Deterministic Constraint-Conflict Diagnosis
Content-addressable memory	Low-Power Approximate MRAM CAM with Dynamic-Reference for HDC Associative Search
Control-Flow Kernels	Resource-Efficient Heterogeneous CGRA for Kernels with Control Flow
Coordinate Rotation Digital Computer (CORDIC) ； Activation Function ；	PDG-CORDIC: A Posit-Decode-Guided Low-Latency CORDIC for Activation Function
cosine aligned guidance	ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Exploration
cost	Chiplet Assembly and Pre-Bond Qualification Planning for Heterogeneous Integrated Systems
Cost-aware design optimization	ARES: Adaptive Reasoning-Effort Steering for PPA- and Cost-Aware RTL Optimization with LLM Agents
Countermeasure	Staggered Instruction-Fetch Duplication: A Lightweight Processor-Level Countermeasure Against Fault Injection
CPU microarchitecture	PaFeDSE: Pareto-Feedback-Guided Microarchitecture Design Space Exploration for Efficient Pareto Search
CPU-GPU co-design	NgramRL: Accelerating RL Post-Training for Structured Generation via Rollout-Aware N-gram Speculative Decoding
CPU-GPU heterogeneous acceleration	Anonymous: A CPU-GPU Heterogeneous Engine for Glitch-Aware Time-Based Gate-Level Power Analysis
CPU-GPU Orchestration	SPICE: Speculative Prefetching with Low-Rank Expert Surrogates and Heterogeneous Orchestration for MoE Inference Acceleration
Cross-corner timing prediction	AnchorGNN: Cross-PVT Corner Timing Prediction via Anchor-Guided Graph Learning and STA-Aware Propagation
Cross-design knowledge transfer	ARES: Adaptive Reasoning-Effort Steering for PPA- and Cost-Aware RTL Optimization with LLM Agents
Cross-Family Generalization	DISSECT: Cross-Family RTL Trojan Localization by Auditing Structural–Functional Disagreement
cross-family prediction	Cross-Family Graph Learning for Sparse Aging-Aware Timing Characterization of Standard-Cell Libraries
cross-layer coupling	From Isolate to Co-Deployment Risk: Coupling-Aware Mapping for ACIM-Digital AI Accelerator
cross-layer modeling	CoSim: A Cross-Layer Simulation Framework for System-Hardware Co-Design of LLM Inference
Cross-module synchronization	Atomic and Hierarchy-Safe Cross-Module Undo/Redo for Analog IC Design
Crosstalk	Operation-Aware Twisting of Folded Bit-Lines for Crosstalk Cancellation in Wafer-Bonded DRAM
Cryptosystem	Investigation of Karatsuba Algorithm for Large-Bitwidth Modular Multiplication
cubes	Cube-based Finite-State-Machine Extraction via SAT Generalizations
Curvilinear Mask Optimization	Curvilinear OPC via Diffeomorphic Deformation
cycle-accurate	TensorLUT: Exact Batched RTL Simulation via ANF-Lifted Tensor-Core GEMM
Cycle-level simulation	A System-Level Typed-Graph Environment for Traceable Cycle-Level Co-Design of Heterogeneous AI Accelerators
D
d2d interconnect	Thermal-Aware Chiplet Placement and Shape Co-Optimization under D2D Interconnect Constraints for 2.5D Integration
Dataflow Optimization	FLARE: A Dataflow-Aware and Scalable Hardware Architecture for Neural-Hybrid Scientific Lossy Compression DPSQ : Dynamic Partial Sum Quantization with Mixed Granularity
Datapath Graphs	VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts
Datapath Optimization	GA2-CT: GPU-Accelerated Genetic Algorithm for Low-Power Compression-Tree Rewiring
deadline-aware scheduling	Progressive Computation Scheduling for Deadline-Critical Tasks in Hierarchical Edge Networks
Deadlock-Avoidance	MinVNS: Minimal Virtual Network Separation for Deadlock Avoidance in Modular Network-on-Chip
Declarative hardware specification	Hardware-Retargetable Grammar-Based NAS from Declarative Device Specifications
Deep learning accelerator	Taming Irregular Sparsity with a Regular Systolic Array for Efficient DNN Training
deep learning compiler	Compiler-driven Generation of Domain-Specific AI Hardware Accelerators for Edge Devices
delay bound	QoS Analysis for UCIe-based Cross-die Communication using Network Calculus
Density modeling	Structure-Preserving Density Modeling for Electrostatics-Based Analytical Placement
Design Automation	CONTOUR: Continuous Topology Search for System-Level RFICs via Bi-Level Optimization and Neural-Analytical Co-Modeling PARFuzzer: Path-Aware RTL Fuzzing with Controlled BTB Conflict Injection for Branch-Predictor Security Validation
Design Automation Workflow	MAESTRO: Memo-Augmented Multi-Agent Engine for Self-Testing RTL Code Generation with Resource Orchestration
Design Exploration	Resource-Efficient Heterogeneous CGRA for Kernels with Control Flow
Design for Manufacturability	An Efficient Layout Decomposition Framework via Unsatisfiable Core
Design guidelines	InfoCIM: An Information-Theoretic Framework for Modeling and Design of Noise-Limited Analog CIM
Design Retargeting	GLARE: Generalizable Large-scale Analog Sizing via Reinforcement Learning with Covariance-Guided Exploration
Design Rule Check	EvoDRC: A Self-Evolving Agentic Framework for Automated DRC Violation Repair
Design Rule Checking	RT-DRC: Accelerating Design Rule Checking Using GPU Ray-Tracing Cores
design space exploration	MX-like Tensor Core for LLM Inference with NPU Integration via Hardware-Software Co-Design Exploration ChronosDSE: Stability-Aware Design Space Exploration for GPGPUs DSEAgent: Agentic AI Accelerator Design Space Exploration via Expert-level Reinforcement Learning MATE: Model-Assisted Trade-off Exploration for Quality-Aware Approximate Matrix Computing FADiff: Fusion-Aware Differentiable Optimization for DNN Scheduling on Tensor Accelerators Q-COMPASS: A Circuit-Calibrated Simulation Framework for QDI NoC Architecture Exploration CoD-MiCo: Co-Design of Mixed-Compression RISC-V Extensions for Neural Networks on FPGAs CoSim: A Cross-Layer Simulation Framework for System-Hardware Co-Design of LLM Inference SymbOperon: Composable and Cost-Efficient Symbolic Reasoning Operators for Neuro-Symbolic Edge Perception Opening the Black Box: A Self-Correcting LLM Agent for EDA Toolchains Based on Source-Code Analysis RASP-LLM: Radiation-Aware Design-Space Exploration of Precision and Selective Protection for On-Orbit LLM Inference Compiler-driven Generation of Domain-Specific AI Hardware Accelerators for Edge Devices From Compiler to Silicon: A Co-Design Approach to High-Performance CGRAs
Design space exploration (DSE)	MAP-DSE: A Fast Performance Simulator for Large-Scale Microarchitectural Design Space Exploration
Design Space Exploration(DSE)	Multi-modal LLM-Driven Generation of Processor Performance Simulators from Datasheet Specifications
Design Space Optimization	Phase-Aware Monte Carlo Tree Search with LLM-Guided Proposal for Multi-Objective Physical Design Tuning
Design Synthesis	3D-VASE: Volumetric-Aware Scalable and Efficient Multi-Layer Design Synthesis for 3D-Printed Microfluidics
Design Technology Co-Optimization	Sample-Efficient Neural Compact Modeling for Design-Technology Co-Optimization Based on Process-Aware Adaptation Multi-Output-Guided Transistor Network Synthesis and Layout for Sequential Cells
Design-for-manufacturing	OptiClear: Differentiable Curvilinear Design Rule Legalization for Inverse-Designed Photonic Device
Design-space exploration	FUSE: Five-Block MVM Energy Comparison
detailed placement	Wirelength-Driven Mixed-Cell-Height Detailed Placement with Multi-Row Cell Relocation
Device degradation	TRAIT: Trajectory-based Robust Aging-aware Chip Identification for Traceability
Diagram-to-Graph Conversion	FlowMapper: Detection-Guided Topology Reconstruction of Circuit Block Diagrams
die-to-die	UACC: A Chiplet-Based Auxiliary Cache for Cost-Effective Performance Scaling in Multicore Processors
die-to-die interconnection	QoS Analysis for UCIe-based Cross-die Communication using Network Calculus
Die-to-die routing	Efficient Concurrent Die-to-Die Routing with Teardrop and Offset-Via Awareness
differentiable formulation	DiffTherm: A Differentiable Thermal Formulation for Cell-Via Co-Optimization in 3D ICs
differentiable optimization	XCTS: Cross-Tier-Aware Differentiable Clock Tree Synthesis for 3D Integrated Circuits OptiClear: Differentiable Curvilinear Design Rule Legalization for Inverse-Designed Photonic Device
differentiable simulation	MIBIFI: Differentiable Electronic–Photonic–Thermal Co-Simulation for Co-Packaged Optics Designs
Differential encoding	STRIDE: Sparse Thermal Reconstruction-Informed Differential Encoding for Thermally Stable 3D-Integrated Analog CIM
Differential Pair	Operation-Aware Twisting of Folded Bit-Lines for Crosstalk Cancellation in Wafer-Bonded DRAM
Differential Pair Routing	ARC: Any-Angle PCB Routing with Obstacle Avoidance under Complex Design Rules
Diffusion Accelerator	DREAM:3D-stacked Token-wise Caching Diffusion Accelerator with Resource-Aware Mapping
Diffusion models	ASSERT: Adaptive Stochastic Sampling for Robust Diffusion Models on Analog Compute-in-Memory Hardware
diffusion policy	EdgeDAE: Acceleration of Diffusion Action Experts for Real-Time Physical AI with Tiny VLAs on Edge FPGA-GPU Systems
Diffusion Transformer	APRQ: Adaptive Prediction-Driven Residual Quantization Accelerator for Diffusion Transformers
Digital Nonlinear Oscillator	Power and EM Side-Channel Leakage Mitigation in Oscillator-Based PUFs via Sampling Techniques
Directed Topology Reconstruction	FlowMapper: Detection-Guided Topology Reconstruction of Circuit Block Diagrams
directory organization	S-cache Directory: Efficient Sharer Tracking for Entry-Constrained Coherence Directories
Displacement field Simulation	ThTrace: A High-Efficiency Displacement Field Simulator for Advanced Packaging
Distribution Shaping	PSD-CIM:A Computing-In-Memory Attention Accelerator with Predictor-Free Sparsity search and Distribution Shaping
DNN Accelerator	TADA: Technology Aware DNN Accelerator Performance and Energy Estimator FADiff: Fusion-Aware Differentiable Optimization for DNN Scheduling on Tensor Accelerators
DNN accelerator reliability	BLINK: Batch NormaLization-based INtegrity ChecKpoints for In-Situ Detection and Mitigation of Diverse Weight Corruptions in DNN Accelerators
DNN architecture protection	TraceMorph: Real-Trace-Guided Execution-Level Obfuscation for RAPL-Based DNN Architecture Protection
DNN inference	CRANE: Criticality-Aware Concurrent Neural Inference on Heterogeneous Edge Platforms
Domain-Specific ISA extension	Accelerating 5G NR Channel Estimation with a Complex-Arithmetic RISC-V Vector Extension
DRAM	GD-PIM: A Low-Cost Gustavson Dataflow-Based Processing-in-Memory Architecture for SpGEMM DRAC: A Static Analysis for DRAM Row Activation Count Toward Efficient Processing-in-Memory Code Generation From DRAM Architecture to Protocol State: A Resource-Grounded Executable Semantics for LPDDR5
DRAM-PIM	CRISP: Paged Sparse Attention on DRAM-PIM with Row-Band-Aware KV Allocation and Frame-Derived Addressing
DRC Violation	FormalPCell: Formal DRC Verification of Parameterized Layout Cells via Symbolic Interpretation and SMT Solving
Dynamic graph construction	ACCORD-IC: Contract-Checked Relation Transactions for Low-Bit Dynamic CNN–GNN Inference
dynamic IR drop prediction	PDN-Aware Graph Transformer-based Dynamic IR Drop Prediction with Criticality-Guided Subgraph Construction
Dynamic Sparse Graph Management	PACT: A Runtime Contract for Sparse-Topology Updates in GPU-Accelerated Timing ECOs
Dynamic Swap	SWAPPER: Dynamic Operand Swapping in Non-commutative Approximate Circuits for Online Error Reduction
E
Early-Stage Digital Bring-Up	A DTCO-Oriented Early Digital Bring-Up Framework under Incomplete PDK and Standard-Cell Assets
ECC	Cross-Bank ECC Strategy for LLM-Oriented Hybrid-Bonded 3D DRAM Architecture
EDA	GRACE: GRAph-based power Consumption Estimator with Parallel Switching Activity Propagation VPR-Evolve: Multi-Agent-Driven Algorithm Evolution for FPGA Place and Route HINT: Toward an Executable Hardware-Intent Intermediate Representation Layer for LLM-Driven RTL Generation
EDA for Emerging Technologies	qLevelPlace: A Level-Based Placement Framework for RSFQ Circuits
EDA Tool	Atomic and Hierarchy-Safe Cross-Module Undo/Redo for Analog IC Design
edge A	SURE-AI: Single-pass Uncertainty Estimation for Reliable Edge AI Accelerators
Edge AI	EdgeDAE: Acceleration of Diffusion Action Experts for Real-Time Physical AI with Tiny VLAs on Edge FPGA-GPU Systems Prefix-Branch Software Co-Design for Random Forest Acceleration on Embedded Hybrid TCAMs MemFLoRA: Memory-Floor LoRA for CNN Adaptation at the Edge
Edge AI training	Device-Circuit Co-Optimization of SOT-MRAM with Accurate PPA Evaluation for Edge AI Training
edge computing	Progressive Computation Scheduling for Deadline-Critical Tasks in Hierarchical Edge Networks
edge CPU-GPU systems	TriM: Efficient MoE Inference on Edge CPU-GPU Systems via Fused Quantization and Sensitivity-Guided Scheduling
Edge GPU	Efficient End-to-End Hyperprior-Based Learned Image Compression on Edge GPUs via Thread-Level Parallel Entropy Coding
edge inference	TADA: Technology Aware DNN Accelerator Performance and Energy Estimator CCD-KV: Exploiting High-Density 3D Charge-Coupled Device Memory for Efficient On-Device LLM KV Caches
Edge Intelligence	SHARD: Sub-Transformer Harnessing for Adaptive Resource-Aware Deployment
Edge perception	SymbOperon: Composable and Cost-Efficient Symbolic Reasoning Operators for Neuro-Symbolic Edge Perception
Edge-to-Edge Distance Checking	RT-DRC: Accelerating Design Rule Checking Using GPU Ray-Tracing Cores
EdgeAI deployment	Hardware-Retargetable Grammar-Based NAS from Declarative Device Specifications
Efficient AI	T3R: Training-Free Two-Stage Token Refinement Towards Efficient and Robust VLA Models
Efficient LLM inference	NgramRL: Accelerating RL Post-Training for Structured Generation via Rollout-Aware N-gram Speculative Decoding
Elastic Neural Networks	SHARD: Sub-Transformer Harnessing for Adaptive Resource-Aware Deployment
Electromagnetic Fault Injection	Reasoning and Modeling of Instruction Corruption of MCU under EMFI
electromagnetic simulation	EMPUF: A Leakage-Controlled Pre-Fabrication Benchmark for PCB Spectral Fingerprints
Electronic Design Automation	CktHVR: A Convergence-Aware GNN-VLM Hypothesize-Verify-Refine Framework for Analog Circuit Topology Rectification Learning-Augmented Multilevel Hypergraph Partitioning with Net-Level Cut Priors CoEvoP&R: Co-Evolving Placement Objectives with Routing Feedback via Large Language Models FlowMapper: Detection-Guided Topology Reconstruction of Circuit Block Diagrams Opening the Black Box: A Self-Correcting LLM Agent for EDA Toolchains Based on Source-Code Analysis
Electronic-photonic comparison	FUSE: Five-Block MVM Energy Comparison
electronic-photonic-thermal co-simulation	MIBIFI: Differentiable Electronic–Photonic–Thermal Co-Simulation for Co-Packaged Optics Designs
Electrostatics-based placement	Structure-Preserving Density Modeling for Electrostatics-Based Analytical Placement
Elmore Delay Extension	RAPID: An Efficient and Accurate Ratio-Based Analytical Proxy for Interconnect Delay
Embedded Systems	Prefix-Branch Software Co-Design for Random Forest Acceleration on Embedded Hybrid TCAMs
Embeddings	Functional Retrieval for Resynthesis-Robust Hardware Trojan Detection in Gate-Level Netlists
Embodied AI	T3R: Training-Free Two-Stage Token Refinement Towards Efficient and Robust VLA Models
Emerging Technologies	CAS: A Ferroelectric Compute-in-Memory Annealer for Sparse Combinatorial Optimization Problems
Emerging Technology	Fanout-Multiplicity-Aware Technology Mapping for Multi-Output Superconducting Logic qLevelPlace: A Level-Based Placement Framework for RSFQ Circuits
Endpoint slack prediction	AnchorGNN: Cross-PVT Corner Timing Prediction via Anchor-Guided Graph Learning and STA-Aware Propagation
Energy efficiency	From Compiler to Silicon: A Co-Design Approach to High-Performance CGRAs
Energy modeling	FUSE: Five-Block MVM Energy Comparison
Engineering Change Order	EvoDRC: A Self-Evolving Agentic Framework for Automated DRC Violation Repair
Engineering Change Order (ECO)	PowerPilot: Preserving Verified Progress in LLM-Based Power-Intent ECO Repair
Entropy Coding	Efficient End-to-End Hyperprior-Based Learned Image Compression on Edge GPUs via Thread-Level Parallel Entropy Coding
entropy filtering	SpecLens: LLM-Based Verilog Generation with Specification-Derived Constraints via Behavioral Divergence
Equality Saturation	Adaptive BTOR2 Reformulation via Solver-Aware Equality Saturation
Equivalent-circuit acceleration	SRAM Bitcell-Peripheral Co-Optimization Under Array-Level Yield Constraints
error bounds	A Resource-Efficient Quantum Circuit for Fixed-Point Logarithm Operations with Analytical Error Bounds
Error budget	AX-AGENT: Contract-Driven Closed-Loop Framework for Error-Bounded PPA-Aware Approximate RTL Generation
Error Correcting Code (ECC)	UniCASE: A Unified 16-bit Floating Point Format with Criticality-Aware Selective ECC for Efficient DNN Protection
error modeling	MATE: Model-Assisted Trade-off Exploration for Quality-Aware Approximate Matrix Computing
ESOP synthesis	TensorLUT: Exact Batched RTL Simulation via ANF-Lifted Tensor-Core GEMM
Etch Proximity Correction	EtchMO: A Differentiable Etch Model for Mask Optimization
Etch Simulation Model	EtchMO: A Differentiable Etch Model for Mask Optimization
Evolutionary algorithm	Archive-Guided MOEA/D for Constrained Many-Objective Analog Circuit Sizing
executable specifications	From DRAM Architecture to Protocol State: A Resource-Grounded Executable Semantics for LPDDR5
Expert Offloading	AHEAD: A Fast and Efficient MoE Speculative Decoding System via Dynamic Draft–Verify Coordination
External memory	Memory-Aware Design-Space Exploration for Multi-Threaded HLS Accelerators
Extreme Edge	FlexRF: Retention-Aware Compilation for Low-power and Area-Efficient Flexible Microprocessors using IGZO DRAM-style Register File
F
face-to-face 3D IC	Power Network Topology Optimization for Top Dies in Backside-Powered F2F 3D ICs
Fault Injection	CHAIDO: Open-Source Simulation-Based Fault Injection for the AMD Versal AI Engine Fine-Grained Compiler-Assisted Hardening via Tolerant-Output Analysis for SDC–Runtime Trade-offs
Fault injection attack	Staggered Instruction-Fetch Duplication: A Lightweight Processor-Level Countermeasure Against Fault Injection
Fault Model	Reasoning and Modeling of Instruction Corruption of MCU under EMFI
Fault tolerance	Weight-Stationary Fault Recovery via Neuron Tuning in RRAM-Based CIM Neuromorphic Accelerators UniCASE: A Unified 16-bit Floating Point Format with Criticality-Aware Selective ECC for Efficient DNN Protection
Fault-tolerant quantum computing	Reducing T-depth in quantum circuits through adaptive allocation of ancillae between T-par and H-gadgets
FeFET	UnO-NeSy: Optimizing Neuro-Symbolic Computing with Unified FeFET Based In-Memory System
few-shot learning	A XNOR-SRAM-Based Computing-in-Memory Macro for Memory-Augmented Neural Networks
FHE	PFHE: Partial Fully Homomorphic Encryption on CNN Inference
Finite Difference Method	ThTrace: A High-Efficiency Displacement Field Simulator for Advanced Packaging
Finite State Machine	REASON: RNG-Aware Finite-State Machines for Hardware-Realistic Stochastic Nonlinear Approximation
fixed-point arithmetic	A Resource-Efficient Quantum Circuit for Fixed-Point Logarithm Operations with Analytical Error Bounds
Flexible Electronics	FlexRF: Retention-Aware Compilation for Low-power and Area-Efficient Flexible Microprocessors using IGZO DRAM-style Register File
Flip Flop Design	Multi-Output-Guided Transistor Network Synthesis and Layout for Sequential Cells
Flip-chip packages	A Dual-Branch GAT-MLP Framework for Efficient Bump-Level Dynamic IR Drop Prediction in Flip-Chip Packages
Flip-Flop	An In-situ Self Clock-Gated 7474 Style Scan-Mux-D Low Power Flip-Flop
Floating point format	UniCASE: A Unified 16-bit Floating Point Format with Criticality-Aware Selective ECC for Efficient DNN Protection
Floorplanning	NaCo3D: Native and Compact 3D Floorplanning via Reinforcement Learning A Two Stage Learning-Based Thermal-Aware Framework for 3D Fixed-Outline Soft-Module Floorplanning across Chip Sizes A HeteroGNN-Based Hierarchical Co-Optimization Framework for Floorplanning and Routing in Advanced Packaging
Folded Bit-line	Operation-Aware Twisting of Folded Bit-Lines for Crosstalk Cancellation in Wafer-Bonded DRAM
folded mapping	An Area-Efficient CIM-Based Ising Annealer with Folded Mapping and Cooling-Scheduled Parallel Swaps Strategy for Large-Scale Traveling Salesman Problem
formal equivalence	Formally Verified Contract-Aware Replacement of Ready/Valid Microarchitectures
Formal hardware verification	ACCORD-IC: Contract-Checked Relation Transactions for Low-Bit Dynamic CNN–GNN Inference
Formal Verification	SLED-IFV: Solver-Validated LLM-Guided Decomposition for Scalable Hardware Information-Flow Verification FormalPCell: Formal DRC Verification of Parameterized Layout Cells via Symbolic Interpretation and SMT Solving Decompose Transform Refine Verify: A new approach for scalable formal verification
FPGA	CoD-MiCo: Co-Design of Mixed-Compression RISC-V Extensions for Neural Networks on FPGAs VPR-Evolve: Multi-Agent-Driven Algorithm Evolution for FPGA Place and Route Power and EM Side-Channel Leakage Mitigation in Oscillator-Based PUFs via Sampling Techniques
FPGA acceleration	EdgeDAE: Acceleration of Diffusion Action Experts for Real-Time Physical AI with Tiny VLAs on Edge FPGA-GPU Systems
FPGA accelerator	MfSpGEMM: Merger-Free Row-Wise SpGEMM with Bitmap Accumulation and HBM-Aware Mapping
FPGA LLM Acceleration	Less is More: KV Cache Scheduling for Bandwidth-Efficient LLM Inference on FPGA
FPGA neural-network acceleration	ACCORD-IC: Contract-Checked Relation Transactions for Low-Bit Dynamic CNN–GNN Inference
FPGA placement	From Communities to Coordinates: Hierarchical Clustering–Guided Placement for Large-Scale FPGAs
FPGA security	Secure Reconfiguration for Multi-Tenant FPGAs
FPGA-based accelerator	SpikeFold: An FPGA-based Neuromorphic Processor with DSP Optimization and Parallel Weight Update STDP
FSM extraction	Cube-based Finite-State-Machine Extraction via SAT Generalizations
Functional Identifiability	Functionality-Aware Is Not Synthesis-Invariant: An End-to-End Audit of Circuit-GNN Representations
Functional Retrieval	Functional Retrieval for Resynthesis-Robust Hardware Trojan Detection in Gate-Level Netlists
Fused ALU Micro-Operations	Enabling Energy-Efficient TinyML Inference via Fused Tensor Architecture
Fused GEMM-ALU Execution	Enabling Energy-Efficient TinyML Inference via Fused Tensor Architecture
Fuzzing	PARFuzzer: Path-Aware RTL Fuzzing with Controlled BTB Conflict Injection for Branch-Predictor Security Validation
G
GAAFET	Sample-Efficient Neural Compact Modeling for Design-Technology Co-Optimization Based on Process-Aware Adaptation
Gate Cut	Scalable Quantum Circuits Partitioning via Shortest-Path Search and Circuit Transformation
Gate Reordering	Scalable Quantum Circuits Partitioning via Shortest-Path Search and Circuit Transformation
Gate-level	GRACE: GRAph-based power Consumption Estimator with Parallel Switching Activity Propagation
Gate-level Netlists	Functionality-Aware Is Not Synthesis-Invariant: An End-to-End Audit of Circuit-GNN Representations Functional Retrieval for Resynthesis-Robust Hardware Trojan Detection in Gate-Level Netlists
Gate-level power analysis	Anonymous: A CPU-GPU Heterogeneous Engine for Glitch-Aware Time-Based Gate-Level Power Analysis
GEMM	Enabling Efficient Quantized LLM Inference on Floating-Point CGRAs via Lightweight Integer Extensions
genetic algorithm	CircuitsDNA: Discovering Unconventional Multi-Accuracy Arithmetic Circuits via Evolutionary Synthesis
Genetic algorithms	IMPACT: Constraint-Aware Search for Imperfectly Factorized Accelerator Mappings
GF(2)	TensorLUT: Exact Batched RTL Simulation via ANF-Lifted Tensor-Core GEMM
Glitch-aware power analysis	Anonymous: A CPU-GPU Heterogeneous Engine for Glitch-Aware Time-Based Gate-Level Power Analysis
GPGPU	ChronosDSE: Stability-Aware Design Space Exploration for GPGPUs
GPU	DFAC: Dataflow-Aided Intra-cluster Coalescer for AI Accelerators TensorLUT: Exact Batched RTL Simulation via ANF-Lifted Tensor-Core GEMM Fast Delay-oriented Logic Optimization with Parallel SOP Generation GARDEN: GPU-Accelerated Rapid Divisor Extraction
GPU acceleration	GAS: GPU Accelerated Schema Aware Exact Subcircuit Matching for Large-Scale Circuits DiffTherm: A Differentiable Thermal Formulation for Cell-Via Co-Optimization in 3D ICs AccTTS: Characterizing and Optimizing Workload Dynamics in Test-Time Scaling RAP: Resource‑Aware Scheduling for GPU Accelerated Hypergraph Partitioning
GPU microarchitecture	BB8: Blocking Buffer for breaking head-of-line stalling in GPGPUs via Instruction Bypassing.
GPU Ray-Tracing Cores	RT-DRC: Accelerating Design Rule Checking Using GPU Ray-Tracing Cores
GPU Stall Reduction	BB8: Blocking Buffer for breaking head-of-line stalling in GPGPUs via Instruction Bypassing.
GPU Static Timing Analysis	PACT: A Runtime Contract for Sparse-Topology Updates in GPU-Accelerated Timing ECOs
GPU-accelerated EDA	Anonymous: A CPU-GPU Heterogeneous Engine for Glitch-Aware Time-Based Gate-Level Power Analysis
GPU-Accelerated Optimization	GA2-CT: GPU-Accelerated Genetic Algorithm for Low-Power Compression-Tree Rewiring
GPU-accelerated placement	ALTO: Joint Track-Height and Placement Optimization for Non-Integer Mixed-Cell-Height Designs
Gradient descent	Gradient-Guided Thermal-Aware Timing Robustness Optimization Under Temperature Inversion
gradient-based optimization	MIBIFI: Differentiable Electronic–Photonic–Thermal Co-Simulation for Co-Packaged Optics Designs
Grammar-based search space	Hardware-Retargetable Grammar-Based NAS from Declarative Device Specifications
Graph Algorithms	FRESHPart: Feedback-Reshaped Spectral Embedding for Hypergraph Partitioning
graph learning	Cross-Family Graph Learning for Sparse Aging-Aware Timing Characterization of Standard-Cell Libraries
Graph Neural Network	GRACE: GRAph-based power Consumption Estimator with Parallel Switching Activity Propagation DISSECT: Cross-Family RTL Trojan Localization by Auditing Structural–Functional Disagreement
Graph Neural Networks	CktHVR: A Convergence-Aware GNN-VLM Hypothesize-Verify-Refine Framework for Analog Circuit Topology Rectification Functionality-Aware Is Not Synthesis-Invariant: An End-to-End Audit of Circuit-GNN Representations Learning-Augmented Multilevel Hypergraph Partitioning with Net-Level Cut Priors aigverse: A Unified Infrastructure for Machine Learning-Driven Logic Synthesis AnchorGNN: Cross-PVT Corner Timing Prediction via Anchor-Guided Graph Learning and STA-Aware Propagation A Dual-Branch GAT-MLP Framework for Efficient Bump-Level Dynamic IR Drop Prediction in Flip-Chip Packages VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts Functional Retrieval for Resynthesis-Robust Hardware Trojan Detection in Gate-Level Netlists
Graph Partitioning	Nexus: Activity-Aware Capacity-Constrained Neuron Partitioning for Multicore SNN Accelerators
H
H-gadget	Reducing T-depth in quantum circuits through adaptive allocation of ancillae between T-par and H-gadgets
Hardware	Lightweight Key-Based Hardware Device-ID Authentication: A Reliable, ML-Resistant Alternative to PUFs
hardware acceleration	DPSQ : Dynamic Partial Sum Quantization with Mixed Granularity CircuitsDNA: Discovering Unconventional Multi-Accuracy Arithmetic Circuits via Evolutionary Synthesis
Hardware Accelerator	Hit-SME: A High-throughput Hybrid SNN-based MLP Engine for Neural Volume Rendering 3DToMe: A Morton-Local and Interaction-Aware Token-Merging Accelerator for Efficient 3D Diffusion Policy Inference
hardware architecture and accelerators	CABLE: A Cached Bidirectional and Multi-lane Item Memory\\for Efficient Hyperdimensional Computing
Hardware Description Language (HDL)	ML-AccelBench: A Benchmark for Evaluating LLM-Based ML Accelerator RTL Generation
Hardware Fuzzing	When Fuzzing Meets Understanding: LLM-Driven Semantic Test Generation for RTL Verification
hardware generation	Compiler-driven Generation of Domain-Specific AI Hardware Accelerators for Edge Devices
Hardware Model Checking	Adaptive BTOR2 Reformulation via Solver-Aware Equality Saturation Decompose Transform Refine Verify: A new approach for scalable formal verification
Hardware noise	ASSERT: Adaptive Stochastic Sampling for Robust Diffusion Models on Analog Compute-in-Memory Hardware
Hardware Non-Idealities	ABNAT: Attention-Based Noise-Aware Training for Robust Transformers on Analog Compute-in-Memory Systems
Hardware Security	GREG: A Graphical Static Analysis Framework for Early Hardware Security Verification EMPUF: A Leakage-Controlled Pre-Fabrication Benchmark for PCB Spectral Fingerprints PARFuzzer: Path-Aware RTL Fuzzing with Controlled BTB Conflict Injection for Branch-Predictor Security Validation SLED-IFV: Solver-Validated LLM-Guided Decomposition for Scalable Hardware Information-Flow Verification A Lightweight Microring-Resonator PUF Design for Silicon Photonics Transceivers DRS: Unified Fully Homomorphic Encryption Hardware Accelerator with Scheme-Switching Security-Aware Runtime Control for Mitigating Token-Acceptance Side Channels in PIM/3D-Memory Speculative LLM Inference Architectures A Reliability-Enhanced SOT-MTJ PUF with Obfuscated Write-Back for Physical-State Exposure Mitigation Power and EM Side-Channel Leakage Mitigation in Oscillator-Based PUFs via Sampling Techniques Functional Retrieval for Resynthesis-Robust Hardware Trojan Detection in Gate-Level Netlists
Hardware Trojan	DISSECT: Cross-Family RTL Trojan Localization by Auditing Structural–Functional Disagreement
Hardware Verification	When Fuzzing Meets Understanding: LLM-Driven Semantic Test Generation for RTL Verification Spec2Plan: An LLM-Powered Framework for Comprehensive Verification Plan Generation Towards Leveraging the Software Ecosystem to Facilitate Hardware Verification
Hardware-aware NAS	Hardware-Retargetable Grammar-Based NAS from Declarative Device Specifications
hardware-software co-design	Declared Event Semantics: Cross-Layer Memory-Hierarchy Co-Design for Latency-Critical Systems APRQ: Adaptive Prediction-Driven Residual Quantization Accelerator for Diffusion Transformers TACO: Topology-Aware Compression via Hardware–Software Co-Design for Robust CiM-Accelerated Edge RAG Retrieval Compiler-driven Generation of Domain-Specific AI Hardware Accelerators for Edge Devices From Compiler to Silicon: A Co-Design Approach to High-Performance CGRAs SSR-VAR: Exploiting Spatial- and Scale-aware Redundancy for Lightweight Inference of Visual Autoregressive Models
Hardware–Algorithm Co-Design	AlignQuant: Alignment First Two-Stage Integer Microscaling Format for Systolic Native LLM Inference
Harness Engineering	HLSClaw: Bringing Vibe Coding to High-Level Synthesis through Skill-Based Agentic Harness
HBM	A Waferscale Memory Architecture for Efficient LLM Inference
HBM address mapping	MfSpGEMM: Merger-Free Row-Wise SpGEMM with Bitmap Accumulation and HBM-Aware Mapping
HBT-aware netlist optimization	Logic Resynthesis for Cross-Die Dependencies in Hybrid Bonded 3D ICs
Health monitoring	Multi-Feature Demographic Decoupling via LPC Cross-Synthesis for Privacy-Preserving Audio Anonymization
Heterogeneous 3D ICs	3D-Syn: 3D-aware Synthesis Flow for Heterogeneous LogicFolding 3D ICs
Heterogeneous AI accelerators	A System-Level Typed-Graph Environment for Traceable Cycle-Level Co-Design of Heterogeneous AI Accelerators
Heterogeneous Architecture	RACE-FFN: Runtime-Adaptive Co-Execution in a Heterogeneous SA-CIM Architecture for Efficient MoE-FFN Acceleration Resource-Efficient Heterogeneous CGRA for Kernels with Control Flow
Heterogeneous computing	GAS: GPU Accelerated Schema Aware Exact Subcircuit Matching for Large-Scale Circuits
Heterogeneous edge computing	CRANE: Criticality-Aware Concurrent Neural Inference on Heterogeneous Edge Platforms
heterogeneous graph neural networks	A HeteroGNN-Based Hierarchical Co-Optimization Framework for Floorplanning and Routing in Advanced Packaging
heterogeneous integration	Chiplet Assembly and Pre-Bond Qualification Planning for Heterogeneous Integrated Systems
Heterogeneous interconnects	Timing-Aware Routing and Heterogeneous TDM Assignment for Multi-Level FPGA-Based Emulation Systems
heterogeneous scheduling	TriM: Efficient MoE Inference on Edge CPU-GPU Systems via Fused Quantization and Sensitivity-Guided Scheduling
Hierarchical analog IC design	Atomic and Hierarchy-Safe Cross-Module Undo/Redo for Analog IC Design
hierarchical edge networks	Progressive Computation Scheduling for Deadline-Critical Tasks in Hierarchical Edge Networks
High-Bandwidth Flash	HAVEN: High-Bandwidth Flash Augmented Vector ENgine for Large-Scale Approximate Nearest-Neighbor Search Acceleration
high-bandwidth memory	MfSpGEMM: Merger-Free Row-Wise SpGEMM with Bitmap Accumulation and HBM-Aware Mapping
high-dimensional circuits	HOIST: A High-Order Interaction Surrogate for Sample-Efficient High-Sigma Yield Estimation in High-Dimensional Circuits
high-dimensional optimization	CRAFT: Constraint-Guided Region-Adaptive Search over Broad Design Spaces for High-Dimensional Analog Circuit Sizing
high-frequency trading	Declared Event Semantics: Cross-Layer Memory-Hierarchy Co-Design for Latency-Critical Systems
High-level synthesis	HLSClaw: Bringing Vibe Coding to High-Level Synthesis through Skill-Based Agentic Harness HINT: Toward an Executable Hardware-Intent Intermediate Representation Layer for LLM-Driven RTL Generation ACCORD-IC: Contract-Checked Relation Transactions for Low-Bit Dynamic CNN–GNN Inference Memory-Aware Design-Space Exploration for Multi-Threaded HLS Accelerators
High-Performance Scientific Computing	FLARE: A Dataflow-Aware and Scalable Hardware Architecture for Neural-Hybrid Scientific Lossy Compression
High-sigma yield estimation	HOIST: A High-Order Interaction Surrogate for Sample-Efficient High-Sigma Yield Estimation in High-Dimensional Circuits
Homomorphic Encryption	DRS: Unified Fully Homomorphic Encryption Hardware Accelerator with Scheme-Switching
HW-SW co-design	MX-like Tensor Core for LLM Inference with NPU Integration via Hardware-Software Co-Design Exploration
Hybrid bonding	Logic Resynthesis for Cross-Die Dependencies in Hybrid Bonded 3D ICs
Hybrid Bonding DRAM	Cross-Bank ECC Strategy for LLM-Oriented Hybrid-Bonded 3D DRAM Architecture
Hyperdimensional Computing	CABLE: A Cached Bidirectional and Multi-lane Item Memory\\for Efficient Hyperdimensional Computing Low-Power Approximate MRAM CAM with Dynamic-Reference for HDC Associative Search Online Open-World Wafer Defect Discovery using Hyperdimensional Computing Cross-Layer Co-Designed In-Memory Hyperdimensional Computing Accelerator for Proteomics at the Edge
hypergraph clustering	From Communities to Coordinates: Hierarchical Clustering–Guided Placement for Large-Scale FPGAs
Hypergraph Partitioning	FRESHPart: Feedback-Reshaped Spectral Embedding for Hypergraph Partitioning Learning-Augmented Multilevel Hypergraph Partitioning with Net-Level Cut Priors CCPart: Timing-Aware Multi-Level Partitioning for Multi-FPGA Systems with Incremental Timing Analysis Placement Guidance Generation via Timing-Aware Hypergraph Partitioning and Multi-Criteria Cluster Selection RAP: Resource‑Aware Scheduling for GPU Accelerated Hypergraph Partitioning
I
IC3/PDR	Formally Verified Contract-Aware Replacement of Ready/Valid Microarchitectures
IGZO eDRAM	FlexRF: Retention-Aware Compilation for Low-power and Area-Efficient Flexible Microprocessors using IGZO DRAM-style Register File
ILP	An Explainable Analog/Mixed-Signal Routing Agent using Deterministic Constraint-Conflict Diagnosis
In Memory Computing	Cross-Layer Co-Designed In-Memory Hyperdimensional Computing Accelerator for Proteomics at the Edge
In-memory computing	FUSE: Five-Block MVM Energy Comparison
In-pixel Computing	A Time-Encoded Analog Photonic Interposer for Energy-Efficient Integration of Analog Vision Sensors and Analog Accelerators
inference simulation	CoSim: A Cross-Layer Simulation Framework for System-Hardware Co-Design of LLM Inference
information flow tracking	GREG: A Graphical Static Analysis Framework for Early Hardware Security Verification
information-flow verification	SLED-IFV: Solver-Validated LLM-Guided Decomposition for Scalable Hardware Information-Flow Verification
Information-theoretic modeling	InfoCIM: An Information-Theoretic Framework for Modeling and Design of Noise-Limited Analog CIM
Instruction set simulation (ISS)	MAP-DSE: A Fast Performance Simulator for Large-Scale Microarchitectural Design Space Exploration
Instruction Space Modeling	Between The Cracks: Uncovering Illegal-Instruction Bugs in RISC-V Processors by Exploring the Unified Encoding Space
instruction-level parallelism	BB8: Blocking Buffer for breaking head-of-line stalling in GPGPUs via Instruction Bypassing.
Interactive Routing	An Explainable Analog/Mixed-Signal Routing Agent using Deterministic Constraint-Conflict Diagnosis
Interconnect Delay Modeling	RAPID: An Efficient and Accurate Ratio-Based Analytical Proxy for Interconnect Delay
Intermediate representation	HINT: Toward an Executable Hardware-Intent Intermediate Representation Layer for LLM-Driven RTL Generation
Interposer	PI-Aware Co-Layer Signal Routing and Power Plane Synthesis for Chiplet Interposers
inverse design	A Unified Framework for Circuit-Aware Tapped-Inductor Inverse Design with Topology-Aware Sequence Representation MIBIFI: Differentiable Electronic–Photonic–Thermal Co-Simulation for Co-Packaged Optics Designs
Inverters	Inverter Redistribution through Self-Dual and Self-Anti-Dual Function Transformation
IoT inference	IMPACT: IoT SNN Inference with a Metadata-Guided Pulse-Width Control Architecture for Conductance-Time Weight Representation in RRAM
IR drop	Cross-Layer Reinforcement Learning for Power-Via Optimization in Multilayer RDL Power/Ground Plane Synthesis
IR-Drop Optimization	MoL-PAM: Joint P/G TSV Planning and Macro Refinement for Memory-on-Logic 3D ICs via a Benders-Type Decomposition Heuristic
Irregular-Shaped Components	A Consensus-Optimization Framework for Progressive Clearance-Aware PCB Legalization with Irregular Components
Ising annealer	An Area-Efficient CIM-Based Ising Annealer with Folded Mapping and Cooling-Scheduled Parallel Swaps Strategy for Large-Scale Traveling Salesman Problem
Ising Machine	AutoIsing: An Automated Compiler for Programmable Ising Machine
J
joint computation--communication scheduling	Progressive Computation Scheduling for Deadline-Critical Tasks in Hierarchical Edge Networks
K
Karatsuba Algorithm	Investigation of Karatsuba Algorithm for Large-Bitwidth Modular Multiplication
Key-Based	Lightweight Key-Based Hardware Device-ID Authentication: A Reliable, ML-Resistant Alternative to PUFs
Key-Value Cache	CCD-KV: Exploiting High-Density 3D Charge-Coupled Device Memory for Efficient On-Device LLM KV Caches
Knowledge Grounding	Opening the Black Box: A Self-Correcting LLM Agent for EDA Toolchains Based on Source-Code Analysis
Krylov subspace methods	CertIR: Certified Static IR-Drop Estimation with Physics-Anchored Neural Correction
KV Cache	Speculate, Verify, Repeat: Faster Decoding via Speculative KV Access and Verification Feedback KV3D: KV Cache-Centric Monolithic 3D-Stackable DRAM-Based Accelerator for LLM Serving CRISP: Paged Sparse Attention on DRAM-PIM with Row-Band-Aware KV Allocation and Frame-Derived Addressing
KV cache management	Reducing Cascaded Speech-to-Speech Latency via Speculative Prefilling and Incremental Cache Recovery
KV Cache Quantization	AlignQuant: Alignment First Two-Stage Integer Microscaling Format for Systolic Native LLM Inference
KV Cache Reduction	SSR-VAR: Exploiting Spatial- and Scale-aware Redundancy for Lightweight Inference of Visual Autoregressive Models
KV Cache Scheduling	Less is More: KV Cache Scheduling for Bandwidth-Efficient LLM Inference on FPGA
KV-cache	Multi-Agent LLM Serving with SSD-Based KV-Cache Offloading
KV-cache quantization	DeferKV: Long-Context LLM Attention Acceleration with Per-Token Scale Folding and Bank-Local Softmax on PIM
L
Lab-On-a-Chip	3D-VASE: Volumetric-Aware Scalable and Efficient Multi-Layer Design Synthesis for 3D-Printed Microfluidics
Laplace approximation	SURE-AI: Single-pass Uncertainty Estimation for Reliable Edge AI Accelerators
Large Language Model	DFAC: Dataflow-Aided Intra-cluster Coalescer for AI Accelerators Phase-Aware Monte Carlo Tree Search with LLM-Guided Proposal for Multi-Objective Physical Design Tuning EvoDRC: A Self-Evolving Agentic Framework for Automated DRC Violation Repair LMSACO: LLM-Guided Multi-Objective State-Adaptive Analog Circuit Sizing Optimization CoSim: A Cross-Layer Simulation Framework for System-Hardware Co-Design of LLM Inference Reducing Cascaded Speech-to-Speech Latency via Speculative Prefilling and Incremental Cache Recovery DISSECT: Cross-Family RTL Trojan Localization by Auditing Structural–Functional Disagreement LUMEN: A Compressed-LUT-based Processing-Near-Memory Architecture for Efficient LLM Inference at the Edge
Large language model (LLM)	TreePIM: A Heterogeneous Processing-in-Memory Architecture for Tree-based Speculative Decoding
Large Language Model Inference	RASP-LLM: Radiation-Aware Design-Space Exploration of Precision and Selective Protection for On-Orbit LLM Inference Cross-Bank ECC Strategy for LLM-Oriented Hybrid-Bonded 3D DRAM Architecture
Large Language Model(LLM)	Multi-modal LLM-Driven Generation of Processor Performance Simulators from Datasheet Specifications ML-AccelBench: A Benchmark for Evaluating LLM-Based ML Accelerator RTL Generation
Large Language Models	When Fuzzing Meets Understanding: LLM-Driven Semantic Test Generation for RTL Verification SLED-IFV: Solver-Validated LLM-Guided Decomposition for Scalable Hardware Information-Flow Verification CCD-KV: Exploiting High-Density 3D Charge-Coupled Device Memory for Efficient On-Device LLM KV Caches CoEvoP&R: Co-Evolving Placement Objectives with Routing Feedback via Large Language Models Opening the Black Box: A Self-Correcting LLM Agent for EDA Toolchains Based on Source-Code Analysis CABAgent: A Cross-Stage Agentic Framework for Generating PDK-Compatible and Layout-Verified Analog Circuit Benchmarks VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts DeferKV: Long-Context LLM Attention Acceleration with Per-Token Scale Folding and Bank-Local Softmax on PIM
large language models (LLMs)	ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Exploration
Large Language Models for EDA	MAESTRO: Memo-Augmented Multi-Agent Engine for Self-Testing RTL Code Generation with Resource Orchestration
Large Reasoning Model	Chain of SRAF Generation: A Large Reasoning Model for Sub-resolution Assist Features
Large-bitwidth Arithmetic	Investigation of Karatsuba Algorithm for Large-Bitwidth Modular Multiplication
Large-Language-Model	VPR-Evolve: Multi-Agent-Driven Algorithm Evolution for FPGA Place and Route
Latch Design	Multi-Output-Guided Transistor Network Synthesis and Layout for Sequential Cells
latency-critical systems	Declared Event Semantics: Cross-Layer Memory-Hierarchy Co-Design for Latency-Critical Systems
latency-insensitive design	Formally Verified Contract-Aware Replacement of Ready/Valid Microarchitectures
Layer Assignment	Operation-Aware Twisting of Folded Bit-Lines for Crosstalk Cancellation in Wafer-Bonded DRAM
Layout legalization	OptiClear: Differentiable Curvilinear Design Rule Legalization for Inverse-Designed Photonic Device
Learned Image Compression	Efficient End-to-End Hyperprior-Based Learned Image Compression on Edge GPUs via Thread-Level Parallel Entropy Coding
Learning-guided optimization	Learning-Augmented Multilevel Hypergraph Partitioning with Net-Level Cut Priors
legalization	Wirelength-Driven Mixed-Cell-Height Detailed Placement with Multi-Row Cell Relocation
Library Characterization	Physics-Informed Generative Model Based Aging Library Characterization
Lightweight	Lightweight Key-Based Hardware Device-ID Authentication: A Reliable, ML-Resistant Alternative to PUFs
linear attention	SPGLA-Net: A Slotline-Aware Port-Graph Linear Attention Residual Network for Sub-THz On-Chip Passive Modeling
link unavailability	RESCUE: Runtime Setup Resilience for TDM-Based Circuit-Switched NoCs
Lithographic Process Window	Chain of SRAF Generation: A Large Reasoning Model for Sub-resolution Assist Features
Lithography	MAGI-OPC: Manhattan Area–Edge Learning Guided by High-Quality ILT for Optical Proximity Correction
LLM	Enabling Efficient Quantized LLM Inference on Floating-Point CGRAs via Lightweight Integer Extensions MARCO: Markov Decision-based Adaptive Path Selection for Dynamic Layer Skipping
LLM Agent	DSEAgent: Agentic AI Accelerator Design Space Exploration via Expert-level Reinforcement Learning
LLM Agents for EDA	PowerPilot: Preserving Verified Progress in LLM-Based Power-Intent ECO Repair
LLM Decoding	Speculate, Verify, Repeat: Faster Decoding via Speculative KV Access and Verification Feedback
LLM for EDA	WaveAce: Analyzing the Root Cause of SoC Test Failures via LLMs' Direct Waveform Inspection Spec2Plan: An LLM-Powered Framework for Comprehensive Verification Plan Generation
LLM Inference	A Waferscale Memory Architecture for Efficient LLM Inference SPICE: Speculative Prefetching with Low-Rank Expert Surrogates and Heterogeneous Orchestration for MoE Inference Acceleration AccTTS: Characterizing and Optimizing Workload Dynamics in Test-Time Scaling AHEAD: A Fast and Efficient MoE Speculative Decoding System via Dynamic Draft–Verify Coordination
LLM Inference Acceleration	MTPMoE: Exploiting Activation Skewness in Single-GPU MoE Multi-Token Prediction via Parallel Dense-Sparse Computing
LLM inference accelerator	RACE-FFN: Runtime-Adaptive Co-Execution in a Heterogeneous SA-CIM Architecture for Efficient MoE-FFN Acceleration
LLM inference security	Security-Aware Runtime Control for Mitigating Token-Acceptance Side Channels in PIM/3D-Memory Speculative LLM Inference Architectures
LLM serving	Multi-Agent LLM Serving with SSD-Based KV-Cache Offloading
LLM Verilog generation	SpecLens: LLM-Based Verilog Generation with Specification-Derived Constraints via Behavioral Divergence
LLM-assisted RTL generation	HINT: Toward an Executable Hardware-Intent Intermediate Representation Layer for LLM-Driven RTL Generation
LLM-aware EDA	An Explainable Analog/Mixed-Signal Routing Agent using Deterministic Constraint-Conflict Diagnosis
LLM-based RTL optimization	ARES: Adaptive Reasoning-Effort Steering for PPA- and Cost-Aware RTL Optimization with LLM Agents
Local DRC Violation Fixing	SCALE: Self-Supervised Constraint-Aware Layout Generation for Local P&R DRV Fixing at Advanced Nodes
local setup recovery	RESCUE: Runtime Setup Resilience for TDM-Based Circuit-Switched NoCs
logic optimization	Node Reduction via Targeted ODC-Based Wire Additions for AIG Optimization Fast Delay-oriented Logic Optimization with Parallel SOP Generation GARDEN: GPU-Accelerated Rapid Divisor Extraction aigverse: A Unified Infrastructure for Machine Learning-Driven Logic Synthesis DeepResub: Towards Learned Logic Optimization Operators
logic restructuring	Placement-Aware Logic Resynthesis with Cooperative Multi-Agent Reinforcement Learning
Logic Synthesis	Fast Delay-oriented Logic Optimization with Parallel SOP Generation Inverter Redistribution through Self-Dual and Self-Anti-Dual Function Transformation Logic Resynthesis for Cross-Die Dependencies in Hybrid Bonded 3D ICs GARDEN: GPU-Accelerated Rapid Divisor Extraction aigverse: A Unified Infrastructure for Machine Learning-Driven Logic Synthesis Fanout-Multiplicity-Aware Technology Mapping for Multi-Output Superconducting Logic Placement-Aware Logic Resynthesis with Cooperative Multi-Agent Reinforcement Learning DeepResub: Towards Learned Logic Optimization Operators 3D-Syn: 3D-aware Synthesis Flow for Heterogeneous LogicFolding 3D ICs PP2Tree: Learning-Guided Frontier Partitioning for Scalable Parallel Logic Synthesis GA2-CT: GPU-Accelerated Genetic Algorithm for Low-Power Compression-Tree Rewiring Formally Verified Contract-Aware Replacement of Ready/Valid Microarchitectures
Logic Transformation	Decompose Transform Refine Verify: A new approach for scalable formal verification
LogicFolding	3D-Syn: 3D-aware Synthesis Flow for Heterogeneous LogicFolding 3D ICs
Lookup Table	LUMEN: A Compressed-LUT-based Processing-Near-Memory Architecture for Efficient LLM Inference at the Edge
LoRA	MemFLoRA: Memory-Floor LoRA for CNN Adaptation at the Edge
Lossy Compression	FLARE: A Dataflow-Aware and Scalable Hardware Architecture for Neural-Hybrid Scientific Lossy Compression
Low Lantency ；	PDG-CORDIC: A Posit-Decode-Guided Low-Latency CORDIC for Activation Function
Low-Bit LLM Inference	AlignQuant: Alignment First Two-Stage Integer Microscaling Format for Systolic Native LLM Inference
Low-power	Low-Power Approximate MRAM CAM with Dynamic-Reference for HDC Associative Search FlexRF: Retention-Aware Compilation for Low-power and Area-Efficient Flexible Microprocessors using IGZO DRAM-style Register File
Low-Power Circuit Design	Multi-Output-Guided Transistor Network Synthesis and Layout for Sequential Cells
Low-Power Optimization	GA2-CT: GPU-Accelerated Genetic Algorithm for Low-Power Compression-Tree Rewiring
Low-Power Verification	PowerPilot: Preserving Verified Progress in LLM-Based Power-Intent ECO Repair
Low-precision inference	ACCORD-IC: Contract-Checked Relation Transactions for Low-Bit Dynamic CNN–GNN Inference
LPDDR5	From DRAM Architecture to Protocol State: A Resource-Grounded Executable Semantics for LPDDR5
M
Machine learning	GRACE: GRAph-based power Consumption Estimator with Parallel Switching Activity Propagation Clock Distribution Network with Backside Clock Mesh in BSPDN Architecture aigverse: A Unified Infrastructure for Machine Learning-Driven Logic Synthesis Multi-Feature Demographic Decoupling via LPC Cross-Synthesis for Privacy-Preserving Audio Anonymization PaFeDSE: Pareto-Feedback-Guided Microarchitecture Design Space Exploration for Efficient Pareto Search Learning-Guided Adaptive Cell-Wise Optimization for Mixed-Size Global Placement HGRP: Heterogeneous Graph Neural Network for Routability Prediction A Dual-Branch GAT-MLP Framework for Efficient Bump-Level Dynamic IR Drop Prediction in Flip-Chip Packages UnifyPower: A Unified Framework of Architecture-Level Power Model for Processors PDN-Aware Graph Transformer-based Dynamic IR Drop Prediction with Criticality-Guided Subgraph Construction
Machine learning Accelerator	ML-AccelBench: A Benchmark for Evaluating LLM-Based ML Accelerator RTL Generation
Magnetic random access memory	Low-Power Approximate MRAM CAM with Dynamic-Reference for HDC Associative Search
Manhattan OPC	MAGI-OPC: Manhattan Area–Edge Learning Guided by High-Quality ILT for Optical Proximity Correction
Mapping	IMPACT: Constraint-Aware Search for Imperfectly Factorized Accelerator Mappings DREAM:3D-stacked Token-wise Caching Diffusion Accelerator with Resource-Aware Mapping
Markov Decision Process(MDP)	MARCO: Markov Decision-based Adaptive Path Selection for Dynamic Layer Skipping
Mask Optimization	EtchMO: A Differentiable Etch Model for Mask Optimization
matrix computing	MATE: Model-Assisted Trade-off Exploration for Quality-Aware Approximate Matrix Computing
Matrix-vector multiplication	FUSE: Five-Block MVM Energy Comparison
Maxwell Electromagnetic Simulation	MaxIM: A Plug-and-Play Maxwellian Engine via Interface Modification for Thick-Mask Lithography
memory barrier optimization	Compiler-driven Optimizations for Efficient Host and Near-DRAM Co-Execution
Memory compiler	Topology as a Design Variable: Joint Architecture-Sizing Optimization for SRAM
memory hierarchy	Declared Event Semantics: Cross-Layer Memory-Hierarchy Co-Design for Latency-Critical Systems
memory management	APRQ: Adaptive Prediction-Driven Residual Quantization Accelerator for Diffusion Transformers Multi-Agent LLM Serving with SSD-Based KV-Cache Offloading
Memory protection	A Minimal MMU for Memory Virtualization on Microcontrollers for time-sensitive applications
Memory Reliability	Cross-Bank ECC Strategy for LLM-Oriented Hybrid-Bonded 3D DRAM Architecture
memory scheduling	Declared Event Semantics: Cross-Layer Memory-Hierarchy Co-Design for Latency-Critical Systems
Memory simulator	Memory-Aware Design-Space Exploration for Multi-Threaded HLS Accelerators
memory technology	TADA: Technology Aware DNN Accelerator Performance and Energy Estimator
Memory virtualization	A Minimal MMU for Memory Virtualization on Microcontrollers for time-sensitive applications
memory-augmented neural network	A XNOR-SRAM-Based Computing-in-Memory Macro for Memory-Augmented Neural Networks
Memory-Bandwidth Bottleneck	Less is More: KV Cache Scheduling for Bandwidth-Efficient LLM Inference on FPGA
memory-controller	From DRAM Architecture to Protocol State: A Resource-Grounded Executable Semantics for LPDDR5
merger-free accumulation	MfSpGEMM: Merger-Free Row-Wise SpGEMM with Bitmap Accumulation and HBM-Aware Mapping
Mesh receiver placement	Clock Distribution Network with Backside Clock Mesh in BSPDN Architecture
micro-ring modulator	MIBIFI: Differentiable Electronic–Photonic–Thermal Co-Simulation for Co-Packaged Optics Designs
Micro-scaling	MX-like Tensor Core for LLM Inference with NPU Integration via Hardware-Software Co-Design Exploration
Microar-chitectural Stability	ChronosDSE: Stability-Aware Design Space Exploration for GPGPUs
Microarchitecture design space exploration	PaFeDSE: Pareto-Feedback-Guided Microarchitecture Design Space Exploration for Efficient Pareto Search
Microcontroller	Reasoning and Modeling of Instruction Corruption of MCU under EMFI
Microcontrollers	A Minimal MMU for Memory Virtualization on Microcontrollers for time-sensitive applications
Microfluidics	3D-VASE: Volumetric-Aware Scalable and Efficient Multi-Layer Design Synthesis for 3D-Printed Microfluidics
Microring Resonator	A Lightweight Microring-Resonator PUF Design for Silicon Photonics Transceivers
Microring resonators	FUSE: Five-Block MVM Energy Comparison
MILP	SpectraPlace2.5D: Thermal-aware Chiplet Placement via Topology-guided MILP and Spectral Thermal Modeling
Minimal Enablement Library	A DTCO-Oriented Early Digital Bring-Up Framework under Incomplete PDK and Standard-Cell Assets
Minimum Translation Vector	A Consensus-Optimization Framework for Progressive Clearance-Aware PCB Legalization with Irregular Components
Mixed Criticality systems	CRANE: Criticality-Aware Concurrent Neural Inference on Heterogeneous Edge Platforms
mixed-cell-height	Wirelength-Driven Mixed-Cell-Height Detailed Placement with Multi-Row Cell Relocation
mixed-precision floating point quantization	RASP-LLM: Radiation-Aware Design-Space Exploration of Precision and Selective Protection for On-Orbit LLM Inference
mixed-precision mapping	From Isolate to Co-Deployment Risk: Coupling-Aware Mapping for ACIM-Digital AI Accelerator
Mixed-precision quantization	TriM: Efficient MoE Inference on Edge CPU-GPU Systems via Fused Quantization and Sensitivity-Guided Scheduling NANQ: Noise-Aware Mixed-Precision Non-Uniform Quantization for Neural Networks on Analog Compute-in-Memory
mixed-signal circuit	CalNet: Temperature-Robust ADC Calibration via Learned BGR Behavior and LUT Correction
Mixture-of-Experts	TriM: Efficient MoE Inference on Edge CPU-GPU Systems via Fused Quantization and Sensitivity-Guided Scheduling SPICE: Speculative Prefetching with Low-Rank Expert Surrogates and Heterogeneous Orchestration for MoE Inference Acceleration MTPMoE: Exploiting Activation Skewness in Single-GPU MoE Multi-Token Prediction via Parallel Dense-Sparse Computing AHEAD: A Fast and Efficient MoE Speculative Decoding System via Dynamic Draft–Verify Coordination
ML EDA	Grad-BSS: Differentiable Optimization for Full-Stack Backside Signal Routing
ML-based estimation	TADA: Technology Aware DNN Accelerator Performance and Energy Estimator
ML-Resistant	Lightweight Key-Based Hardware Device-ID Authentication: A Reliable, ML-Resistant Alternative to PUFs
MLIR	Compiler-driven Optimizations for Efficient Host and Near-DRAM Co-Execution
MLIR Compiler Infrastructure	GenMLIR: An MLIR Compiler for Dynamic Programming Workloads on Tier-Aware 3D-DRAM PIM
model order reduction	SPLIT-MOR: Fast and Accurate Model Order Reduction for Nonlinear Transient Thermal Simulation of 2.5D/3D ICs
Modular	MinVNS: Minimal Virtual Network Separation for Deadlock Avoidance in Modular Network-on-Chip
Modular multiplication	Investigation of Karatsuba Algorithm for Large-Bitwidth Modular Multiplication
Module recognition	GAS: GPU Accelerated Schema Aware Exact Subcircuit Matching for Large-Scale Circuits
Modulo scheduling	From Compiler to Silicon: A Co-Design Approach to High-Performance CGRAs
MoE	RACE-FFN: Runtime-Adaptive Co-Execution in a Heterogeneous SA-CIM Architecture for Efficient MoE-FFN Acceleration
MOEA/D	Archive-Guided MOEA/D for Constrained Many-Objective Analog Circuit Sizing
Monolithic 3D DRAM	GenMLIR: An MLIR Compiler for Dynamic Programming Workloads on Tier-Aware 3D-DRAM PIM
Monolithic 3D-Stackable DRAM	KV3D: KV Cache-Centric Monolithic 3D-Stackable DRAM-Based Accelerator for LLM Serving
Monte Carlo Tree Search	Phase-Aware Monte Carlo Tree Search with LLM-Guided Proposal for Multi-Objective Physical Design Tuning
Montgomery Modular multiplication	Investigation of Karatsuba Algorithm for Large-Bitwidth Modular Multiplication
Multi-Agent Design Automation	MAESTRO: Memo-Augmented Multi-Agent Engine for Self-Testing RTL Code Generation with Resource Orchestration
multi-agent reinforcement learning	Placement-Aware Logic Resynthesis with Cooperative Multi-Agent Reinforcement Learning
Multi-agent systems	CABAgent: A Cross-Stage Agentic Framework for Generating PDK-Compatible and Layout-Verified Analog Circuit Benchmarks Multi-Agent LLM Serving with SSD-Based KV-Cache Offloading
Multi-FPGA system	CCPart: Timing-Aware Multi-Level Partitioning for Multi-FPGA Systems with Incremental Timing Analysis
Multi-FPGA systems	Timing-Aware Routing and Heterogeneous TDM Assignment for Multi-Level FPGA-Based Emulation Systems
Multi-Input Data Conversion	OMNI-DC: One-shot Multi-input Neural-Inference-Based Data Converter for Analog Computation-in-Memory
Multi-level routing	Timing-Aware Routing and Heterogeneous TDM Assignment for Multi-Level FPGA-Based Emulation Systems
multi-objective optimization	MATE: Model-Assisted Trade-off Exploration for Quality-Aware Approximate Matrix Computing CoSim: A Cross-Layer Simulation Framework for System-Hardware Co-Design of LLM Inference PaFeDSE: Pareto-Feedback-Guided Microarchitecture Design Space Exploration for Efficient Pareto Search Topology as a Design Variable: Joint Architecture-Sizing Optimization for SRAM SRAM Bitcell-Peripheral Co-Optimization Under Array-Level Yield Constraints
Multi-objective reinforcement learning	ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Exploration
Multi-Operator	RobotCFU: A Tightly Coupled Multi-Operator CFU for Embedded RISC-V Robot Control
Multi-output technology mapping	Fanout-Multiplicity-Aware Technology Mapping for Multi-Output Superconducting Logic
multi-precision	Enabling Efficient Quantized LLM Inference on Floating-Point CGRAs via Lightweight Integer Extensions
Multi-tenant FPGAs	Secure Reconfiguration for Multi-Tenant FPGAs
Multi-Token Prediction	MTPMoE: Exploiting Activation Skewness in Single-GPU MoE Multi-Token Prediction via Parallel Dense-Sparse Computing
Multi-turn LLM Dialogue	ATLAS: A Thermal-Aware 3D-Stacked Heterogeneous Architecture For LLM Multi-Turn Dialogue Serving
multi/many-core system	S-cache Directory: Efficient Sharer Tracking for Entry-Constrained Coherence Directories
Multilayer	3D-VASE: Volumetric-Aware Scalable and Efficient Multi-Layer Design Synthesis for 3D-Printed Microfluidics
Multiple patterning lithography	An Efficient Layout Decomposition Framework via Unsatisfiable Core
N
Near-Storage Processing	HAVEN: High-Bandwidth Flash Augmented Vector ENgine for Large-Scale Approximate Nearest-Neighbor Search Acceleration
Negative Testing	Between The Cracks: Uncovering Illegal-Instruction Bugs in RISC-V Processors by Exploring the Unified Encoding Space
network calculus	QoS Analysis for UCIe-based Cross-die Communication using Network Calculus
Network-on-Chip	QoS Analysis for UCIe-based Cross-die Communication using Network Calculus Cross-Bank ECC Strategy for LLM-Oriented Hybrid-Bonded 3D DRAM Architecture MinVNS: Minimal Virtual Network Separation for Deadlock Avoidance in Modular Network-on-Chip
networks-on-chip	RESCUE: Runtime Setup Resilience for TDM-Based Circuit-Switched NoCs
Networks-on-chip and NoC-based system design	Naviq: An Open-Source System-on-Chip Simulator for Rapid Prototyping, Verification, and Design Space Exploration
Neural Architecture Search	CONTOUR: Continuous Topology Search for System-Level RFICs via Bi-Level Optimization and Neural-Analytical Co-Modeling Hardware-Retargetable Grammar-Based NAS from Declarative Device Specifications
Neural Network	MAGI-OPC: Manhattan Area–Edge Learning Guided by High-Quality ILT for Optical Proximity Correction Taming Irregular Sparsity with a Regular Systolic Array for Efficient DNN Training A Two Stage Learning-Based Thermal-Aware Framework for 3D Fixed-Outline Soft-Module Floorplanning across Chip Sizes
neural network acceleration	NOVA-CIM: Noise- and Correlation-Tolerant Stochastic Interfaces for Analog Compute-in-Memory
neural networks	CalNet: Temperature-Robust ADC Calibration via Learned BGR Behavior and LUT Correction
Neural Volume Rendering	Hit-SME: A High-throughput Hybrid SNN-based MLP Engine for Neural Volume Rendering
Neuro-symbolic AI	SymbOperon: Composable and Cost-Efficient Symbolic Reasoning Operators for Neuro-Symbolic Edge Perception
Neuro-symbolic computing	UnO-NeSy: Optimizing Neuro-Symbolic Computing with Unified FeFET Based In-Memory System
Neuromorphic computing	IMPACT: IoT SNN Inference with a Metadata-Guided Pulse-Width Control Architecture for Conductance-Time Weight Representation in RRAM
Neuromorphic Hardware Mapping	Nexus: Activity-Aware Capacity-Constrained Neuron Partitioning for Multicore SNN Accelerators
Neuron Partitioning	Nexus: Activity-Aware Capacity-Constrained Neuron Partitioning for Multicore SNN Accelerators
NoC Simulator	Q-COMPASS: A Circuit-Calibrated Simulation Framework for QDI NoC Architecture Exploration
Noise-aware quantization	NANQ: Noise-Aware Mixed-Precision Non-Uniform Quantization for Neural Networks on Analog Compute-in-Memory
Noise-aware sampling	ASSERT: Adaptive Stochastic Sampling for Robust Diffusion Models on Analog Compute-in-Memory Hardware
Noise-Aware Training	ABNAT: Attention-Based Noise-Aware Training for Robust Transformers on Analog Compute-in-Memory Systems
Noise-limited design	InfoCIM: An Information-Theoretic Framework for Modeling and Design of Noise-Limited Analog CIM
Non-commutative	SWAPPER: Dynamic Operand Swapping in Non-commutative Approximate Circuits for Online Error Reduction
Non-integer mixed cell-height	ALTO: Joint Track-Height and Placement Optimization for Non-Integer Mixed-Cell-Height Designs
Non-uniform quantization	NANQ: Noise-Aware Mixed-Precision Non-Uniform Quantization for Neural Networks on Analog Compute-in-Memory
Nonlinear Function Approximation	REASON: RNG-Aware Finite-State Machines for Hardware-Realistic Stochastic Nonlinear Approximation
nonlinear transient thermal simulation	SPLIT-MOR: Fast and Accurate Model Order Reduction for Nonlinear Transient Thermal Simulation of 2.5D/3D ICs
normalized weight	ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Exploration
NVM-in-cache	NVM-in-Cache: Repurposing Commodity 6T SRAM Cache into NVM Analog Processing-in-Memory Engine using a Novel Compute-on-Powerline Scheme
O
Obfuscated write back	A Reliability-Enhanced SOT-MTJ PUF with Obfuscated Write-Back for Physical-State Exposure Mitigation
Obfuscation	TraceMorph: Real-Trace-Guided Execution-Level Obfuscation for RAPL-Based DNN Architecture Protection
objective functions	CoEvoP&R: Co-Evolving Placement Objectives with Routing Feedback via Large Language Models
observability don't-cares	Node Reduction via Targeted ODC-Based Wire Additions for AIG Optimization
offset via	Network Flow Guided Routing and Force Directed Offset Via Placement for Advanced Chiplet Interconnect
Offset-via	Efficient Concurrent Die-to-Die Routing with Teardrop and Offset-Via Awareness
on-chip cache	APRQ: Adaptive Prediction-Driven Residual Quantization Accelerator for Diffusion Transformers
On-chip monitoring	BLINK: Batch NormaLization-based INtegrity ChecKpoints for In-Situ Detection and Mitigation of Diverse Weight Corruptions in DNN Accelerators
On-Device Learning	MemFLoRA: Memory-Floor LoRA for CNN Adaptation at the Edge
on-orbit computing	RASP-LLM: Radiation-Aware Design-Space Exploration of Precision and Selective Protection for On-Orbit LLM Inference
Online Anomaly Detection	Online Open-World Wafer Defect Discovery using Hyperdimensional Computing
Online Clustering	Online Open-World Wafer Defect Discovery using Hyperdimensional Computing
Online Error Reduction	SWAPPER: Dynamic Operand Swapping in Non-commutative Approximate Circuits for Online Error Reduction
Online STDP learning	SpikeFold: An FPGA-based Neuromorphic Processor with DSP Optimization and Parallel Weight Update STDP
OPCSA	A Reliability-Enhanced SOT-MTJ PUF with Obfuscated Write-Back for Physical-State Exposure Mitigation
Open-Set Recognition	Online Open-World Wafer Defect Discovery using Hyperdimensional Computing
Open-source	ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Exploration
OpenAccess	Atomic and Hierarchy-Safe Cross-Module Undo/Redo for Analog IC Design
operational semantics	From DRAM Architecture to Protocol State: A Resource-Grounded Executable Semantics for LPDDR5
Operator Network	ResistONet: Cascade Operator Network for Photoresist Simulation
Optical neural network accelerators	FUSE: Five-Block MVM Energy Comparison
optical neural networks	Observability-Aware Runtime Reliability for MZI-Based Optical Neural Networks
Optical Proximity Correction	Curvilinear OPC via Diffeomorphic Deformation
Optical Proximity Effect	Chain of SRAF Generation: A Large Reasoning Model for Sub-resolution Assist Features
Optimization	UnO-NeSy: Optimizing Neuro-Symbolic Computing with Unified FeFET Based In-Memory System Chiplet Assembly and Pre-Bond Qualification Planning for Heterogeneous Integrated Systems
Optoelectronic interconnects	A System-Level Typed-Graph Environment for Traceable Cycle-Level Co-Design of Heterogeneous AI Accelerators
Out-of-order issue	BB8: Blocking Buffer for breaking head-of-line stalling in GPGPUs via Instruction Bypassing.
P
P/G TSV Planning	MoL-PAM: Joint P/G TSV Planning and Macro Refinement for Memory-on-Logic 3D ICs via a Benders-Type Decomposition Heuristic
Package routing	Efficient Concurrent Die-to-Die Routing with Teardrop and Offset-Via Awareness
parallel algorithms	Fast Delay-oriented Logic Optimization with Parallel SOP Generation GARDEN: GPU-Accelerated Rapid Divisor Extraction
Parallel Computation	VoxPMC: A Fast Voxel-Based Particle Monte Carlo Simulator for Feature-Scale Process Topography Simulation HB-VGGT: Exploiting Head-Wise Complementary Redundancy for Efficient VGGT Inference on Hybrid-Bonded Architecture
parallel swap	An Area-Efficient CIM-Based Ising Annealer with Folded Mapping and Cooling-Scheduled Parallel Swaps Strategy for Large-Scale Traveling Salesman Problem
Parameter optimization	Atomic and Hierarchy-Safe Cross-Module Undo/Redo for Analog IC Design
Parameter Tuning	Phase-Aware Monte Carlo Tree Search with LLM-Guided Proposal for Multi-Objective Physical Design Tuning
Partial FHE	PFHE: Partial Fully Homomorphic Encryption on CNN Inference
Particle Monte Carlo	VoxPMC: A Fast Voxel-Based Particle Monte Carlo Simulator for Feature-Scale Process Topography Simulation
Partitioning	PP2Tree: Learning-Guided Frontier Partitioning for Scalable Parallel Logic Synthesis
PCell	FormalPCell: Formal DRC Verification of Parameterized Layout Cells via Symbolic Interpretation and SMT Solving
PDK Cleanup	A DTCO-Oriented Early Digital Bring-Up Framework under Incomplete PDK and Standard-Cell Assets
Performance counters	SiliDiff: Post-Silicon Thermal and Power Reconstruction from Sparse Sensing with a Cascaded Conditional Diffusion Model
Performance Modeling	ChronosDSE: Stability-Aware Design Space Exploration for GPGPUs
Performance simulation	MAP-DSE: A Fast Performance Simulator for Large-Scale Microarchitectural Design Space Exploration Multi-modal LLM-Driven Generation of Processor Performance Simulators from Datasheet Specifications
Performance tuning	Atomic and Hierarchy-Safe Cross-Module Undo/Redo for Analog IC Design
Peripheral co-optimization	SRAM Bitcell-Peripheral Co-Optimization Under Array-Level Yield Constraints
Photonic computing	FUSE: Five-Block MVM Energy Comparison
Photonic inverse design	OptiClear: Differentiable Curvilinear Design Rule Legalization for Inverse-Designed Photonic Device
Photoresist Model	ResistONet: Cascade Operator Network for Photoresist Simulation
Physical AI	T3R: Training-Free Two-Stage Token Refinement Towards Efficient and Robust VLA Models
Physical AI in embedded systems	EdgeDAE: Acceleration of Diffusion Action Experts for Real-Time Physical AI with Tiny VLAs on Edge FPGA-GPU Systems
Physical Design	NaCo3D: Native and Compact 3D Floorplanning via Reinforcement Learning AgenticPD: A Stage-Aware Agentic Framework for Closed-Loop Physical Design Optimization Phase-Aware Monte Carlo Tree Search with LLM-Guided Proposal for Multi-Objective Physical Design Tuning Structure-Preserving Density Modeling for Electrostatics-Based Analytical Placement ALTO: Joint Track-Height and Placement Optimization for Non-Integer Mixed-Cell-Height Designs ARC: Any-Angle PCB Routing with Obstacle Avoidance under Complex Design Rules VPR-Evolve: Multi-Agent-Driven Algorithm Evolution for FPGA Place and Route Learning-Guided Adaptive Cell-Wise Optimization for Mixed-Size Global Placement HGRP: Heterogeneous Graph Neural Network for Routability Prediction
physical design automation	Placement Guidance Generation via Timing-Aware Hypergraph Partitioning and Multi-Criteria Cluster Selection
Physical unclonable function	A Lightweight Microring-Resonator PUF Design for Silicon Photonics Transceivers A Reliability-Enhanced SOT-MTJ PUF with Obfuscated Write-Back for Physical-State Exposure Mitigation
physical unclonable functions	EMPUF: A Leakage-Controlled Pre-Fabrication Benchmark for PCB Spectral Fingerprints
Physical verification	RT-DRC: Accelerating Design Rule Checking Using GPU Ray-Tracing Cores CABAgent: A Cross-Stage Agentic Framework for Generating PDK-Compatible and Layout-Verified Analog Circuit Benchmarks
Physical-aware optimization	Logic Resynthesis for Cross-Die Dependencies in Hybrid Bonded 3D ICs
physical-aware synthesis	Placement-Aware Logic Resynthesis with Cooperative Multi-Agent Reinforcement Learning
Physically Unclonable Function	Power and EM Side-Channel Leakage Mitigation in Oscillator-Based PUFs via Sampling Techniques
Physics Informed Machine Learning	Physics-Informed Generative Model Based Aging Library Characterization
Physics-Informed Neural Networks	ResistONet: Cascade Operator Network for Photoresist Simulation
PIM	GD-PIM: A Low-Cost Gustavson Dataflow-Based Processing-in-Memory Architecture for SpGEMM
Pipeline-aware compilation	From Compiler to Silicon: A Co-Design Approach to High-Performance CGRAs
Place-and-Route	VPR-Evolve: Multi-Agent-Driven Algorithm Evolution for FPGA Place and Route
Place-and-Route DRC Fixing	SCALE: Self-Supervised Constraint-Aware Layout Generation for Local P&R DRV Fixing at Advanced Nodes
Placement	SpectraPlace2.5D: Thermal-aware Chiplet Placement via Topology-guided MILP and Spectral Thermal Modeling CoEvoP&R: Co-Evolving Placement Objectives with Routing Feedback via Large Language Models Learning-Guided Adaptive Cell-Wise Optimization for Mixed-Size Global Placement
Placement and Routing	Obstacle-Aware Timing-Driven Buffer Insertion via Feasible Shallow-Light Topology Reconstruction
placement guidance	Placement Guidance Generation via Timing-Aware Hypergraph Partitioning and Multi-Criteria Cluster Selection
placement initialization	From Communities to Coordinates: Hierarchical Clustering–Guided Placement for Large-Scale FPGAs
port graph	SPGLA-Net: A Slotline-Aware Port-Graph Linear Attention Residual Network for Sub-THz On-Chip Passive Modeling
Posit format ；	PDG-CORDIC: A Posit-Decode-Guided Low-Latency CORDIC for Activation Function
Post-Placement Optimization	PACT: A Runtime Contract for Sparse-Topology Updates in GPU-Accelerated Timing ECOs
Post-placement resynthesis	Logic Resynthesis for Cross-Die Dependencies in Hybrid Bonded 3D ICs
Post-silicon	SiliDiff: Post-Silicon Thermal and Power Reconstruction from Sparse Sensing with a Cascaded Conditional Diffusion Model
Post-Training Quantization	AlignQuant: Alignment First Two-Stage Integer Microscaling Format for Systolic Native LLM Inference
Power Consumption	An In-situ Self Clock-Gated 7474 Style Scan-Mux-D Low Power Flip-Flop
power delivery network	PI-Aware Co-Layer Signal Routing and Power Plane Synthesis for Chiplet Interposers PDN-Aware Graph Transformer-based Dynamic IR Drop Prediction with Criticality-Guided Subgraph Construction
Power Dilivery network	Cross-Layer Reinforcement Learning for Power-Via Optimization in Multilayer RDL Power/Ground Plane Synthesis
Power estimation	GRACE: GRAph-based power Consumption Estimator with Parallel Switching Activity Propagation
Power integrity	CertIR: Certified Static IR-Drop Estimation with Physics-Anchored Neural Correction Cross-Layer Reinforcement Learning for Power-Via Optimization in Multilayer RDL Power/Ground Plane Synthesis
Power integrity analysis	A Dual-Branch GAT-MLP Framework for Efficient Bump-Level Dynamic IR Drop Prediction in Flip-Chip Packages
Power Intent (UPF)	PowerPilot: Preserving Verified Progress in LLM-Based Power-Intent ECO Repair
Power model	UnifyPower: A Unified Framework of Architecture-Level Power Model for Processors
Power modeling analysis and simulation	Anonymous: A CPU-GPU Heterogeneous Engine for Glitch-Aware Time-Based Gate-Level Power Analysis
Power reconstruction	SiliDiff: Post-Silicon Thermal and Power Reconstruction from Sparse Sensing with a Cascaded Conditional Diffusion Model
Power-performance-area trade-offs	From Compiler to Silicon: A Co-Design Approach to High-Performance CGRAs
power-signal co-optimization	Power Network Topology Optimization for Top Dies in Backside-Powered F2F 3D ICs
Power/Ground Plane Synthesis	Cross-Layer Reinforcement Learning for Power-Via Optimization in Multilayer RDL Power/Ground Plane Synthesis
PPA evaluation	Device-Circuit Co-Optimization of SOT-MRAM with Accurate PPA Evaluation for Edge AI Training
pre-fabrication benchmarking	EMPUF: A Leakage-Controlled Pre-Fabrication Benchmark for PCB Spectral Fingerprints
Preconditioned Iterative Solver	ThTrace: A High-Efficiency Displacement Field Simulator for Advanced Packaging
prediction	APRQ: Adaptive Prediction-Driven Residual Quantization Accelerator for Diffusion Transformers
Preference-vector conditioning	ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Exploration
Preprocessing	Adaptive BTOR2 Reformulation via Solver-Aware Equality Saturation
Printed Circuit Board Legalization	A Consensus-Optimization Framework for Progressive Clearance-Aware PCB Legalization with Irregular Components
privacy preservation	Multi-Feature Demographic Decoupling via LPC Cross-Synthesis for Privacy-Preserving Audio Anonymization
Privacy-preserving machine learning	DRS: Unified Fully Homomorphic Encryption Hardware Accelerator with Scheme-Switching PFHE: Partial Fully Homomorphic Encryption on CNN Inference
process variation	HOIST: A High-Order Interaction Surrogate for Sample-Efficient High-Sigma Yield Estimation in High-Dimensional Circuits
Processing in Memory	DRAC: A Static Analysis for DRAM Row Activation Count Toward Efficient Processing-in-Memory Code Generation
processing in-memory (PIM)	NVM-in-Cache: Repurposing Commodity 6T SRAM Cache into NVM Analog Processing-in-Memory Engine using a Novel Compute-on-Powerline Scheme
Processing near memory	KV3D: KV Cache-Centric Monolithic 3D-Stackable DRAM-Based Accelerator for LLM Serving
processing-in-memory	GenMLIR: An MLIR Compiler for Dynamic Programming Workloads on Tier-Aware 3D-DRAM PIM Security-Aware Runtime Control for Mitigating Token-Acceptance Side Channels in PIM/3D-Memory Speculative LLM Inference Architectures DeferKV: Long-Context LLM Attention Acceleration with Per-Token Scale Folding and Bank-Local Softmax on PIM
Processing-in-memory (PIM)	TreePIM: A Heterogeneous Processing-in-Memory Architecture for Tree-based Speculative Decoding Prefix-Branch Software Co-Design for Random Forest Acceleration on Embedded Hybrid TCAMs
Processing-Near-Memory	LUMEN: A Compressed-LUT-based Processing-Near-Memory Architecture for Efficient LLM Inference at the Edge
Processor	Staggered Instruction-Fetch Duplication: A Lightweight Processor-Level Countermeasure Against Fault Injection UnifyPower: A Unified Framework of Architecture-Level Power Model for Processors
Processor Fuzzing	Between The Cracks: Uncovering Illegal-Instruction Bugs in RISC-V Processors by Exploring the Unified Encoding Space
progressive computation	Progressive Computation Scheduling for Deadline-Critical Tasks in Hierarchical Edge Networks
Progressive Library Augmentation	A DTCO-Oriented Early Digital Bring-Up Framework under Incomplete PDK and Standard-Cell Assets
Property Decomposition	Decompose Transform Refine Verify: A new approach for scalable formal verification
property-directed reachability	SLED-IFV: Solver-Validated LLM-Guided Decomposition for Scalable Hardware Information-Flow Verification
Pulse-width modulation	IMPACT: IoT SNN Inference with a Metadata-Guided Pulse-Width Control Architecture for Conductance-Time Weight Representation in RRAM
PVT variations	AnchorGNN: Cross-PVT Corner Timing Prediction via Anchor-Guided Graph Learning and STA-Aware Propagation CalNet: Temperature-Robust ADC Calibration via Learned BGR Behavior and LUT Correction
Python	aigverse: A Unified Infrastructure for Machine Learning-Driven Logic Synthesis
Python-Based Verification	Towards Leveraging the Software Ecosystem to Facilitate Hardware Verification
Q
QoR Optimization	AgenticPD: A Stage-Aware Agentic Framework for Closed-Loop Physical Design Optimization
QoS	QoS Analysis for UCIe-based Cross-die Communication using Network Calculus
Quantization	DPSQ : Dynamic Partial Sum Quantization with Mixed Granularity APRQ: Adaptive Prediction-Driven Residual Quantization Accelerator for Diffusion Transformers Enabling Efficient Quantized LLM Inference on Floating-Point CGRAs via Lightweight Integer Extensions EdgeDAE: Acceleration of Diffusion Action Experts for Real-Time Physical AI with Tiny VLAs on Edge FPGA-GPU Systems SSR-VAR: Exploiting Spatial- and Scale-aware Redundancy for Lightweight Inference of Visual Autoregressive Models ACED: An Algorithm–Hardware Co-Designed VLA Accelerator Exploiting Dynamic Weight-Precision Switching
Quantized Neural Networks	BLINK: Batch NormaLization-based INtegrity ChecKpoints for In-Situ Detection and Mitigation of Diverse Weight Corruptions in DNN Accelerators
quantum arithmetic	A Resource-Efficient Quantum Circuit for Fixed-Point Logarithm Operations with Analytical Error Bounds
Quantum circuit optimization	Reducing T-depth in quantum circuits through adaptive allocation of ancillae between T-par and H-gadgets
Quantum Circuit Partitioning	Scalable Quantum Circuits Partitioning via Shortest-Path Search and Circuit Transformation
quantum logarithm	A Resource-Efficient Quantum Circuit for Fixed-Point Logarithm Operations with Analytical Error Bounds
Quasi Delay Insensitive circuits	Q-COMPASS: A Circuit-Calibrated Simulation Framework for QDI NoC Architecture Exploration
R
radiation-aware reliability	RASP-LLM: Radiation-Aware Design-Space Exploration of Precision and Selective Protection for On-Orbit LLM Inference
Random Forest	Prefix-Branch Software Co-Design for Random Forest Acceleration on Embedded Hybrid TCAMs
Rapid Single Flux Quantum (RSFQ)	qLevelPlace: A Level-Based Placement Framework for RSFQ Circuits
RAPL power side channel	TraceMorph: Real-Trace-Guided Execution-Level Obfuscation for RAPL-Based DNN Architecture Protection
rare-event simulation	HOIST: A High-Order Interaction Surrogate for Sample-Efficient High-Sigma Yield Estimation in High-Dimensional Circuits
RC Tree Moment Matching	RAPID: An Efficient and Accurate Ratio-Based Analytical Proxy for Interconnect Delay
Read Reference Voltage	Reducing Read Retries by Skipping Similar Adjacent Read Voltage Parameters in 3D TLC NAND Flash
Read Retry	Reducing Read Retries by Skipping Similar Adjacent Read Voltage Parameters in 3D TLC NAND Flash
ready/valid	Formally Verified Contract-Aware Replacement of Ready/Valid Microarchitectures
Reconfigurable computing	From Compiler to Silicon: A Co-Design Approach to High-Performance CGRAs
Reconfigurable Logic and FPGAs	Naviq: An Open-Source System-on-Chip Simulator for Rapid Prototyping, Verification, and Design Space Exploration
redistribution layers	Cross-Layer Reinforcement Learning for Power-Via Optimization in Multilayer RDL Power/Ground Plane Synthesis
Redundant via	Cross-Layer Reinforcement Learning for Power-Via Optimization in Multilayer RDL Power/Ground Plane Synthesis
REFSM	Cube-based Finite-State-Machine Extraction via SAT Generalizations
region-adaptive search	CRAFT: Constraint-Guided Region-Adaptive Search over Broad Design Spaces for High-Dimensional Analog Circuit Sizing
Register Transfer Level (RTL)	ML-AccelBench: A Benchmark for Evaluating LLM-Based ML Accelerator RTL Generation
Reinforcement Learning	Thermal-Aware Chiplet Placement Integrating Evolutionary Reinforcement Learning and Monte Carlo Tree Search GLARE: Generalizable Large-scale Analog Sizing via Reinforcement Learning with Covariance-Guided Exploration NgramRL: Accelerating RL Post-Training for Structured Generation via Rollout-Aware N-gram Speculative Decoding
Relation-identity certification	ACCORD-IC: Contract-Checked Relation Transactions for Low-Bit Dynamic CNN–GNN Inference
Reliability	Reducing Read Retries by Skipping Similar Adjacent Read Voltage Parameters in 3D TLC NAND Flash Physics-Informed Generative Model Based Aging Library Characterization UniCASE: A Unified 16-bit Floating Point Format with Criticality-Aware Selective ECC for Efficient DNN Protection Fine-Grained Compiler-Assisted Hardening via Tolerant-Output Analysis for SDC–Runtime Trade-offs
reliability characterization	CHAIDO: Open-Source Simulation-Based Fault Injection for the AMD Versal AI Engine
Rendering	TempoGS: Temporal Binning and Expiration-Aware Gaussian Loading for Memory-Efficient 4D Gaussian Splatting Acceleration
Representation Learning	Functionality-Aware Is Not Synthesis-Invariant: An End-to-End Audit of Circuit-GNN Representations Functional Retrieval for Resynthesis-Robust Hardware Trojan Detection in Gate-Level Netlists
Request Coalescing	DFAC: Dataflow-Aided Intra-cluster Coalescer for AI Accelerators
resource analysis	A Resource-Efficient Quantum Circuit for Fixed-Point Logarithm Operations with Analytical Error Bounds
Resource-Aware Scheduling	RAP: Resource‑Aware Scheduling for GPU Accelerated Hypergraph Partitioning
resource-limited verification	CircuitsDNA: Discovering Unconventional Multi-Accuracy Arithmetic Circuits via Evolutionary Synthesis
Resubstitution	DeepResub: Towards Learned Logic Optimization Operators
Resynthesis	Functional Retrieval for Resynthesis-Robust Hardware Trojan Detection in Gate-Level Netlists
Retrieval-Augmented Generation	HAVEN: High-Bandwidth Flash Augmented Vector ENgine for Large-Scale Approximate Nearest-Neighbor Search Acceleration TACO: Topology-Aware Compression via Hardware–Software Co-Design for Robust CiM-Accelerated Edge RAG Retrieval VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts
reverse engineering	Cube-based Finite-State-Machine Extraction via SAT Generalizations
RF fingerprints	EMPUF: A Leakage-Controlled Pre-Fabrication Benchmark for PCB Spectral Fingerprints
RF passive synthesis	A Unified Framework for Circuit-Aware Tapped-Inductor Inverse Design with Topology-Aware Sequence Representation
RFIC	CONTOUR: Continuous Topology Search for System-Level RFICs via Bi-Level Optimization and Neural-Analytical Co-Modeling SPGLA-Net: A Slotline-Aware Port-Graph Linear Attention Residual Network for Sub-THz On-Chip Passive Modeling
Ring Oscillator	Power and EM Side-Channel Leakage Mitigation in Oscillator-Based PUFs via Sampling Techniques
RISC-V	Accelerating 5G NR Channel Estimation with a Complex-Arithmetic RISC-V Vector Extension RobotCFU: A Tightly Coupled Multi-Operator CFU for Embedded RISC-V Robot Control MAP-DSE: A Fast Performance Simulator for Large-Scale Microarchitectural Design Space Exploration Staggered Instruction-Fetch Duplication: A Lightweight Processor-Level Countermeasure Against Fault Injection A Minimal MMU for Memory Virtualization on Microcontrollers for time-sensitive applications CoD-MiCo: Co-Design of Mixed-Compression RISC-V Extensions for Neural Networks on FPGAs Multi-modal LLM-Driven Generation of Processor Performance Simulators from Datasheet Specifications FlexRF: Retention-Aware Compilation for Low-power and Area-Efficient Flexible Microprocessors using IGZO DRAM-style Register File Fine-Grained Compiler-Assisted Hardening via Tolerant-Output Analysis for SDC–Runtime Trade-offs
RISC-V ISA Compliance	Between The Cracks: Uncovering Illegal-Instruction Bugs in RISC-V Processors by Exploring the Unified Encoding Space
RobotCFU	RobotCFU: A Tightly Coupled Multi-Operator CFU for Embedded RISC-V Robot Control
robotic manipulation	3DToMe: A Morton-Local and Interaction-Aware Token-Merging Accelerator for Efficient 3D Diffusion Policy Inference
Robotics	T3R: Training-Free Two-Stage Token Refinement Towards Efficient and Robust VLA Models
Robust Vector Retrieval	TACO: Topology-Aware Compression via Hardware–Software Co-Design for Robust CiM-Accelerated Edge RAG Retrieval
Root Cause Analysis	WaveAce: Analyzing the Root Cause of SoC Test Failures via LLMs' Direct Waveform Inspection
Routability prediction	HGRP: Heterogeneous Graph Neural Network for Routability Prediction
routing	CoEvoP&R: Co-Evolving Placement Objectives with Routing Feedback via Large Language Models PI-Aware Co-Layer Signal Routing and Power Plane Synthesis for Chiplet Interposers A HeteroGNN-Based Hierarchical Co-Optimization Framework for Floorplanning and Routing in Advanced Packaging
routing-aware placement	APPlace: Co-Optimizing Device Locations and Access Points for Routing-Aware Analog Placement
row-wise product	MfSpGEMM: Merger-Free Row-Wise SpGEMM with Bitmap Accumulation and HBM-Aware Mapping
RRAM	Weight-Stationary Fault Recovery via Neuron Tuning in RRAM-Based CIM Neuromorphic Accelerators IMPACT: IoT SNN Inference with a Metadata-Guided Pulse-Width Control Architecture for Conductance-Time Weight Representation in RRAM
RTL	PP2Tree: Learning-Guided Frontier Partitioning for Scalable Parallel Logic Synthesis DISSECT: Cross-Family RTL Trojan Localization by Auditing Structural–Functional Disagreement
RTL Code Generation	VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts
RTL generation framework	AX-AGENT: Contract-Driven Closed-Loop Framework for Error-Bounded PPA-Aware Approximate RTL Generation
RTL simulation	TensorLUT: Exact Batched RTL Simulation via ANF-Lifted Tensor-Core GEMM
RTL Verification and Debugging	MAESTRO: Memo-Augmented Multi-Agent Engine for Self-Testing RTL Code Generation with Resource Orchestration
runtime reliability	Observability-Aware Runtime Reliability for MZI-Based Optical Neural Networks
runtime scheduling	RACE-FFN: Runtime-Adaptive Co-Execution in a Heterogeneous SA-CIM Architecture for Efficient MoE-FFN Acceleration
RVV	Accelerating 5G NR Channel Estimation with a Complex-Arithmetic RISC-V Vector Extension
S
S-parameter prediction	SPGLA-Net: A Slotline-Aware Port-Graph Linear Attention Residual Network for Sub-THz On-Chip Passive Modeling
Safety-critical system	BLINK: Batch NormaLization-based INtegrity ChecKpoints for In-Situ Detection and Mitigation of Diverse Weight Corruptions in DNN Accelerators
SAT generalization	Cube-based Finite-State-Machine Extraction via SAT Generalizations
Scalable Architecture	FLARE: A Dataflow-Aware and Scalable Hardware Architecture for Neural-Hybrid Scientific Lossy Compression
Scale Hyperprior Model	Efficient End-to-End Hyperprior-Based Learned Image Compression on Edge GPUs via Thread-Level Parallel Entropy Coding
Scheduling	CRANE: Criticality-Aware Concurrent Neural Inference on Heterogeneous Edge Platforms
Scheme-Switching	DRS: Unified Fully Homomorphic Encryption Hardware Accelerator with Scheme-Switching
Scientific Computing	LU-Evolve: Agent-Based Algorithm Exploration for Sparse LU Solvers
Scientific Machine Learning	Encoding Symmetries into Operator Learning: Towards Accurate Multi-Physics Simulation in Advanced Packaging
Secure Reconfiguration	Secure Reconfiguration for Multi-Tenant FPGAs
selective protection	RASP-LLM: Radiation-Aware Design-Space Exploration of Precision and Selective Protection for On-Orbit LLM Inference
Self-Anti-Dual	Inverter Redistribution through Self-Dual and Self-Anti-Dual Function Transformation
self-consistency	SpecLens: LLM-Based Verilog Generation with Specification-Derived Constraints via Behavioral Divergence
Self-Correction	Opening the Black Box: A Self-Correcting LLM Agent for EDA Toolchains Based on Source-Code Analysis
Self-Dual	Inverter Redistribution through Self-Dual and Self-Anti-Dual Function Transformation
Semiconductor Process Simulation	VoxPMC: A Fast Voxel-Based Particle Monte Carlo Simulator for Feature-Scale Process Topography Simulation
Sensing Margin	Operation-Aware Twisting of Folded Bit-Lines for Crosstalk Cancellation in Wafer-Bonded DRAM
Separating Axis Theorem	A Consensus-Optimization Framework for Progressive Clearance-Aware PCB Legalization with Irregular Components
Sequential Cell	Multi-Output-Guided Transistor Network Synthesis and Layout for Sequential Cells
Sequential equivalence checking	ARES: Adaptive Reasoning-Effort Steering for PPA- and Cost-Aware RTL Optimization with LLM Agents
setup resilience	RESCUE: Runtime Setup Resilience for TDM-Based Circuit-Switched NoCs
sharer tracking	S-cache Directory: Efficient Sharer Tracking for Entry-Constrained Coherence Directories
Shortest Path	Scalable Quantum Circuits Partitioning via Shortest-Path Search and Circuit Transformation
side channel	Security-Aware Runtime Control for Mitigating Token-Acceptance Side Channels in PIM/3D-Memory Speculative LLM Inference Architectures
Side-Channel Attack	Power and EM Side-Channel Leakage Mitigation in Oscillator-Based PUFs via Sampling Techniques
signal routing	Grad-BSS: Differentiable Optimization for Full-Stack Backside Signal Routing
silent data corruption	CHAIDO: Open-Source Simulation-Based Fault Injection for the AMD Versal AI Engine Fine-Grained Compiler-Assisted Hardening via Tolerant-Output Analysis for SDC–Runtime Trade-offs
silicon measurement-assisted fine-tuning	CalNet: Temperature-Robust ADC Calibration via Learned BGR Behavior and LUT Correction
Silicon Photonics	A Lightweight Microring-Resonator PUF Design for Silicon Photonics Transceivers
Simulated Annealing	ChronosDSE: Stability-Aware Design Space Exploration for GPGPUs
simulation and modeling	FADiff: Fusion-Aware Differentiable Optimization for DNN Scheduling on Tensor Accelerators
single-event upset	CHAIDO: Open-Source Simulation-Based Fault Injection for the AMD Versal AI Engine
Sizing	Obstacle-Aware Timing-Driven Buffer Insertion via Feasible Shallow-Light Topology Reconstruction
Slew-Aware Delay-Ratio Correction	RAPID: An Efficient and Accurate Ratio-Based Analytical Proxy for Interconnect Delay
slotline passive network	SPGLA-Net: A Slotline-Aware Port-Graph Linear Attention Residual Network for Sub-THz On-Chip Passive Modeling
SMT	An Explainable Analog/Mixed-Signal Routing Agent using Deterministic Constraint-Conflict Diagnosis
SoC Test	WaveAce: Analyzing the Root Cause of SoC Test Failures via LLMs' Direct Waveform Inspection
Soft errors	UniCASE: A Unified 16-bit Floating Point Format with Criticality-Aware Selective ECC for Efficient DNN Protection Fine-Grained Compiler-Assisted Hardening via Tolerant-Output Analysis for SDC–Runtime Trade-offs
Software-driven Test	WaveAce: Analyzing the Root Cause of SoC Test Failures via LLMs' Direct Waveform Inspection
software-hardware co-design	TriM: Efficient MoE Inference on Edge CPU-GPU Systems via Fused Quantization and Sensitivity-Guided Scheduling
software–hardware co-design	3DToMe: A Morton-Local and Interaction-Aware Token-Merging Accelerator for Efficient 3D Diffusion Policy Inference
SOT-MRAM	Device-Circuit Co-Optimization of SOT-MRAM with Accurate PPA Evaluation for Edge AI Training SURE-AI: Single-pass Uncertainty Estimation for Reliable Edge AI Accelerators
SOT-MTJ	A Reliability-Enhanced SOT-MTJ PUF with Obfuscated Write-Back for Physical-State Exposure Mitigation
Source-Code Analysis	Opening the Black Box: A Self-Correcting LLM Agent for EDA Toolchains Based on Source-Code Analysis
Source-Equivalence Retrieval	Functionality-Aware Is Not Synthesis-Invariant: An End-to-End Audit of Circuit-GNN Representations
Source-to-source Transformation	HLSClaw: Bringing Vibe Coding to High-Level Synthesis through Skill-Based Agentic Harness
sparse attention	CRISP: Paged Sparse Attention on DRAM-PIM with Row-Band-Aware KV Allocation and Frame-Derived Addressing
Sparse LU Factorization	LU-Evolve: Agent-Based Algorithm Exploration for Sparse LU Solvers
Sparse sensors	SiliDiff: Post-Silicon Thermal and Power Reconstruction from Sparse Sensing with a Cascaded Conditional Diffusion Model
Sparse thermal sensing	STRIDE: Sparse Thermal Reconstruction-Informed Differential Encoding for Thermally Stable 3D-Integrated Analog CIM
Sparse training	Taming Irregular Sparsity with a Regular Systolic Array for Efficient DNN Training
Sparsity	CoD-MiCo: Co-Design of Mixed-Compression RISC-V Extensions for Neural Networks on FPGAs
specification enhancement	SpecLens: LLM-Based Verilog Generation with Specification-Derived Constraints via Behavioral Divergence
Spectral Bias	OMNI-DC: One-shot Multi-input Neural-Inference-Based Data Converter for Analog Computation-in-Memory
Spectral Graph Theory	FRESHPart: Feedback-Reshaped Spectral Embedding for Hypergraph Partitioning
Spectral Placement	Scalable Quantum Circuits Partitioning via Shortest-Path Search and Circuit Transformation
Spectral Thermal Modeling	SpectraPlace2.5D: Thermal-aware Chiplet Placement via Topology-guided MILP and Spectral Thermal Modeling
speculative decoding	Security-Aware Runtime Control for Mitigating Token-Acceptance Side Channels in PIM/3D-Memory Speculative LLM Inference Architectures AHEAD: A Fast and Efficient MoE Speculative Decoding System via Dynamic Draft–Verify Coordination NgramRL: Accelerating RL Post-Training for Structured Generation via Rollout-Aware N-gram Speculative Decoding
Speculative decoding (SD)	TreePIM: A Heterogeneous Processing-in-Memory Architecture for Tree-based Speculative Decoding
Speculative Prefetching	SPICE: Speculative Prefetching with Low-Rank Expert Surrogates and Heterogeneous Orchestration for MoE Inference Acceleration
speech emotion recognition	Multi-Feature Demographic Decoupling via LPC Cross-Synthesis for Privacy-Preserving Audio Anonymization
speech-to-speech systems	Reducing Cascaded Speech-to-Speech Latency via Speculative Prefilling and Incremental Cache Recovery
SpGEMM	GD-PIM: A Low-Cost Gustavson Dataflow-Based Processing-in-Memory Architecture for SpGEMM MfSpGEMM: Merger-Free Row-Wise SpGEMM with Bitmap Accumulation and HBM-Aware Mapping
SPICE	Sample-Efficient Neural Compact Modeling for Design-Technology Co-Optimization Based on Process-Aware Adaptation
SPICE simulation	Archive-Guided MOEA/D for Constrained Many-Objective Analog Circuit Sizing
SPICE validation	HOIST: A High-Order Interaction Surrogate for Sample-Efficient High-Sigma Yield Estimation in High-Dimensional Circuits
Spiking Neural Network	Hit-SME: A High-throughput Hybrid SNN-based MLP Engine for Neural Volume Rendering
Spiking neural networks	Weight-Stationary Fault Recovery via Neuron Tuning in RRAM-Based CIM Neuromorphic Accelerators SpikeFold: An FPGA-based Neuromorphic Processor with DSP Optimization and Parallel Weight Update STDP IMPACT: IoT SNN Inference with a Metadata-Guided Pulse-Width Control Architecture for Conductance-Time Weight Representation in RRAM Nexus: Activity-Aware Capacity-Constrained Neuron Partitioning for Multicore SNN Accelerators
SRAM	NVM-in-Cache: Repurposing Commodity 6T SRAM Cache into NVM Analog Processing-in-Memory Engine using a Novel Compute-on-Powerline Scheme UACC: A Chiplet-Based Auxiliary Cache for Cost-Effective Performance Scaling in Multicore Processors
SRAM design automation	Topology as a Design Variable: Joint Architecture-Sizing Optimization for SRAM
SRAM optimization	SRAM Bitcell-Peripheral Co-Optimization Under Array-Level Yield Constraints
SSD offloading	Multi-Agent LLM Serving with SSD-Based KV-Cache Offloading
Standard Cell Library	Multi-Output-Guided Transistor Network Synthesis and Layout for Sequential Cells
standard-cell characterization	Cross-Family Graph Learning for Sparse Aging-Aware Timing Characterization of Standard-Cell Libraries
Static analysis	GREG: A Graphical Static Analysis Framework for Early Hardware Security Verification DRAC: A Static Analysis for DRAM Row Activation Count Toward Efficient Processing-in-Memory Code Generation
Static IR-drop estimation	CertIR: Certified Static IR-Drop Estimation with Physics-Anchored Neural Correction
static timing analysis	RAPID: An Efficient and Accurate Ratio-Based Analytical Proxy for Interconnect Delay XCTS: Cross-Tier-Aware Differentiable Clock Tree Synthesis for 3D Integrated Circuits AnchorGNN: Cross-PVT Corner Timing Prediction via Anchor-Guided Graph Learning and STA-Aware Propagation Anonymous: Fast Clock-Aware Timing Propagation for Complex Clock Logic and Constraints with State Flow Graph Abstraction CCPart: Timing-Aware Multi-Level Partitioning for Multi-FPGA Systems with Incremental Timing Analysis
Stationary Velocity Field	Curvilinear OPC via Diffeomorphic Deformation
Steiner Tree Construction	Obstacle-Aware Timing-Driven Buffer Insertion via Feasible Shallow-Light Topology Reconstruction
Stochastic computing	NOVA-CIM: Noise- and Correlation-Tolerant Stochastic Interfaces for Analog Compute-in-Memory REASON: RNG-Aware Finite-State Machines for Hardware-Realistic Stochastic Nonlinear Approximation
stochastic interface	NOVA-CIM: Noise- and Correlation-Tolerant Stochastic Interfaces for Analog Compute-in-Memory
Storage System	Reducing Read Retries by Skipping Similar Adjacent Read Voltage Parameters in 3D TLC NAND Flash
streaming inference	Reducing Cascaded Speech-to-Speech Latency via Speculative Prefilling and Incremental Cache Recovery
Structural Topology	Functional Retrieval for Resynthesis-Robust Hardware Trojan Detection in Gate-Level Netlists
Stuck-At-Faults	Weight-Stationary Fault Recovery via Neuron Tuning in RRAM-Based CIM Neuromorphic Accelerators
Sub-resolution Assist Features	Chain of SRAF Generation: A Large Reasoning Model for Sub-resolution Assist Features
Subcircuit matching	GAS: GPU Accelerated Schema Aware Exact Subcircuit Matching for Large-Scale Circuits
subgraph construction	PDN-Aware Graph Transformer-based Dynamic IR Drop Prediction with Criticality-Guided Subgraph Construction
Super-Resolution	ScaleLUT: A Fully-Parallel Configurable LUT-Based Accelerator for Real-Time Multi-Scale Super-Resolution
Superconducting circuit	Fanout-Multiplicity-Aware Technology Mapping for Multi-Output Superconducting Logic
Superconducting Circuit Physical Design	qLevelPlace: A Level-Based Placement Framework for RSFQ Circuits
Superconducting SFQ circuit	qLevelPlace: A Level-Based Placement Framework for RSFQ Circuits
Supervised Learning	MAGI-OPC: Manhattan Area–Edge Learning Guided by High-Quality ILT for Optical Proximity Correction
surrogate model	HOIST: A High-Order Interaction Surrogate for Sample-Efficient High-Sigma Yield Estimation in High-Dimensional Circuits
Surrogate modeling	SPGLA-Net: A Slotline-Aware Port-Graph Linear Attention Residual Network for Sub-THz On-Chip Passive Modeling Topology as a Design Variable: Joint Architecture-Sizing Optimization for SRAM
Symbolic operator	SymbOperon: Composable and Cost-Efficient Symbolic Reasoning Operators for Neuro-Symbolic Edge Perception
synchronization	Compiler-driven Optimizations for Efficient Host and Near-DRAM Co-Execution
Synopsys Design Constraints	Anonymous: Fast Clock-Aware Timing Propagation for Complex Clock Logic and Constraints with State Flow Graph Abstraction
Synthesis Invariance	Functionality-Aware Is Not Synthesis-Invariant: An End-to-End Audit of Circuit-GNN Representations
Synthetic Layout Data Generation	SCALE: Self-Supervised Constraint-Aware Layout Generation for Local P&R DRV Fixing at Advanced Nodes
System Inverse Design	CONTOUR: Continuous Topology Search for System-Level RFICs via Bi-Level Optimization and Neural-Analytical Co-Modeling
System-level modeling	A System-Level Typed-Graph Environment for Traceable Cycle-Level Co-Design of Heterogeneous AI Accelerators
System-level modeling simulation and validation	Naviq: An Open-Source System-on-Chip Simulator for Rapid Prototyping, Verification, and Design Space Exploration
Systolic Array	Hit-SME: A High-throughput Hybrid SNN-based MLP Engine for Neural Volume Rendering
T
T-depth reduction	Reducing T-depth in quantum circuits through adaptive allocation of ancillae between T-par and H-gadgets
T-par	Reducing T-depth in quantum circuits through adaptive allocation of ancillae between T-par and H-gadgets
Tail-latency-aware inference	ACCORD-IC: Contract-Checked Relation Transactions for Low-Bit Dynamic CNN–GNN Inference
Tail-Phase Robustness	ChronosDSE: Stability-Aware Design Space Exploration for GPGPUs
TCAD	Sample-Efficient Neural Compact Modeling for Design-Technology Co-Optimization Based on Process-Aware Adaptation
TDM	RESCUE: Runtime Setup Resilience for TDM-Based Circuit-Switched NoCs
Teardrop	Efficient Concurrent Die-to-Die Routing with Teardrop and Offset-Via Awareness
Technology Mapping	Inverter Redistribution through Self-Dual and Self-Anti-Dual Function Transformation
Temperature inversion	Gradient-Guided Thermal-Aware Timing Robustness Optimization Under Temperature Inversion
Template-based Generation	AutoIsing: An Automated Compiler for Programmable Ising Machine
tensor cores	TensorLUT: Exact Batched RTL Simulation via ANF-Lifted Tensor-Core GEMM
Ternary Content-Addressable Memory (TCAM)	Prefix-Branch Software Co-Design for Random Forest Acceleration on Embedded Hybrid TCAMs
test economics	Chiplet Assembly and Pre-Bond Qualification Planning for Heterogeneous Integrated Systems
test-aware	Chiplet Assembly and Pre-Bond Qualification Planning for Heterogeneous Integrated Systems
Test-time scaling	AccTTS: Characterizing and Optimizing Workload Dynamics in Test-Time Scaling
Thermal	A Two Stage Learning-Based Thermal-Aware Framework for 3D Fixed-Outline Soft-Module Floorplanning across Chip Sizes
Thermal management	SiliDiff: Post-Silicon Thermal and Power Reconstruction from Sparse Sensing with a Cascaded Conditional Diffusion Model
Thermal Optimization	ATLAS: A Thermal-Aware 3D-Stacked Heterogeneous Architecture For LLM Multi-Turn Dialogue Serving
Thermal Simulation	Encoding Symmetries into Operator Learning: Towards Accurate Multi-Physics Simulation in Advanced Packaging MIBIFI: Differentiable Electronic–Photonic–Thermal Co-Simulation for Co-Packaged Optics Designs
thermal-aware design	SpectraPlace2.5D: Thermal-aware Chiplet Placement via Topology-guided MILP and Spectral Thermal Modeling Thermal-Aware Chiplet Placement and Shape Co-Optimization under D2D Interconnect Constraints for 2.5D Integration DiffTherm: A Differentiable Thermal Formulation for Cell-Via Co-Optimization in 3D ICs STRIDE: Sparse Thermal Reconstruction-Informed Differential Encoding for Thermally Stable 3D-Integrated Analog CIM
Thermal-Aware Optimization	Thermal-Aware Chiplet Placement Integrating Evolutionary Reinforcement Learning and Monte Carlo Tree Search
Thermal-aware timing robustness	Gradient-Guided Thermal-Aware Timing Robustness Optimization Under Temperature Inversion
Thermomechanical Simulation	ThTrace: A High-Efficiency Displacement Field Simulator for Advanced Packaging
Thick-Mask Lithography	MaxIM: A Plug-and-Play Maxwellian Engine via Interface Modification for Thick-Mask Lithography
Time-Axis Splitting	Scalable Quantum Circuits Partitioning via Shortest-Path Search and Circuit Transformation
Time-based power analysis	Anonymous: A CPU-GPU Heterogeneous Engine for Glitch-Aware Time-Based Gate-Level Power Analysis
Time-division multiplexing	Timing-Aware Routing and Heterogeneous TDM Assignment for Multi-Level FPGA-Based Emulation Systems
Time-domain Computing	A Time-Encoded Analog Photonic Interposer for Energy-Efficient Integration of Analog Vision Sensors and Analog Accelerators
timing constraints	From DRAM Architecture to Protocol State: A Resource-Grounded Executable Semantics for LPDDR5
Timing ECO Flows	PACT: A Runtime Contract for Sparse-Topology Updates in GPU-Accelerated Timing ECOs
Timing path	Timing-Aware Routing and Heterogeneous TDM Assignment for Multi-Level FPGA-Based Emulation Systems
Timing-driven placement	ALTO: Joint Track-Height and Placement Optimization for Non-Integer Mixed-Cell-Height Designs
TinyML	Enabling Energy-Efficient TinyML Inference via Fused Tensor Architecture
token merging	3DToMe: A Morton-Local and Interaction-Aware Token-Merging Accelerator for Efficient 3D Diffusion Policy Inference
Topography Evolution	VoxPMC: A Fast Voxel-Based Particle Monte Carlo Simulator for Feature-Scale Process Topography Simulation
Topology	SpectraPlace2.5D: Thermal-aware Chiplet Placement via Topology-guided MILP and Spectral Thermal Modeling
Topology Maintenance	PACT: A Runtime Contract for Sparse-Topology Updates in GPU-Accelerated Timing ECOs
Topology optimization	Topology as a Design Variable: Joint Architecture-Sizing Optimization for SRAM
Topology Rectification	CktHVR: A Convergence-Aware GNN-VLM Hypothesize-Verify-Refine Framework for Analog Circuit Topology Rectification
Topology-Aware Compression	TACO: Topology-Aware Compression via Hardware–Software Co-Design for Robust CiM-Accelerated Edge RAG Retrieval
Transformer	A Unified Framework for Circuit-Aware Tapped-Inductor Inverse Design with Topology-Aware Sequence Representation
Transformer Deployment	ABNAT: Attention-Based Noise-Aware Training for Robust Transformers on Analog Compute-in-Memory Systems
Transient analysis	PARFuzzer: Path-Aware RTL Fuzzing with Controlled BTB Conflict Injection for Branch-Predictor Security Validation
Transistor Network Synthesis	Multi-Output-Guided Transistor Network Synthesis and Layout for Sequential Cells
traveling salesman problem (TSP)	An Area-Efficient CIM-Based Ising Annealer with Folded Mapping and Cooling-Scheduled Parallel Swaps Strategy for Large-Scale Traveling Salesman Problem
Trusted Execution Environments	Secure Reconfiguration for Multi-Tenant FPGAs
U
UCIe	QoS Analysis for UCIe-based Cross-die Communication using Network Calculus
UCIe protocol	Thermal-Aware Chiplet Placement and Shape Co-Optimization under D2D Interconnect Constraints for 2.5D Integration
Ultra-low power	UnO-NeSy: Optimizing Neuro-Symbolic Computing with Unified FeFET Based In-Memory System
uncertainty estimation	SURE-AI: Single-pass Uncertainty Estimation for Reliable Edge AI Accelerators
Undo/Redo	Atomic and Hierarchy-Safe Cross-Module Undo/Redo for Analog IC Design
Unsatisfiable Core	An Efficient Layout Decomposition Framework via Unsatisfiable Core
useful skew	A Comprehensive Clock Tree Synthesis with Useful Skew for 3D ICs
V
Vector Processor	Accelerating 5G NR Channel Estimation with a Complex-Arithmetic RISC-V Vector Extension
verification	From DRAM Architecture to Protocol State: A Resource-Grounded Executable Semantics for LPDDR5
Verification Methodology	Towards Leveraging the Software Ecosystem to Facilitate Hardware Verification
Verification Planning	Spec2Plan: An LLM-Powered Framework for Comprehensive Verification Plan Generation
Verilog	ML-AccelBench: A Benchmark for Evaluating LLM-Based ML Accelerator RTL Generation
Versal	CHAIDO: Open-Source Simulation-Based Fault Injection for the AMD Versal AI Engine
Virtual Channel	MinVNS: Minimal Virtual Network Separation for Deadlock Avoidance in Modular Network-on-Chip
Vision Language Model	SCALE: Self-Supervised Constraint-Aware Layout Generation for Local P&R DRV Fixing at Advanced Nodes
Vision Language Models	CktHVR: A Convergence-Aware GNN-VLM Hypothesize-Verify-Refine Framework for Analog Circuit Topology Rectification
Vision Transformers	SHARD: Sub-Transformer Harnessing for Adaptive Resource-Aware Deployment
Vision-Language-Action Model	EdgeDAE: Acceleration of Diffusion Action Experts for Real-Time Physical AI with Tiny VLAs on Edge FPGA-GPU Systems ActRAM: A Hybrid Analog/Digital Action-Expert Accelerator Architecture for Vision-Language-Action Models ACED: An Algorithm–Hardware Co-Designed VLA Accelerator Exploiting Dynamic Weight-Precision Switching
Visual Autoregressive Model	SSR-VAR: Exploiting Spatial- and Scale-aware Redundancy for Lightweight Inference of Visual Autoregressive Models
VLSI placement	Placement Guidance Generation via Timing-Aware Hypergraph Partitioning and Multi-Criteria Cluster Selection
VTA	Enabling Energy-Efficient TinyML Inference via Fused Tensor Architecture
W
Wafer Defect Analysis	Online Open-World Wafer Defect Discovery using Hyperdimensional Computing
Wafer-Bonded DRAM	Operation-Aware Twisting of Folded Bit-Lines for Crosstalk Cancellation in Wafer-Bonded DRAM
Waferscale	A Waferscale Memory Architecture for Efficient LLM Inference
Warp scheduling	BB8: Blocking Buffer for breaking head-of-line stalling in GPGPUs via Instruction Bypassing.
Warpage Analysis	ThTrace: A High-Efficiency Displacement Field Simulator for Advanced Packaging
Warpage Simulation	Encoding Symmetries into Operator Learning: Towards Accurate Multi-Physics Simulation in Advanced Packaging
Waveform-based power analysis	Anonymous: A CPU-GPU Heterogeneous Engine for Glitch-Aware Time-Based Gate-Level Power Analysis
Weight Clustering	CoD-MiCo: Co-Design of Mixed-Compression RISC-V Extensions for Neural Networks on FPGAs
Wire Connectivity Extraction	FlowMapper: Detection-Guided Topology Reconstruction of Circuit Block Diagrams
Wire Cut	Scalable Quantum Circuits Partitioning via Shortest-Path Search and Circuit Transformation
Wire Twisting	Operation-Aware Twisting of Folded Bit-Lines for Crosstalk Cancellation in Wafer-Bonded DRAM
wirelength	A HeteroGNN-Based Hierarchical Co-Optimization Framework for Floorplanning and Routing in Advanced Packaging
Y
yield	Chiplet Assembly and Pre-Bond Qualification Planning for Heterogeneous Integrated Systems
Yield estimation	SRAM Bitcell-Peripheral Co-Optimization Under Array-Level Yield Constraints

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