ABSTRACT. Computing-in-Memory (CIM) has been widely studied to mitigate data transfer bottlenecks in von Neumann architectures. Memory-augmented neural networks (MANN) address the catastrophic for getting problem in few-shot learning applications by introducing external memory, and have become an important method for few-shot learning. However, its frequent data transmission and similarity calculations result in a large amount of energy and computational overhead. To tackle these challenges, we propose an efficient SRAM Computing-in-Memory architecture based on customized hardware-software co-optimization. We first propose a binarization optimization for MANN to enable area and energy efficient hardware deployment on a CIM macro. We further design a reconfigurable XNOR-SRAM CIM macro that supports 𝐿1 distance calculation based on bitwise XNOR operations, and Top-1 similarity search through an Adaptive Masking-based Max Engine(AMBME). Implemented in 28-nm technology, our macro achieves an energy efficiency of 182.78 TOPS/W and a throughput density of 6.83 TOPS/mm2, attaining classification accuracies of 94.2% and 85.7% for 8-way 4-shot and 32-way 1-shot tasks on the Omniglot dataset.

ABSTRACT. SRAM's power-performance-area-stability trade-off is governed by a discrete architectural choice, bitcell topology, that couples non-separably with continuous transistor sizing, yet no open-source SRAM tool treats topology as an optimizeable variable: OpenRAM offers no optimization, and OpenYield restricts its optimizer to scalar sizing on a fixed 6T topology. We remove this restriction. OpenYield-V2 jointly evolves topology and transistor parameters under high-fidelity, full-macro simulation, using a few-shot surrogate to absorb the resulting evaluation cost and a structure-aware coarse-to-refined optimizer to reconcile discrete architectural search with continuous local refinement. Across a range of design conditions, the optimal topology shifts systematically rather than following a fixed rule, revealing a topology decision boundary that cannot be captured by single-topology optimization; exposing topology as a design variable allows the optimizer to automatically exploit this boundary, improving hypervolume by up to 12.0\% over the strongest single-topology baseline. \href{https://anonymous.4open.science/r/OpenYield-900D/README.md}{OpenYieldV2} is open-source to support reproducible architecture-level SRAM design research.

ABSTRACT. ACIM-digital heterogeneous accelerators route noise-tolerant computation to analog compute-in-memory (ACIM). Precision-critical work remains on digital processing elements (PEs). Existing mixed-precision mappers rank layers or operators independently, assuming that joint accuracy loss is additive. We show that this assumption fails: individually safe modules can form \emph{cross-layer noise-coupled} pairs whose joint degradation is up to $10.7\times$ larger than single-module analysis predicts. We propose CLAM, a coupling-aware mapping framework that recasts mapping as co-deployment-risk control. It profiles a floor-stabilized pairwise coupling matrix, exploits block-local coupling to reduce profiling cost, and searches budget-feasible ACIM/digital assignments that avoid jointly dangerous ACIM placements. Across ResNet-50, BERT-base, Llama-3-8B, and Swin-T, CLAM is compared with five recent advanced mapping methods under the same ACIM macro-operation budget. The results show that CLAM delays the collapse frontier by one to two increments in $b_{\mathrm{MO}}^\star$ and improves accuracy-matched target energy efficiency by $2.00\times$, $1.53\times$, $1.41\times$, and $1.28\times$ over the strongest non-coupling runner-up on the four workloads, respectively.

ABSTRACT. The rapid growth of deep neural network (DNN) workloads has significantly increased the demand for large-capacity on-chip SRAM in machine learning (ML) applications, with SRAM arrays now occupying a substantial fraction of the total die area. To address the dual challenges of storage density and computation efficiency, this paper proposes an NVM-in-Cache architecture that integrates resistive RAM (RRAM) devices into a conventional 6T-SRAM cell, forming a compact 6T-2R bit-cell. This hybrid cell enables Processing-in-Memory (PIM) mode, which performs massively parallel multiply-and-accumulate (MAC) operations directly on cache power lines while preserving stored cache data. By exploiting the intrinsic properties of the 6T-2R structure, the architecture achieves additional storage capability, high computational throughput without any bit-cell area overhead. Circuit- and array-level simulations in GlobalFoundries 22nm FDSOI technology demonstrate that the proposed design achieves a throughput of 0.4 TOPS and 417.25 TOPS/W. For 128 row-parallel operations, the CIFAR-10 classification is demonstrated by mapping a Resnet-18 neural network, achieving an accuracy of 91.76%. These results highlight the potential of the NVM-in-Cache approach to serve as a scalable, energy-efficient computing method by re-purposing existing 6T SRAM cache architecture for next-generation AI accelerators and general purpose processors.

ABSTRACT. Advancement of edge AI keeps raising the bar for emerging non-volatile memories (NVM). Spin-orbit torque MRAM (SOT-MRAM), offering high speed, low power, and high reliability, is a strong candidate for edge AI training, yet its efficiency is governed by coupled device- and circuit-level factors that demand joint optimization. Starting from SOT switching physics, we introduce a current-shunting estimator to refine a Verilog-A device model, and build power, performance, and area (PPA) evaluators for device–circuit co-optimization. System-level training evaluation shows that the optimized SOT-MRAM attains throughput and training speed comparable to SRAM, and 11.7× and 18.4× higher efficiency than RRAM and FeFET, respectively, paving the way for generative AI at the edge.

ABSTRACT. Threshold-voltage drift from wear and retention increases raw errors in 3D NAND flash. When ECC decoding fails, SSD controllers invoke read retry using vendor read retry tables (RRTs), but conventional sequential sweeps incur substantial latency, known as the sequential-sweep penalty (SSP). This work proposes Adaptive Grouping-based Read Retry (AGRR), which groups similar retry parameters, probes representative entries, and uses historical decoding outcomes to guide future retries. Evaluated on real 3D TLC NAND, AGRR reduces read latency by up to 79% with <2% loss in decode success rate. With only lightweight one-time calibration, AGRR comes within about 0.2 retries of the in-RRT oracle, which is an ideal policy that directly selects a decodable entry from the shipped vendor RRT for each failed page, closing over 92% of the retry gap.

ABSTRACT. Inverse design of on-chip tapped inductors is one-to-many: a target electrical response can map to many layouts, but few remain legal and effective after electromagnetic (EM) and circuit-level evaluation. Existing learning-based methods often rely on restrictive parametric codes or image-like maps that weaken layout discipline. We instead represent each inductor as a topology-aware sequence and generate it autoregressively with a decoder-only transformer conditioned on structured passive tokens. A verification-aware flow then performs legality screening, minimum-edit repair, post-EM ranking, and circuit-level selection. Across three T-coil-peaked driver cases and three oscillator-tank cases, each evaluated over five seeds, our method achieves the best mean circuit-level performance in every case. It delivers the highest mean driver 3-dB bandwidths of 60.66--82.53~GHz with 2.86$\times$--2.95$\times$ bandwidth extension, and the lowest mean oscillator frequency errors of 1.84\%--4.61\% with the highest mean figures of merit.

ABSTRACT. System-level RFIC design remains largely manual and simulation-intensive, especially when multiple stages must be co-optimized under coupled gain, noise figure (NF), bandwidth, and matching constraints. Using an RF receiver as a case study, this paper presents CONTOUR, an AI-assisted framework for unified RFIC system design via a loading-aware bi-level optimization formulation. CONTOUR encodes discrete topology choices continuously and jointly optimizes topology and sizing across the receiver chain, explicitly modeling inter-stage loading through backward impedance propagation. A timescale-separated bi-level particle swarm optimization (PSO), combined with neural-analytical co-modeling, accelerates search while reserving high-fidelity simulation for final verification. Results show robust convergence, outperforms joint-optimization baselines, and adaptive topology selection across gain-, bandwidth-, and NF-prioritized targets. A complete specs-to-layout case study further demonstrates the practicality of CONTOUR for automated RFIC receiver design.

ABSTRACT. Hierarchical IC editing flows (hierarchical design verification, global parameter sweeping, device optimization, post-simulation tuning) frequently modify multiple nested submodules. Conventional EDA tools adopt per-design linear undo stacks, failing to support atomic cross-module synchronization and often triggering dangling cell ref- erences, silent state corruption, and unconditional full redo record erasure. This paper proposes an application-layer cross-module synchro- nized undo/redo framework built on a bidirectional operation- design association model, fully implemented atop standard unmod- ified OpenAccess APIs. Three core techniques constitute our solu- tion: a recursive BFS impact closure algorithm to compute minimal coupled submodule sets; a hierarchy-aware topological scheduler enforcing child-first restoration to eliminate cross-module refer- ence exceptions; and a fine-grained selective redo cleanup strategy that retains independent redo branches without overriding the database’s native truncation rule. We formally prove the atomicity, minimality, and hierarchical safety of the proposed framework. Experiments cover three industrial analog/mixed-signal bench- marks: a 3-layer Gilbert RF mixer (|𝑅| = 3), a 5-layer charge pump (|𝑅| = 8), and an extreme 10-level cross-library nested RF front-end with |𝑅| = 107 coupled submodules. Under steady-state warm- cache tests, our framework guarantees full cross-module atomic consistency and eliminates dangling reference faults across all scales, retaining an average redo retention rate of 85.3% for inde- pendent subcircuit redo branches discarded entirely by commercial tools. Steady-state checkpoint insertion latency averages 84.81 μs for |𝑅| = 3, 114.57 μs for |𝑅| = 8, and 688.4 μs for |𝑅| = 107, staying below 0.7 ms even in the industrial extreme case. The lightweight preUndo BFS closure completes within 19 μs for all benchmarks. Aggregated application-layer logic accounts for less than 3.2% of total cross-module undo latency; verifying that unavoidable native OpenAccess snapshot rollback dominates overall delay.

ABSTRACT. Full-wave electromagnetic (EM) simulation accurately characterizes Sub-THz on-chip passive networks, but minute-scale evaluation of each candidate makes iterative exploration of high-dimensional geometry spaces computationally expensive. This creates a coupled learning problem: the surrogate must capture frequency-dependent response patterns while resolving directed RF port-pair interactions defined by each topology. We propose SPGLA-Net, a slotline-aware surrogate that maps geometry parameters to function-specific S- parameter targets over 100–200 GHz, including return loss, in- sertion loss, and transmitter-receiver (TX-RX) isolation. Its gated linear attention branch provides the primary frequency sequence prediction, while a directed port-graph branch supplies topology- conditioned residual corrections through adaptive gating. On one slotline power combiner (PC) and two electrical-balance duplexer (EBD) topologies in 40-nm bulk CMOS, SPGLA-Net achieves the lowest overall dB-domain mean absolute error (MAE) among seven baselines and reduces the error of the best baseline by 17.8%, 4.2%, and 14.1%, respectively. Under the reported batch-32 inference pro- tocol, SPGLA-Net predicts all 101 frequency points in an amortized 2.6–2.7 ms per geometry, supporting fast RF candidate screening before final full-wave verification.

ABSTRACT. The scarcity of layout-verified benchmarks remains a critical barrier to AI-driven analog circuit design automation. Existing studies primarily address schematic-level generation or optimization under simplified device assumptions, often omitting foundry PDK integration, physical verification, and post-layout evaluation, thereby limiting reproducibility and practical relevance. This paper presents CABAgent (Cross-Stage Analog Benchmark Agent), an agentic framework for generating PDK-compatible circuits through an end-to-end workflow encompassing simulation, layout generation, DRC/LVS verification, parasitic extraction, and post-layout evaluation. Given natural-language circuit descriptions, interface constraints, and PDK information, CABAgent generates validated SKY130-compatible SPICE netlists using a self-evolving memory (SEM)-based multi-agent loop that integrates circuit generation, static checking, Ngspice validation, reflection, and knowledge curation. Validated seeds are subsequently expanded into standardized benchmark packages through automated exploration of device sizing, bias conditions, and layout constraints. CABAgent achieves 98.3% Pass@1 and generates 1,000 package trials across 20 topologies within approximately 23 hours while preserving successful artifacts and stage-aware failures. Ablation results show that SEM improves Pass@1 by 18.9%. A downstream analog sizing consumer using CABAgent achieves 70.5% post-layout Pass@1, 12.3% above pre-layout-only sizing after physical verification. These results establish CABAgent as a reproducible foundation for physically grounded analog design research. Code is available: https://github.com/artifact-cabagent/CABAgent.

ABSTRACT. Photonic inverse design enables ultra-compact, high-performance devices with highly curvilinear and non-intuitive geometries, but the resulting layouts often violate fabrication design rules and hinder foundry manufacturing. Legalization methods designed for rectilinear Manhattan electrical layouts are not directly applicable to curvilinear inverse-designed photonic devices. Meanwhile, existing fabrication-aware inverse-design methods apply soft penalties on small features and sharp curvatures, but still cannot guarantee design-rule-compliant final layouts. In this work, we present OptiClear, a curvilinear design rule legalization framework for inverse-designed photonic devices. OptiClear provides two complementary legalization engines: OptiClear-R, a rule-based morphological legalizer that efficientlyresolves violation regions through iterative morphology-guided mask processing, and OptiClear-D, a differentiable legalizer that formulates legalization as a minimum-distortion mask optimization problem under morphological stationary-point constraints, explicitly seeking a rule-compliant layout with minimal geometric deviation from the original design. We further develop customized differentiable morphological GPU operators that significantly improve the scalability of high-resolution mask legalization. Comprehensive evaluation across diverse inverse-designed photonic devices and a wide range of design- rule settings shows that OptiClear reduces design-rule violations from thousands to zero. The rule-based legalizer offers high runtime efficiency, while the differentiable legalizer more faithfully preserves the original optical functionality. This work establishes curvilinear design rule legalization as a practical post-design electronic-photonic design automation (EPDA) stage for translating high-performance inverse-designed photonic layouts into manufacturable tape-out-ready devices. More broadly, the differentiable formulation also opens the door to future end-to-end design-rule-aware curvilinear inverse hardware design. We will open-source the codes.

ABSTRACT. Modern neural network accelerators commonly exploit operation fusion using intra-layer dataflows to minimize data movement. However, in Input Stationary (IS) and Weight Stationary (WS) dataflows, partial sums (PSUMs) are frequently accessed off-chip, leading to high off-chip traffic. A straightforward solution is to quantize them statically, but this often causes significant accuracy degradation. Our analysis of PSUM data distribution reveals that outliers cause small values to be underrepresented during quantization. As a solution, a fine-grained Dynamic PSUM quantization (DPSQ) scheme is proposed to enhance quantization robustness. To address the energy overhead of dynamic quantization, we propose quantization with mixed granularity in which only the outlier-sensitive portion is dynamically quantized in a fine-grained manner. We evaluate our methodology by developing a specialized accelerator architecture tailored for Transformer-based models. Experimental results confirm that our method significantly reduces off-chip memory traffic while maintaining high numerical precision.

ABSTRACT. Conventional low-bit LLM quantization prioritizes accuracy while forcing hardware to absorb the overhead of reconciling token generation, quantization granularity, and matmul flow misalignment through buffering, data reformatting, and high-precision recovery on the decoding critical path. We reverse this accuracy first paradigm with AlignQuant, an alignment aware two-stage integer microscaling framework designed for native systolic execution. First, adaptive high-bit quantization minimizes mapping error while retaining compatibility with standard integer MAC units. Second, group-wise significance aware truncation produces a compact 4-bit representation whose shift flags naturally align with the matmul dataflow. AlignQuant thereby resolves attention score–value quantization and matmul misalignment while preserving regular systolic execution. Even under the aggressive W4A4KV4SQ8 configuration, AlignQuant outperforms prior methods in accuracy while reducing area by 40.11%, achieving a 2.27× speedup, and cutting energy consumption by 32.36%.

ABSTRACT. In edge-AI accelerators, nonlinear activation functions such as tanh, sigmoid, and softmax are key latency and cost contributors in post-accumulation datapaths. CORDIC-based designs provide an efficient hardware approach to these activation functions, and recent work has replaced IEEE 754 with Posit format to improve accuracy at low bit widths. However, existing Posit-CORDIC designs still rely on fixed iteration schedules. Posit decoding is used mainly for format conversion, while the decoded regime, exponent, and fraction fields remain underutilized for computation control. This paper designs PDG-CORDIC, a lowlatency Posit-decode-guided CORDIC algorithm that uses decoded Posit fields to guide hyperbolic and linear CORDIC iterations. The proposed method supports input-scale-aware scheduling, bypass selection, and adaptive termination while maintaining bounded numerical error. Based on PDG-CORDIC, we develop a parallel tanh architecture and extend it to sigmoid and softmax units. PDG-CORDIC reduces the critical path delay by 41.7%–45.2% for 12-bit tanh, 37.8%–42.1% for sigmoid, and 20.2%–30.9% for softmax,within a 28-nm TSMC physical-synthesis evaluation.

ABSTRACT. Diffusion Transformers (DiTs) have become a dominant backbone for high-quality image and video generation, but their iterative denoising process repeatedly invokes deep Transformer blocks and causes substantial computation and memory traffic. Existing cache- based and prediction-based acceleration methods reduce redundant computation, yet they often introduce additional residual-state storage and irregular memory accesses, limiting practical hard- ware efficiency. This paper proposes APRQ, an adaptive prediction- driven residual quantization accelerator for DiT inference. APRQ jointly optimizes prediction scheduling and residual data move- ment through two key techniques. First, it dynamically adjusts prediction strategies across timesteps and layers to avoid ineffec- tive high-cost prediction. Second, it exploits the low-magnitude characteristics of prediction residuals with mixed-precision quanti- zation, reducing residual storage and memory traffic. A lightweight on-chip management mechanism further keeps frequently reused residual states close to the compute units. With a dedicated hard- ware engine, APRQ translates algorithmic prediction into practical acceleration. Experiments demonstrate that APRQ achieves 7.03× speedup and 7.11× energy-efficiency improvement over an NVIDIA A100 GPU and 1.60× speedup and 36% energy savings over ViDA, with negligible generation-quality degradation.

ABSTRACT. Coarse-grained reconfigurable arrays (CGRAs) are emerging as promising unified accelerators for general-purpose and AI workloads because of their programmability. However, supporting diverse workloads requires high-precision datapaths, which limit inference efficiency for quantized large language models (LLMs) compared with dedicated low-precision AI accelerators. Direct integration of existing multi-precision arithmetic units imposes substantial area overhead, degrading the area efficiency of CGRAs.To address this challenge, we propose a hardware--software co-design approach that augments FP32 datapaths with only lightweight integer extensions and exploits the reconfigurability of CGRAs to efficiently support finer-grained quantization. Our experimental results demonstrate that the proposed design enables 8-bit and 4-bit integer-quantized LLMs to retain over 99% and up to 98% of BF16-level inference accuracy, respectively. At comparable accuracy, the proposed design reduces GEMM energy by up to 55% and area by 26% compared with an FP8-enabled CGRA, while achieving throughput comparable to that of a dedicated AI accelerator.

ABSTRACT. Block-scaled quantization formats such as OCP Microscaling (MX) and NVFP4 have been widely adopted as efficient data formats for LLM inference. However, the design space of these formats spanned by shared scale format, weight, and activation format combinations has not been systematically explored, and the joint accuracy–silicon tradeoff across this space remains uncharacterized, leaving the true Pareto-optimal configurations for NPU-based edge LLM deployment an open question. To bridge this gap, we conduct a joint hardware–software (HW–SW) co-design exploration of the above underexplored MX-like design space with three innovations. 1) We define and systematically characterize the full 8-bit scale format family within the MX-like design space, jointly with asymmetric weight-activation precision, identifying configurations that outperform both MX and NVFP4. 2) We build a per-format specialized MAC datapath template that enables fair hardware cost evaluation across the space. 3) We develop an automated co-design flow, integrated into the open-source SNAX NPU platform, that enables joint HW-SW analysis across the design space. Overall, our co-design exploration reveals that scale format matters only under the aggressive FP4 quantization, yielding a case-oriented design guideline for both scale format and asymmetric weight-activation precision. We further identify UE5M3 as the optimal scale format for the FP4 regime, reducing perplexity degradation by up to 5.8% relative to NVFP4, at a cost of only +0.06% area and +0.49% power overhead.

ABSTRACT. 2.5D chiplet integration offers a practical way to combine different computing and memory dies in one package. However, placement of chiplets must balance wirelength, placement legality, and temperature. A compact placement can shorten some connections, but it may also create thermal hotspots. Existing methods often rely on costly search, separate legalization, or thermal models that require training data and parameter tuning. This paper presents SpectraPlace2.5D, a thermal-aware placement framework for 2.5D chiplet systems. SpectraPlace2.5D first builds a topology-guided seed from bus-level connectivity. It explores chiplet rotations and relative positions, then converts the selected topology into initial coordinates and orientations. The seed is used as a warm start for a Mixed Integer Linear Programming(MILP) model. The model jointly handles chiplet positions, orientations, interposer boundaries, non-overlap constraints, wirelength, and the peak temperature, so every feasible solution is already legal. For fast temperature evaluation during placement, SpectraPlace2.5D uses a spectral thermal model based on Green’s function. By decomposing heat conduction into cosine modes, the method achieves speedups of several thousand times with a single precomputation without requiring any data-driven training. Experiments on ten public benchmarks show that, compared with ATPlace2.5D, a state-of-the-art framework, SpectraPlace2.5D reduces wirelength by 9.0% in wirelength-driven placement. In thermal-aware placement, SpectraPlace2.5D reduces wirelength by 27.1%, lowers the maximum chiplet temperature by 1.52 K, and reduces the total runtime by 29.0%.

ABSTRACT. Chiplet placement on the interposer directly impacts interconnect quality, thermal reliability, and manufacturing cost, yet prior works have addressed wirelength, thermal, or area optimization independently without considering the physical constraints of die-to-die interconnects. In this paper, we propose a thermal-aware chiplet placement framework that jointly optimizes chiplet shapes, positions, D2D module positions, and thermal distribution while satisfying the physical constraints of die-to-die interconnects. The proposed method constructs a connectivity graph from the netlist and applies a force-directed algorithm to extract the relative chiplet topology. Based on this topology, chiplet placement is formulated as a nonlinear optimization problem and solved using Interior Point OPTimizer (IPOPT), where a thermal objective is minimized subject to D2D module alignment and interconnect constraints. A grid-based thermal solver is directly integrated into the NLP formulation, enabling efficient gradient-driven thermal optimization within the placement loop. Experimental results on benchmarks with up to 32 chiplets show that the proposed framework produces placement solutions with a peak temperature competitive with state-of-the-art placers and a shorter total wirelength, while being the only method to satisfy the die-to-die interconnect constraints.

ABSTRACT. As 2.5D heterogeneous integration becomes a key enabler for extending Moore’s law, automated chiplet placement has emerged as a critical bottleneck in package-level design. This problem requires jointly optimizing wirelength and peak temperature in a highly non-convex search space, where state-of-the-art (SOTA) analytical placers may become trapped in local optima.

To address this challenge, we propose ERL-Placer, a chiplet placement framework that couples Evolutionary Reinforcement Learning (ERL) with Monte Carlo Tree Search (MCTS) to improve global exploration under the coupled wirelength–thermal objective. ERL-Placer first employs a Dependency-Aware Placement Sequencer (DAPS) to determine a chiplet order that reduces search complexity while prioritizing modules that are more important to the overall objective. It then uses a hybrid ERL–MCTS engine, supported by a dual-mode physics engine that combines fast search guidance with accurate multi-objective evaluation, to explore candidate placements and refine high-quality solutions.

On ten public 2.5D cases, ERL-Placer reduces geometric-mean wirelength by 6.0% and peak temperature by 0.65°C compared to the SOTA analytical placer. On the five larger cases, these improvements further increase to 15.2% and 1.34°C. These results show that ERL-Placer is particularly effective on large benchmarks for high-quality joint wirelength–thermal optimization, with even stronger advantages on more challenging design instances.

ABSTRACT. With advances in packaging technologies, rising interconnect density in redistribution layers makes further wirelength reduction challenging. Fortunately, iteratively refining chip positions and net pin assignments offers an effective way to reduce inter-chip signal wirelength. However, repeated router invocations are time-consuming, and conventional metrics may not accurately reflect the actual wirelength of net pin assignments. To address these issues, we propose a HeteroGNN-based hierarchical co-optimization framework that reduces wirelength while ensuring routability. First, we develop a differentiable floorplan refinement engine that optimizes chip positions using a smooth wirelength objective and dynamically adjusts the learning rate for stable gradient descent. Second, we design a HeteroGNN-based routability predictor that constructs an FOWLP-specific heterogeneous graph and models inter-entity interactions through relation-specific message passing for rapid routability prediction. Finally, we propose an XGBoost-based ranking model that ranks candidate pin assignments more consistently with actual wirelength rankings than HPWL, thereby improving pin assignment quality. Compared with previous router-in-the-loop flow, the proposed framework reduces routed wirelength by 5% and achieves a 2.30× speedup.

ABSTRACT. With the evolution of advanced packaging such as interposers and chiplet-based integration, the co-design of signal routing and power delivery networks (PDNs) has become critical. Constrained by limited interposer layers, efficiently sharing the same physical layer for high-density signals and multi-voltage power planes is urgently needed. Traditional decoupled designs often cause routing congestion and IR drop violations while underutilizing same-layer vacant space, leading to redundant total layers. To address this, we propose a three-stage signal–power co-design framework jointly optimizing same-layer routing and PDN synthesis. First, pre-routing occupancy is mapped to a routing fragmentation-aware grid resistance model for IR-drop pre-evaluation, establishing an initial layer allocation via the Hungarian algorithm and generating routing guidance comprising hard blockages and dynamic soft penalties. Second, an IR-drop-driven 3D detailed routing strictly enforces Ground-Signal-Ground (GSG) shielding while utilizing this guidance to actively avoid PDN-critical regions, reserving physical space for same-layer power planes. Finally, during PDN synthesis, resistance maps are updated to reflect actual routing-induced bottlenecks, layer assignments are refined, and multi-voltage power planes are constructed using an IR-drop-driven Breadth-First Search (BFS) competitive expansion and cross-layer invasion strategy. Experimental results demonstrate that this method effectively reduces total layers without violating IR drop thresholds, achieving a balance between signal wirelength and overall resource utilization.

ABSTRACT. Advanced packaging integrates multiple dies through Redistribution Layers (RDLs), and each additional RDL raises the manufacturing cost. The primary objective of this work is therefore to minimize the number of routing layers, and the total wirelength is a secondary objective. Two manufacturability constructs make this objective hard to reach. The teardrop avoids abrupt changes in the line width, and the offset via disperses the vias across adjacent layers to raise the manufacturing yield and to prevent via channel collapse. However, the offset via occupies routing resources on two layers at once, which complicates the routing resource planning. This work proposes a framework that maximizes the available routing resources. It applies a force directed offset via placement algorithm to find the appropriate locations for the offset vias, a network flow based algorithm to determine the routing order, and a linear regression model in the pathfinding. Compared with prior work, our router completes the routing with fewer layers under the offset via and teardrop constraints.

ABSTRACT. Regression runs have a useful shape: one compiled RTL design, many independent seeds. TensorLUT uses that batch dimension to run 2-state, single-clock LUT/DFF simulation on NVIDIA tensor cores. A Boolean AND is true exactly when the popcount of its inputs equals their number, and an XOR is a parity, so writing each LUT layer in algebraic normal form (ANF) turns a clock edge into two single-bit and.popc matrix products: one plus a degree check builds the AND terms, a second plus parity produces the outputs. A tensor-core-aware compiler routes affine cones to a single GF(2) GEMM, lowers bounded nonlinear cones to term-reduced ESOP, and tiles wide cones as levelized LUT-ANF, all preserving the synthesized LUT semantics and validated bit-for-bit against Icarus Verilog. On one RTX 4090, TensorLUT reaches up to 3.0 x 10^9 cycle-stimuli/s on algebraic microbenchmarks, and on RTeAAL's RocketChip core it sustains 8.2 x 10^6, a 206x speedup over a single Verilator process, using about 8x less GPU memory than a non-tensor-core CUDA baseline.

ABSTRACT. Accurate thermal and displacement field prediction is crucial for optimizing advanced packaging designs. While operator learning surrogates offer orders-of-magnitude speedup over traditional finite element solvers, existing approaches largely ignore symmetry, requiring large amounts of training data and exhibiting poor generalization beyond the training distribution. In this paper, we present a unified equivariant operator learning framework that directly incorporates two physical symmetries --- scaling homogeneity and D4 spatial equivariance --- into the network architecture through norm factorization and equivariant convolutional kernels. Across both thermal and warpage domains, our model achieves mean absolute errors (MAEs) comparable to or lower than those of strong baselines trained with data augmentation. Moreover, it extrapolates exactly to input scales far beyond the training range, whereas augmentation-based baselines degrade substantially.

ABSTRACT. High-Level Synthesis (HLS) design-space exploration (DSE) commonly obtains accelerator cycle counts with a fixed or user-specified external-memory latency. This abstraction is convenient, but it is not selection-faithful for irregular, memory-bound accelerators: changing cores, hardware threads, memory endpoints, or address interleaving changes request overlap, ordering, and contention, so the omitted memory timing error is configuration-dependent and compounds across the design space. We connect multi-threaded graph accelerators generated by the open-source HLS tool Bambu to an open-source cycle-accurate memory simulator Ramulator 2’s HBM2 backend. We compare this framework with fixed latencies of 2, 8, and 20 cycles (denoted by Fix2, Fix8, Fix20). Fix2 is the default memory latency specified in the Bambu HLS tool, Fix8 is the most favorable empirical single-constant approximation in our experiments, and Fix20 is the delay used by the source accelerator template and an optimistic HBM proxy. We evaluate six decisions across two GAPBS graph benchmarks: PageRank and triangle counting. We observe that, fixed latency reverses the cycle-minimizing memory bank/channel count choice, and reverses chunk-size choices only when the bank count is low, causing up to 9.8% runtime selection penalty. It also understates the value of temporal multithreading enough for Fix2 to choose a lower-thread design, causing 5.2% and 19.2% area-delay penalty, even though the raw cycle order is unchanged. No tested constant preserves all six decisions. We demonstrate that a validated, stateful DRAM/HBM simulator like Ramulator backend for external memory is therefore not merely an accuracy refinement for this class of memory-bound HLS DSE; it is required to rank memory-parallel configurations reliably.

ABSTRACT. Feature-scale plasma process simulation requires coupled particle transport, surface interaction, and dynamic topography evolution. For this purpose, we propose VoxPMC, a parallel accelerated voxel- based particle Monte Carlo (PMC) simulator. It aggregates particles into bundles that propagate collectively and then make surface re- actions via multinomial and binomial sampling, significantly reduc- ing per-particle computations while maintaining geometric fidelity. To accelerate dynamic topography evolution, VoxPMC employs a cache-aware two-level voxel organization with using cache-line- aligned atomic integers. This data structure improves spatial locality and enables lock-free compare-and-swap (CAS) updates, minimiz- ing synchronization overhead. The experiment on diverse test cases with the bundle size 10 shows up to 103× speedup of VoxPMC over the per-particle serial-computing baseline. Compared to Sentaurus Topography 3D, VoxPMC delivers from 1.5× to 5.5× speedup with high geometric fidelity under the setting of 16-thread computation.

ABSTRACT. Aging-aware standard-cell timing characterization requires costly transistor-level simulation across cell families and operating condi- tions. Existing accelerators mainly reduce sampling within char- acterized families, leaving sparse family-level transfer unresolved. We present Sparse Aging-aware Graph-learning for Timing charac- terization (SAGET) for selection-informed prediction within a fixed library. Offline Logic-Class-Aware Family Selection organizes full- library singleton evidence to design a 44-family predictor-training set, after which mRMR refines 317 graph features to 278 effective dimensions and the SAGET GNN predicts delay and output slew. The final predictor is supervised only by these 44 families and eval- uated across 74 combinational families from the ASAP7 7.5-track regular-threshold-voltage (RVT) standard-cell library, including 30 predictor-untrained families. The primary SAGET run satisfies the strict criterion for all 74 families, requiring both targets to achieve 𝑅2 > 0.95, RMSE < 5 ps, and MAPE < 10%. It achieves delay 𝑅2 = 0.9945 with 1.62 ps RMSE and slew 𝑅2 = 0.9984 with 1.26 ps RMSE; the best same-protocol evaluated tabular baseline satisfies 57 families. Deployed SAGET inference is 421.4× faster than estimated full-SPICE truth generation over the same task scope. Together, these results indicate that SAGET can support simulation-efficient timing characterization in future standard-cell library development.

ABSTRACT. Abstract Accurate high-sigma yield estimation requires resolving rare cir- cuit failures in high-dimensional process-variation spaces, where exhaustive transistor-level Monte Carlo (MC) simulation is prohibi- tively expensive. Surrogates can screen large populations cheaply, but flat models do not explicitly exploit device organization, and directly counting predicted failures can turn small threshold errors into large probability bias. We present HOIST, a device-structured and SPICE-validated framework that separates failure discovery from probability estimation. A shared device encoder, global circuit context, and multiplicative local–global fusion provide an explicit pathway for coordinated mismatch. An always-on attention residual head further refines high-risk ordering with a fixed label budget and a strictly positive calibration scale. The frozen models process a finite MC population in two bounded-memory passes, retaining complementary failure-prone and boundary-sensitive candidates for direct validation. Fixed score strata and fresh uniform audits provide an unbiased fallback for failures missed outside Top-𝐾; model predic- tions are not final failure labels. Experiments on SRAM benchmarks with 18–1203 process variables evaluate failure-probability error and total transistor-level simulation cost against representative high- sigma yield-analysis baselines. HOIST requires 2,848–5,336 SPICE simulations with 2.59%–8.28% relative failure-probability error and achieves average speedups over six baselines of 3.76×, 7.73×, and 6.64× on three cases, respectively (6.04× overall).

ABSTRACT. Sparse general matrix–matrix multiplication (SpGEMM) suffers from irregular memory accesses and workload imbalance. Although bank-level DRAM processing-in-memory (PIM) reduces off-chip data movement, its limited local storage makes dataflow and matrix partitioning critical. SPIMA employs outer-product dataflow and two-dimensional 𝑀–𝑁 partitioning, but its two-dimensional accumulation scope increases buffer demand, while insufficient non-zero overlap along 𝐾 can underutilize banks. We propose GD-PIM, a lightweight DRAM-PIM architecture combining row-wise Gustavson dataflow, an Output Row Buffer (ORB), and 𝑀-dimension partitioning. GD-PIM limits active partial sums to one output-row segment and assigns disjoint output rows to banks, avoiding overlap-dependent empty tiles and cross-bank reduction. Indirect row address generation and atom-level operand filtering support irregular B-row accesses. With 48 PIM banks, GD-PIM achieves geometric-mean speedups of 11.8× and 2.56× over SPIMA using equal 4KB and 64KB per-bank buffers, respectively, including host-side processing, data transfers, and PIM execution.

ABSTRACT. Row-wise sparse matrix--matrix multiplication (SpGEMM) is well suited to field-programmable gate array (FPGA) acceleration because it avoids repeated row--column index matching. However, on high-bandwidth-memory (HBM)-equipped FPGAs, improved delivery of irregular $B$ rows exposes two additional performance bottlenecks: comparison-based mergers repeatedly identify, combine, and order partial products that collapse into the same output entries, while direct row-to-port mapping can create transient contention across parallel HBM ports. To address both bottlenecks, we develop a row-wise SpGEMM accelerator that combines the Bitmap-based Address-Aware Accumulator (BAAA) with the cache-free Static-4R and Boundary-Padded CSR Scheme (BPCS) memory organization. BAAA directly indexes the FP32 accumulation state by output column and uses a hierarchical bitmap to emit completed rows in compressed sparse row (CSR) column order, eliminating comparison-based merging. Static-4R statically partitions the HBM data-delivery organization into four lane-private producer domains, each bound to one lane group and backed by a local replica of the read-only matrix B, while BPCS applies bounded padding to improve physical address placement. Experimental results demonstrate that SpGEMM achieves a geometric mean (geomean) speedup of 3.06$\times$ compared to the state-of-the-art (SOTA) FPGA-based SpGEMM accelerator. In the same-platform comparisons, its BAAA backend achieves average speedups of 1.53$\times$ over SOTA merger backends. Moreover, Static-4R+BPCS reduces the normalized cycle count from 1.00 for direct mapping to 0.34.

ABSTRACT. Mixture-of-Experts (MoE) architectures enable scalable large language models (LLMs) by activating only a sparse subset of experts for each token. However, dynamic routing introduces irregular expert workloads, quantization-granularity mismatch, and redundant data movement, limiting the efficiency of existing routing-agnostic accelerators. This paper presents RACE-FFN, a runtime-adaptive heterogeneous architecture that co-executes MoE FFNs on a systolic array (SA) and an SRAM-CIM engine. We propose Runtime-Adaptive Co-Execution (RACE) to mitigate routing-induced workload imbalance by exploiting the complementary characteristics of the two engines and enabling bidirectional idle-engine assistance, thereby improving hardware utilization and reducing inference latency. We further propose Routing-Aware Progressive Quantization (RAPQ), which uses runtime routing scores to support engine-aligned dual-granularity precision adaptation, reducing unnecessary refinement-weight accesses and DRAM traffic. Finally, Routing-Aware Token and Expert Ordering (RATEO) jointly reorders expert execution and token issue to improve on-chip data reuse and shorten partial-sum lifetime. Compared with prior MoE accelerator, RACE-FFN improves the average speedup by 37.3% and reduces energy consumption by 10.4%, while limiting the average downstream-task accuracy loss to 0.59 percentage points.

ABSTRACT. Processing-in-Memory (PIM) on monolithic 3D (M3D) DRAM is a promising answer to the memory wall for data-intensive dynamic programming (DP), yet extracting its performance today demands hand-written kernels: the programmer must pick a tile size, place data across non-uniform-latency memory tiers, partition work between heterogeneous processing units, and insert the right broadcasts and queues by hand. We present GenMLIR, an MLIR compiler that automates this mapping for tier-aware 3D PIM. GenMLIR encodes the semi-ring generalized grid update, the algebraic form shared by all-pairs shortest path (APSP) and sequence alignment, as a first-class IR abstraction, and lowers it through four GenDRAM-aware pass groups that derive blocked tiling, tier-aware placement, tile-to-PU assignment, and explicit communication. We also characterize precisely which DP recurrences the abstraction admits and which it does not. On the GenDRAM architecture, GenMLIR-generated code runs up to 5.8× (APSP) and 16.7× (alignment) faster than a lowering without compiler support, and 1.2–1.4× faster than a standard affine-tiling PIM compiler we also implement, reaching 90–100% of an achievable-performance bound. It expresses these workloads in 4–9 lines instead of ~300–500 and compiles in a negligible fraction of runtime.

ABSTRACT. Retrieval-Augmented Generation (RAG) relies on large-scale Approximate Nearest Neighbor Search (ANNS) to retrieve semantically relevant context for large language models. Among ANNS methods, IVF-PQ offers an attractive balance between memory efficiency and search accuracy. However, achieving high recall requires reranking which fetches full-precision vectors for reranking, and the billionscale vector databases need to reside in CPU DRAM or SSD due to the limited capacity of GPU HBM. This off-GPU data movement introduces substantial latency and throughput degradation. We propose HAVEN, a GPU architecture augmented with High-Bandwidth Flash (HBF) which is a recently introduced die-stacked 3D NAND technology engineered to deliver terabyte-scale capacity and hundreds of GB/s read bandwidth. By integrating HBF and near-storage search unit as an on-package complement to HBM, HAVEN enables the full-precision vector database to reside entirely on-device, eliminating PCIe and DDR bottlenecks during reranking. Through detailed modeling of re-architected 3D NAND subarrays, power-constrained HBF bandwidth, and end-to-end IVFPQ pipelines, we demonstrate that HAVEN improves reranking throughput by up to 20× and latency up to 40× across billion-scale datasets compared to GPU-DRAM and GPU-SSD systems. Our results show that HBF-augmented GPUs enable high-recall retrieval at throughput previously achievable only without reranking, offering a promising direction for memory-centric AI accelerators.

ABSTRACT. Ising model-based annealers have emerged as promising hardware platforms for solving NP-hard combinatorial optimization problems (COPs), and compute-in-memory (CIM) based Ising annealers further offer notable advantages in reducing data movement. However, for large-scale Traveling Salesman Problems (TSPs), conventional analog CIM-based annealers suffer from inefficient mapping, as sparse weights around the array diagonal require oversized arrays, causing low utilization, severe IR drop, and degraded accuracy; meanwhile, sequential simulated annealing (SA) limits convergence speed. To address these challenges, this work presents an area-efficient CIM-based Ising annealer with two key innovations. First, a folded mapping scheme compacts sparse weights into a significantly smaller CIM array, improving utilization and mitigating IR-drop-induced accuracy degradation. Second, a Cooling-scheduled Parallel Swaps Strategy enables parallel spin swaps, accelerating annealing without compromising convergence quality. Evaluated on 29- to 150-city TSPs under a fully connected Ising model, the proposed design achieves up to 99.9% of the theoretical optimum while reducing normalized area by up to 68% and time-to-solution by 25% compared with state-of-the-art designs.

ABSTRACT. In 4D Gaussian Splatting (4D-GS), the per-frame rendering pipeline repeatedly fetches Gaussian primitives from off-chip memory before evaluating their temporal validity at the current timestamp. This fetch-then-filter execution flow causes redundant off-chip memory traffic and unnecessary computations since many fetched Gaussians are temporally invalid and do not contribute to the rendered frame. In this paper, we present TempoGS, a temporal-validity-aware Gaussian loading scheme for memory-efficient 4D-GS acceleration. First, temporal binning divides input sequence into temporal bins and organizes Gaussians into compact groups, so that renderer can access only the group associated with the input timestamp. Second, expiration-aware Gaussian loading skips the Gaussians that are no longer temporally valid before parameter fetch during forward-time rendering, thereby reducing intra-bin Gaussian fetches and unnecessary processing of expired Gaussians. To efficiently support this loading scheme, we present a 4D-GS accelerator architecture and temporal-validity-aware dataflow that integrate temporal bin selection and expiration checking, enabling temporally invalid Gaussians to be filtered before off-chip parameter fetch. By integrating TempoGS with the proposed accelerator architecture, the off-chip Gaussian parameter accesses are reduced, thus improving energy efficiency while achieving real-time rendering speed.

ABSTRACT. Visual Autoregressive (VAR) is a novel visual generative paradigm that generates images via a ``next-scale prediction'' approach. Compared to traditional next-token prediction and diffusion methods, it achieves better generation quality. However, this generation approach still faces the following challenges: \textbf{(1)} The size of the generated token maps increases in a superpolynomial manner, leading to significant attention computation overhead; \textbf{(2)} The information of previously generated token maps is buffered as KV Cache, resulting in large memory overhead; \textbf{(3)} The latter scales used to model fine-grained details require far more GEMM computation than the earlier scales used to model the image. These characteristics make VAR models distinct from traditional generative models.

To address these issues, we propose SSR-VAR, a hardware-software co-design method for lightweight VAR inference that exploits the spatial-aware and scale-aware redundancy: then propose \textbf{(1) Spatial-based Two-level Locality Attention Mask Design and Scheduling} for attention computation simplification, \textbf{(2) Scale-based KV Cache Pruning and Memory Mapping} for KV Cache memory reduction, and \textbf{(3) Scale-based Mixed Precision Computation and Array Design} for GEMM's efficiency. Experiments show that on a resource-aligned simulation on the NVIDIA RTX 6000 Ada GPU, SSR-VAR can achieve up to 5.15$\times$ memory reduction and up to 6.13$\times$ computation acceleration across different VAR models.

ABSTRACT. Diffusion models have shown remarkable success on content generation while suffering from substantial computational overhead due to the iterative denoising process. Token-wise caching Diffusion (TC-DM) mitigates redundant computation by selectively activating critical tokens while caching the rest, shifting the workload characteristic from compute-bound to memory-bound. Meanwhile, 3D-stacked architecture provides a promising solution to alleviate the bandwidth bottleneck. In this work, we propose DREAM, an algorithm–hardware co-design architecture for efficient token-wise caching Diffusion deployment. DREAM adopts a 3D-stacked logic-to-DRAM architecture with a resource-aware dynamic mapping to maximize pipeline parallelism. To support the proposed mapping strategy, a content-addressable memory (CAM) based scheduler is developed to manage runtime token dependencies and efficiently allocate tasks to core groups. Comprehensive evaluations on image and video generation workloads demonstrate that our DREAM architecture significantly improves 1.97x/1.91x performance and 1.9x/2.1x energy efficiency over 2D multi-core baseline on image/video generation tasks.

ABSTRACT. 3D diffusion policies have shown strong performance in instruction-conditioned robotic manipulation by grounding scene representations and robot actions in a shared 3D workspace. However, their diffusion-based action heads repeatedly process long 3D scene-token sequences across multiple denoising steps, causing severe latency overhead for edge-side closed-loop control. Although our analysis reveals substantial token redundancy, with only 42% task-relevant tokens and 15% temporally changed tokens on average, existing token compression methods are not directly suitable for 3D robotic policies. Token pruning may destroy local topology and remove contact-critical regions, while conventional token merging lacks spatio-temporal priors and introduces online matching and irregular memory-access overhead. To address these challenges, we propose a token-merging accelerator built around 3DToMe, an interaction-aware 3D token merging method with co-designed hardware execution. 3DToMe performs locality-constrained token merging guided by task relevance and temporal-change cues, while the proposed accelerator integrates a Morton-locality-based merge engine and a merge-aware Transformer core. Experiments show that 3DToMe reduces scene tokens by 75% with negligible loss in manipulation performance. The co-designed accelerator delivers 6.4× and 15.3× end-to-end speedups over the dense accelerator and an RTX 3090 GPU, respectively, and supports action generation at over 30 Hz, highlighting its suitability for real-time edge-side 3D robotic control.

ABSTRACT. Real-time super-resolution (SR) remains challenging for edge devices. Although deep-learning-based SR methods achieve high reconstruction quality, their heavy multiply-accumulate (MAC) operations incur substantial resource and power costs, limiting practical deployment. Lookup-table (LUT)-based SR offers a more efficient alternative by replacing convolutional inference with precomputed table queries. However, existing LUT-based methods still suffer from limited speed, high storage overhead, and restricted scalability across upsampling factors. This paper presents ScaleLUT, a hardware-oriented LUT design framework and fully parallel reconfigurable accelerator for real-time multi-scale SR. By jointly optimizing LUT design and hardware implementation, ScaleLUT achieves competitive SR performance with high hardware efficiency. Specifically, a hardware-friendly YUV-domain strategy and a power-of-two kernel design with rotation ensemble are introduced to improve receptive-field (RF) coverage while reducing LUT dimensionality, where the latter further simplifies hardware by replacing division operations with shift operations. Together, these designs yield an 18.4% memory reduction over state-of-the-art (SOTA) LUT-based SR methods. Furthermore, ScaleLUT supports arbitrary input resolutions and configurable ×2ⁿ upsampling factors with a deeply pipelined and massively parallel architecture that fully exploits the multiplication-free nature of LUT inference. Implemented on a Xilinx ZCU102 FPGA, ScaleLUT achieves real-time 4K SR at 95.3 FPS for ×2 upscaling at 300 MHz. Compared with existing SR accelerators, it uses at least 58.6% fewer LUTs, 41.1% fewer flip-flops, zero DSPs, and 42.0% lower power. It also delivers 10× and 1.2× speedups over the best CPU-based SR implementation and prior FPGA-based SR accelerators, respectively. Overall, ScaleLUT demonstrates the effectiveness of joint LUT algorithm–hardware co-design for practical and energy-efficient edge SR deployment.

ABSTRACT. The Fast Extract (FX) algorithm is a classical divisor extraction method designed to rapidly merge shared logic across the Boolean network. It is often paired with prevalent AIG optimizations to transcend their local scope, providing a complementary global perspective that unlocks further logic reduction. However, the massive scale of modern circuits renders this process computationally expensive, creating a severe scalability bottleneck. To address this issue, this paper proposes GARDEN, a GPU-Accelerated Rapid Divisor Extraction algorithm based on FX. By highly parallelizing the generation and extraction processes of candidate divisors, our approach achieves an 89.0× speedup and a 6.9% reduction in literals compared with ABC’s optimized FX implementation. Furthermore, when GARDEN is interleaved with AIG optimizations, the end-to-end GPU sequence achieves a 54.4× speedup over ABC while reducing area and delay by 2.2% and 4.6%, respectively.

ABSTRACT. Compression-tree (CT) optimization primarily targets area and delay; fixed-skeleton workload power remains underexplored. A fixed CT skeleton still admits a vast function-preserving rewiring space, whose exploration is bottlenecked by workload- and timing- accurate gate-level simulation and power analysis for every candidate. GA2-CT compiles the skeleton once and evaluates candidate populations with a batched GPU simulator that models glitches explicitly, without a learned power proxy, at roughly 600× the throughput of a commercial-flow lane. This acceleration enables a timing-constrained genetic algorithm to explore the rewiring space at scale. Commercial EDA confirms lower pre-layout power than the IP across all nine multiplier, MAC, and digital compute-in-memory (DCIM) configurations, by up to 28.6%; post-route MUL/MAC gains reach 23.7%. Code, benchmarks, and search hyperparameters are released in an anonymous repository.

ABSTRACT. Delay-oriented logic optimization faces efficiency issue as the scale of VLSI designs grows. Since extensive SOP generation incurs sub stantial runtime overhead during delay optimization, it is essential to accelerate this procedure for obtaining overall speed-up. This paper proposes a fully GPU-accelerated delay-oriented logic op timization framework whose core component is a fine-grained GPU-parallel SOP generation algorithm with minterm-level par allelism for both original and complemented functions. Our algo rithm our algorithm achieves 15.2× speed-up on average without quality degradation compared with ABC. When combining our delay-oriented optimization with resyn2, a full-GPU accelerated resyn_sop sequence obtains 12.1× acceleration over ABC.

ABSTRACT. Heterogeneous LogicFolding three-dimensional (3D) ICs vertically stack logic tiers of different technology nodes. They require electronic design automation (EDA) tools to be 3D-aware across different design stages. However, existing 3D IC flows perform logic synthesis before tier partitioning. This makes logic synthesis unaware of both tier-specific technology characteristics and cross-tier interconnect costs. As a result, there is a significant gap between logic synthesis and the final 3D physical implementation. In this paper, we propose 3D-Syn, the first 3D-aware Synthesis flow for heterogeneous LogicFolding 3D ICs. 3D-Syn first constructs a coarse-grained netlist for tier partitioning. Since the flow needs to know the area of each coarse-grained unit under each tier’s technology library, we propose a graph neural network-based method to estimate its post-route area. Based on the partitioning results, 3D-Syn synthesizes each tier using its corresponding library while considering cross-tier interconnect delay. Experimental results show that 3D-Syn improves post-route power, performance and area (PPA) over the conventional synthesis-first flow.

ABSTRACT. Sequential cells, such as latches (LATs) and flip-flops (FFs), are PPA-critical components of modern standard-cell libraries because they are widely instantiated and directly connected to the clock network. However, their transistor-level topologies are still developed through manual circuit design, while existing exact transistor-network synthesis methods primarily target combinational cells. This paper presents SES, to our knowledge, the first exact transistor-network synthesis framework for sequential standard cells. SES formulates LAT and FF synthesis as multi-output-guided transistor-network synthesis by cutting feedback loops and exposing feedback-related signals as additional inputs and outputs. To enable robust and low-power sequential-cell synthesis, we introduce three sequential-cell-aware techniques: race-aware data-hold constraints for reliable state retention, clock-toggle power constraints for suppressing hidden internal switching, and floating-aware synthesis for exploring compact and power-efficient topologies. The synthesized candidate networks are validated through circuit-level simulation using an industrial 4-nm FinFET PDK. Among the validated candidates, our synthesized FF SES-FF (22/8/205) achieves 1.04x the frequency and 0.70x the power of a conventional TGFF. We then generate a layout for the selected synthesized FF and evaluate its block-level impact. Replacing the baseline FF with SES-FF (22/8/205) achieves up to a 5% area reduction, an 18% power reduction, and a 11% frequency improvement across the evaluated blocks.

ABSTRACT. In hybrid-bonded face-to-face 3D ICs, a cross-die dependency arises when a gate output on one die drives logic on the other die. After routing, such dependencies are primarily reflected in HBT usage and routed wirelength. Existing 3D physical-design flows reduce these effects through partitioning, placement, terminal assignment, and routing, but all keep the logic netlist fixed. In this paper, we propose Resyn3D, a post-placement gate-level resynthesis framework with six operators that optimizes cross-die dependencies through logic-level restructuring. For each operator pass, Resyn3D prioritizes roots by a physical cross-die cost and commits edits through guarded acceptance and rollback. Experiments show that Resyn3D further reduces HBT count by 3.12% and routed wirelength by 2.25% on average over the partitioned and placed 3D design.

ABSTRACT. Physical design quality-of-results~(QoR) optimization is hard and expensive. Choices made at one stage can help or hurt later stages. Each evaluation requires a costly EDA run through the full flow. While existing methods still treat optimization as flat parameter tuning or a LLM-based script generation task, we present AgenticPD\footnote{Our code is open-sourced at \url{https://anonymous.4open.science/r/AgenticPD-C74B}.}, a stage-aware agentic framework for physical design QoR optimization. Instead of re-running the full flow after every trial, AgenticPD is organized around the stage boundaries of the physical design flow, where a Judge Agent navigates the search and stage-specialized agents make local decisions within their own stage using stage-local tools. Additionally, the agent harness in AgenticPD provides structured observations, execution history, and agent context management. Together, these components form a stage-aware closed loop: measured post-GR QoR updates the optimization history, the Judge selects a retained design state and the stages to revise, and the Stage Agents execute the resulting downstream branch; post-DR QoR is reserved for final reporting. AgenticPD improves timing while maintaining competitive power and area.

ABSTRACT. Large language model (LLM)-based agents for EDA tuning face a "dual black-box" barrier: the LLM's reasoning is probabilistic, and the tool's internal heuristics are opaque. Retrieval over user manuals describes parameter syntax, not the causal mechanics encoded in C++ cost functions, leaving agents blind to the physical consequences of parameter choices. We present SC-Agent, a self-correcting framework that grounds LLM reasoning in the tool's source code through three components. An AST-driven pipeline traces Tcl parameters into the C++ cost logic that governs their effects. Execution-in-the-Loop verification then tests each extracted rule on miniature benchmarks, admitting only 55 physically confirmed causal rules into a read-only knowledge base. A dual-segment architecture separates these verified tool mechanics from learned design-specific heuristics, and a reflection loop routes any discrepancy to the appropriate segment. On OpenROAD across three designs and two technology nodes, SC-Agent reaches baseline 100-iteration peaks within ~10 iterations (an ≈8× reduction in evaluations) while achieving superior composite QoR. This demonstrates that verified source-code grounding opens the EDA black box for both sample-efficient and high-quality tuning.

ABSTRACT. Analytical placers rely on differentiable objective functions to guide placement, typically combining intermediate surrogate metrics such as half-perimeter wirelength (HPWL) and cell-density penal- ties. However, these placement-stage surrogates remain misaligned with downstream routed and timing quality. Prior work reduces this gap with human-designed terms or learned black-box surro- gates, but the former requires expert retuning and the latter is difficult to explain, debug, or deploy in analytical placement flows. CoEvoP&R addresses these limitations with a large language model (LLM)-based framework that automatically evolves analytical place- ment objectives. At each generation, the prompt combines the re- stricted objective interface, baseline context, and archived prior candidates with routing-related feedback from placement, timing proxy, and routing tools. The LLM proposes readable differentiable objectives, which are embedded and validated in DREAMPlace, evaluated through timing proxy and acutal router, and stored with their feedback to guide later generations. Across eight ChiPBench Nangate45 designs and three seeds, CoEvoP&R reduces post-route routed wirelength and congestion by 16.9% and 36.7%, with gains of 0.70 ns in worst negative slack and a 912 ns reduction in to- tal negative slack magnitude over native DREAMPlace. Across eight ICCAD 2015 Superblue designs, it reduces post-route routed wirelength and congestion by 5.4% and 23.2%. Code is available at https://anonymous.4open.science/r/CoEvoPR-Platform.

ABSTRACT. CAD tools typically apply the same fixed, hand-designed algorithms across circuits with widely different structural and timing characteristics. A common way to specialize these one-size-fits-all flows to a target design is to tune the CAD tool’s hyperparameters. However, hyperparameter tuning can only select among behaviors already implemented by the fixed algorithm, limiting the achievable quality of results while requiring many expensive place-and-route evaluations. We present VPR-Evolve, a multi-agent framework that specializes Versatile Place and Route (VPR), the open-source FPGA pack-place-and-route engine in the Verilog-to-Routing (VTR) flow, by evolving its source code for each design. VPR-Evolve uses LLM agents to propose, implement, and evaluate code-level modifications, while a shared memory records prior outcomes and guides subsequent evolution. Every candidate is evaluated through a complete VPR build and run, directly optimizing a composite score measured as a weighted function of critical-path delay (CPD), routed wirelength (WL), and tool runtime (RT). Across five VTR-9 benchmark circuits, VPR-Evolve improves the composite score by up to 2.7% over stock VPR in VTR-9. Relative to stock VPR, it reduces CPD by up to 9.8%, routed WL by up to 18.1%, and tool RT by up to 79.3%. VPR-Evolve reduces CPD by up to 6.0%, routed WL by up to 2.2%, and tool RT by up to 7.8% compared with a hyperparameter-tuning baseline.

ABSTRACT. Physical design tuning must search a large parameter space under a limited budget of expensive full-flow executions. The task is hard because design decisions are phase-coupled, failures may surface only in later stages, and multiple PPA objectives must be traded off over clean-feasible solutions. We present PILOT-Agent, a phase-aware framework that casts this problem as Monte Carlo Tree Search over configuration prefixes aligned with the ordered stages of the design flow. At each prefix, an LLM Proposal Agent generates context-conditioned next-phase candidates, while every selection stays grounded in measured outcomes: a surrogate screening policy decides which proposals justify execution, and an archive-aware tree policy steers the budget toward frontier-improving rollouts. Under the same budget, PILOT-Agent recovers clean-feasible Pareto fronts more accurately than Bayesian optimization and LLM-agent baselines, cutting hypervolume and coverage error by 31% and 52% over the strongest baseline. These gains carry over to design-level PPA: when optimizing one of power, timing, or area without regressing the others, PILOT-Agent always yields a qualifying design point, within 1% of the best baseline in most cases.

ABSTRACT. Design rule check (DRC) closure remains a major bottleneck in advanced-node physical design. Although detailed routers are rule-aware, residual design rule violations (DRVs) often require manual engineering change order iterations. Automating this process is challenging because repairs must account for complex geometric interactions, preserve circuit connectivity, and avoid introducing new violations. We present EvoDRC, a skill-evolution framework for agentic block-level DRC repair. EvoDRC initializes layer-specific repair skills using knowledge distilled from an unrelated reference design and continuously evolves these skills using traceable repair experience collected from the target design. EvoDRC decomposes the layout into bounded repair regions and assigns an LLM repair agent to each region. Local DRC analysis, connectivity-checking, and impact-preview tools provide feedback on proposed modifications. Repair operations and their resulting DRV changes are stored in a knowledge database and used to evolve the repair skills. Experiments on seven block-level designs from the DAC26 DRC Benchmark show that EvoDRC achieves a 73.5\% overall reduction compared to the reported baseline.

ABSTRACT. In advanced semiconductor manufacturing at the 28 nm node and below, lithographic imaging is significantly affected by three-dimensional thick-mask effects. Therefore, capturing accurate mask-emitted diffraction near fields is essential for high-fidelity imaging and requires rigorous solutions of Maxwell’s equations to capture electromagnetic coupling and vector scattering. However, abrupt permittivity discontinuities at material interfaces in complex 3D masks challenge conventional numerical solvers, leading to spurious oscillations, staircasing artifacts, and severe discretization errors. To address this bottleneck, we propose a high-fidelity lithography simulation framework with MaxIM as its core near-field solver. MaxIM is a lightweight, plug-and-play, interface-modified Finite-Difference Time-Domain (FDTD) solver that introduces an interface modification function to correct local errors at material discontinuities. By exploiting the decoupling between near-field diffraction and lens imaging, we further couple MaxIM with a differentiable lithography-aware lens proxy model. The integrated framework forms an end-to-end, physically interpretable workflow from thick-mask electromagnetic simulation to aerial-image generation while maintaining high computational efficiency. Experiments show that, under DUV and EUV lithography scenarios, the proposed method improves aerial-image prediction accuracy and achieves a substantial RMSE reduction compared with state-of-the-art baselines.

ABSTRACT. As feature sizes continue to shrink, the importance of photoresist simulation continues to grow. Existing studies often focus on individual stages, rather than providing a unified simulation framework. Moreover, recent machine learning-based methods accelerate simulation but are often black-box models. We propose ResistONet, a cascade operator network framework that integrates three key subprocesses, including photoacid generation driven by the 3D intensity distribution during exposure, reaction-diffusion kinetics during post-exposure bake (PEB), and dissolution kinetics during development in chemically amplified resist (CAR) modeling. This design enables end-to-end prediction from the 3D intensity distribution to the final photoresist profile, while also predicting intermediate states throughout the process. In addition, we incorporate physics-based loss terms to ensure that the learned solution remains consistent with the governing physical laws. Experimental evaluations show that ResistONet reduces runtime compared with a rigorous simulator and improves accuracy over prior methods.

ABSTRACT. Optical proximity correction (OPC) must balance lithographic fidelity, mask manufacturability, runtime efficiency, and full-chip scalability. To combine Manhattan manufacturability with neural inference efficiency, recent work has explored directly predicting mask-segment movements. However, prior neural segment prediction relies entirely on the final lithographic error to supervise segment correction indirectly, providing no explicit movement target for each segment. Consequently, its predictions remain insufficiently accurate and still require additional iterative ILT refinement. We propose MAGI-OPC, an ILT-supervised neural Manhattan OPC framework. MAGI-OPC directly learns segment movement labels generated by high-quality ILT, amortizing per-layout iterative optimization into single-pass inference. This enables high lithographic fidelity, efficient inference, and manufacturable Manhattan masks without additional ILT refinement. To provide accurate and manufacturable supervision, we develop an MRC-aware segment-level ILT flow incorporating EPE-aligned curvilinear retargeting, segment fragmentation, and morphology-based regularization. MAGI-OPC further employs a hybrid area--edge representation, where edge tokens serve as correction units and polygon-derived area tokens provide complementary two-dimensional mask-occupancy context. Experimental results show that MAGI-OPC achieves high lithographic fidelity, Manhattan manufacturability, efficient inference, and stable scalability across layout sizes, including full-chip deployment without noticeable stitching artifacts.

ABSTRACT. As integrated circuit features keep shrinking, sub-resolution assist features (SRAFs) are increasingly used to improve wafer pattern quality and expand the lithographic process window. Traditional model-based methods are computationally intensive, whereas recent machine learning approaches often ignore the underlying logic of SRAF generation, resulting in limited accuracy and making practical debugging difficult. To address the above challenges, we propose LRM-SRAF, a large reasoning model–based approach for SRAF generation. It encodes the SRAF generation process derived from EDA tools into a structured generation chain for process-aligned supervised fine-tuning (SFT), leveraging the chain-of-thought (CoT) paradigm to enhance reasoning capability. Furthermore, we apply group relative policy optimization (GRPO)-based reinforcement learning with carefully designed reward functions to further improve SRAF insertion performance. By inferring the SRAF generation process step by step, our model produces a complete stage-wise generation process, which improves interpretability. Experiments demonstrate that our model outperforms state-of-the-art methods across both metal and via layers.

ABSTRACT. Recently, curvilinear masks have demonstrated superior lithographic fidelity and process robustness compared with traditional Manhattan masks. However, most existing curvilinear mask optimization methods are based on pixel-wise optical proximity correction (OPC), known as inverse lithography technology (ILT), which is computationally expensive and poses significant challenges for mask manufacturability. This paper presents DeformOPC, a novel framework for curvilinear mask optimization based on a diffeomorphism deformation algorithm. It formulates mask optimization as a differentiable deformation that transforms the original Manhattan layout into a curvilinear pattern. To maintain manufacturability, the deformation is constrained to preserve diffeomorphism by optimizing a stationary velocity field (SVF). The SVF is differentiably integrated into pattern deformation using the scaling-and-squaring method. Unlike pixel-based OPC, DeformOPC optimizes only the boundary velocity field of the layout pattern, ensuring topological stability while substantially reducing optimization complexity. Extensive experimental results demonstrate that DeformOPC efficiently produces curvilinear masks with enhanced lithographic performance.

ABSTRACT. As technology nodes continue to shrink, discrepancies between wafer patterns and design targets become increasingly pronounced. In addition to distortions introduced by the lithography system, substantial deviations also arise during the etch stage. However, most existing studies mainly compensate lithography-induced errors while largely overlooking etch-related bias, making even highly accurate photoresist patterns sensitive to etch variations. To address this issue, we develop EtchMO, a CUDA-accelerated differentiable etch model for mask optimization. EtchMO predicts the post-etch pattern directly from the photoresist pattern, and its fully differentiable formulation enables seamless integration into existing optical proximity correction (OPC) algorithms for end-to-end etch-bias-aware optimization. In addition, we propose a pixel-wise etch proximity correction (EPC) method as a faster stage-wise alternative. Experimental results show that EtchMO maintains good agreement with an industrial reference etch simulator and, when cascaded with OPC, improves final post-etch pattern fidelity by jointly accounting for lithography and etch effects. Our pixel-wise EPC method also outperforms the conventional EPC workflow implemented in a commercial EDA tool, while providing a more efficient alternative. The code is available at https://anonymous.4open.science/r/EtchMO-3F2D.

ABSTRACT. Transformer-based models have become the backbone of a wide range of tasks, but their intensive computation and data movement incur substantial energy overhead. Analog compute-in-memory (CIM) offers an energy-efficient alternative, yet its inherent hardware non-idealities perturb stored weights and can significantly degrade model performance. Although existing noise-aware training (NAT) methods improve robustness by injecting noise during training, they largely overlook the critical role of attention mechanisms in Transformer inference. To bridge this gap, we analyze how CIM-induced noise reshapes attention in Transformers and identify two key observations: (1) the divergence between clean and noisy attention maps increases substantially in deeper layers, and (2) conventional NAT can remain overconfident even when its attention routes deviate markedly from the clean reference. Motivated by these findings, we propose ABNAT, an attention-based noise-aware training framework that teaches the noisy student to preserve the clean teacher's headwise attention routes rather than merely reproduce answers, without hardware changes or inference overhead; selective variants further reduce training cost. Extensive experiments across vision, language, and multimodal Transformers show that ABNAT consistently improves robustness over corresponding NAT baselines, improving noise-degraded accuracy by up to 11.28% and reducing attention deviation by up to 85.77%.

ABSTRACT. Analog compute-in-memory (CIM) enables energy-efficient neural-network inference, but device variation and read noise can severely degrade low-bit quantized models. Existing CIM-oriented quantization methods mainly minimize ideal quantization error, ignoring the hardware noise floor and thus causing inefficient precision allocation. We propose NANQ, a noise-aware mixed-precision non-uniform quantization framework for analog CIM. NANQ models magnitude-dependent weight noise from measured eFlash-CIM responses and converts the noise profile into an adaptive quantization density, assigning finer resolution to low-noise regions while avoiding ineffective precision in noise-dominated regions. It further allocates layer-wise bit-widths according to both noise sensitivity and the marginal gain of increasing precision. Evaluated through on-chip inference using an eFlash-CIM SoC across CNNs, ViTs, and language models, NANQ generally outperforms uniform and APoT quantization at low precision. At 2-bit weight-magnitude precision, NANQ improves CIFAR-100 accuracy by up to 52.57 percentage points and reduces WikiText-2 perplexity by up to 86.7% over APoT. Mixed-precision NANQ matches or exceeds fixed 4-bit performance using only 3.1–3.4 equivalent bits, reducing the average bit-width by 15.0%–22.5% without retraining.

ABSTRACT. Diffusion models have demonstrated exceptional performance in image generation tasks, yet their deployment is constrained by substantial computational requirements that can be mitigated through compute-in-memory (CIM) architectures. Nevertheless, the inherent noise of CIM systems introduce weight perturbations that compromise generation quality. While prior works studied robustness of other neural networks under hardware noise, the specific vulnerability patterns and mitigation strategies for diffusion models remain unexplored. To address this issue, we present a comprehensive investigation of diffusion model vulnerability under noise conditions measured on real CIM hardware. Our analysis reveals that the sampling process exhibits different sensitivity to weight perturbations, where initial phases are more sensitive than later phases, and increasing sampling stochasticity helps alleviate this sensitivity. Based on these findings, we propose ASSERT, a training-free noise-aware sampling strategy that employs higher stochasticity in early steps and then gradually transitions to deterministic sampling as denoising progresses. Experimental results across various datasets demonstrate that ASSERT yields up to 2.58$\times$ and 5.21$\times$ improvement in Fréchet Inception Distance (FID) under different noise conditions for DDPM and DDIM, respectively.

ABSTRACT. Analog compute-in-memory (CIM) enables energy-efficient neural-network acceleration but remains sensitive to analog noise and costly deterministic data conversion. Conventional analog-to-digital converter (ADC)-based readout directly quantizes noisy column currents, causing inference accuracy to depend strongly on read noise, active-row scaling, and ADC precision. In this paper, we present NOVA-CIM, a noise- and correlation-tolerant stochastic interface for analog CIM. NOVA-CIM replaces multi-bit ADC readout with random-reference 1-bit sensing and reconstructs multiply-accumulate (MAC) results through lightweight counting. By converting column currents into comparison probabilities, this probability-domain readout averages zero-mean dynamic read noise over stochastic samples while reducing dependence on high-resolution ADCs. We provide a unified robustness analysis showing that dynamic read noise is suppressed through temporal averaging and that spatial input-bitstream correlation increases instantaneous current variance rather than introducing first-order MAC bias. MAC-level experiments and end-to-end evaluation on ViT-Base validate the analysis: under read noise, Top-1 accuracy remains 84.48% near the 84.51% bfloat16 (BF16) baseline; under stochastic number generator (SNG) reuse, MAC bias stays near zero while root-mean-square error (RMSE) and stochastic cross-correlation (SCC) grow as predicted.

ABSTRACT. Dynamic low-bit CNN–GNN inference introduces a discontinu- ous failure mode: a small selector perturbation can change rela- tion identity and thereby redirect graph topology, degree, mes- sage basis, memory-bank access, replay traffic, tail service, and visible output. We present ACCORD-IC (Atomic Contracted Cor- rection with Ordered Relation Disclosure for Image Classification), a parameterized heterogeneous-precision FPGA architecture that separates inexpensive relation proposal from architectural autho- rization. A complete FINN-generated Stable Base Engine always emits a legal classification result, while an HLS-authored graph sidecar selectively refines unresolved rank boundaries, generates a contract-consistent witness, and receives payload and execu- tion permission only after independent checking, current-frame replay, range, service, and deadline obligations close. Graph mes- sages remain isolated in guarded shadow state until atomic Com- mit; otherwise the frame retires through the complete base path or a formally bounded lower-degree correction. This proposal– certification–authorization–commit pipeline combines dynamic nonlocal reasoning with deterministic visibility and fail-closed tail behavior. On Ultra96-V2, the optimized implementation achieves 93.0% CIFAR-100 Top-1 and 0.158-ms p99, while reducing p99 EDP by 51.0% relative to a matched full-relation-service implementation.

ABSTRACT. Edge artificial intelligence systems require both efficient inference and reliable prediction under shifts in input data. Existing Bayesian uncertainty methods provide reliable predictions, but they often rely on repeated inference passes or model ensembles, making them inapplicable for real-time safety-critical edge inference. This work proposes SURE-AI, a hardware-aware quantized framework for single-pass uncertainty estimation on multi-pillar SOT-MRAM CIM accelerators. The framework estimates final-layer weight uncertainty using a Kronecker-factored (KFAC) Laplace approximation and obtains predictive uncertainty through linearized predictive inference. Network weights and KFAC factors are quantized to the available conductance states and incorporate process- and voltage-induced conductance variation during estimation. The proposed framework is evaluated on a CIM-based edge inference system with an ARM host processor, where it maintains stable uncertainty calibration under device variation and achieves uncertainty quality comparable to Deep Ensembles, while reducing area-delay-energy product by 14.6x over Monte Carlo Dropout and 9.1x over a 3-member Deep Ensemble on ResNet-56/CIFAR-100.

ABSTRACT. Analog circuit sizing is a critical challenge in analog design automa- tion, as it directly impacts overall performance. Typically, automatic sizing starts from an expert-provided initial solution or relies on a manually narrowed design space. However, this approach is time- consuming and labor-intensive, as the process depends heavily on manual input and experience, limiting optimization efficiency. When jointly optimizing all sizing variables over broad design spaces, existing methods often exhibit slow and unstable conver- gence under strict constraints. To address these limitations, we propose CRAFT, a constraint-guided region-adaptive search frame- work over broad design spaces for high-dimensional analog circuit sizing. The experiments show that CRAFT improves the average fea- sible objective by 1.48×–9.44× over the best-performing baselines, achieves a 1.10×–1.27× runtime speedup over the fastest baselines, and maintains a 100% success rate across all four transistor-level circuit benchmarks.

ABSTRACT. Existing many-objective optimizers usually aim for broad and well-distributed Pareto-front coverage. In analog circuit sizing, strict specifications often restrict feasible designs to narrow trade-off regions. As a result, a fixed SPICE budget may be inefficiently allocated to search directions with little feasible support. We propose AG-MOEA/D, an archive-guided variant of the Multiobjective Evolutionary Algorithm based on Decomposition (MOEA/D), to reuse optimization results accumulated during the search. AG-MOEA/D uses this evidence to coordinate constraint handling, objective-space subproblem allocation, and decision-space offspring generation. It suppresses unsupported search directions, reallocates subproblems toward archive-supported objective regions, and extracts variable-level information to guide Differential Evolution (DE)-based variation. Experiments on five practical analog circuit sizing tasks evaluated by SPICE simulations show that AG-MOEA/D achieves the highest mean normalized hypervolume among representative many-objective baselines. Compared with the strongest baseline, AG-MOEA/D improves normalized hypervolume by 22.97%–103.88% on four circuits. It also obtains a large relative gain on the most tightly constrained case by discovering additional feasible trade-off regions under the same total SPICE budget.

ABSTRACT. Large-scale analog circuit sizing is challenging: each sizing instance under a given specification and Process Design Kit (PDK) induces a high-dimensional, strongly coupled search space under expensive SPICE evaluation, and practical design flows repeatedly retarget the same topology to new specifications and PDKs. Policy-based reinforcement learning (RL) learns reusable policies across related tasks, but vanilla policy-gradient methods struggle at this scale because premature variance collapse weakens exploration. We formulate large-scale sizing as a single-step, task-conditioned policy-learning problem and target high-dimensional same-topology retargeting -- a 149-parameter topology re-optimized across specifications and PDKs. To address the resulting search--transfer tension, GLARE brings Covariance Matrix Adaptation (CMA)-inspired, history-driven per-dimension exploration into a transferable policy, adapting a decoupled mean/variance scaffold with sizing-specific mechanisms: a single-step absolute-parameter formulation, process-grid-bounded variance, and policy-weight reuse across related tasks. From scratch, GLARE improves simulation efficiency by 1.5--1.8$\times$ over the strongest RL baseline while remaining competitive with CMA-ES; under cross-specification and cross-PDK transfer, the reused policy meets the nominal scalarized-reward threshold before any target-task fine-tuning and improves further thereafter.

ABSTRACT. Fair energy comparison across digital, photonic, and in-memory accelerators is undermined by two hidden choices: which on-chip blocks are charged to the compute budget, and which literature values are used for photonic conversion, laser supply, and thermal tuning. We present a framework that makes both choices explicit by decomposing every accelerator into five blocks - compute, electrical-to-optical conversion, optical-to-electrical conversion, memory, and control - each carried as a measured range rather than a single number. Applied to a 28-nanometer-class digital baseline and a ring-based photonic link, block-inclusion choices alone span a twentyfold range in reported digital energy per operation, and under published thermal-tuning powers the photonic path never breaks even against digital unless efficient tuning or non-volatile weights are assumed. Running the framework's audit on our own artifact caught two errors: a photonic circuit-construction bug and a digital measurement bug that had overstated datapath energy by roughly sixty percent.

ABSTRACT. Co-packaged optics (CPO) combines micro-ring modulators and the switching circuits into a single package, shortening the electrical reach between them and lifting both the bandwidth density and the energy efficiency of the link. However, the resonance drifts significantly with the heat generated by the electronic driving circuits. Therefore, finding the operating point that reaches electro-thermal equilibrium, which often differs from the nominal design point, is important for CPO designs. To date, the simulation tools for CPO designs still treat the three physical domains separately: photonic circuit simulators use quasi-static ring models; electronic circuits adopt SPICE-based simulation; and specific solvers are applied to handle thermal physics. Designers have to sweep each domain separately and absorb the coupling with an estimated margin, which is slow and error-prone. To solve this issue, this paper proposes MIBIFI (Multiphysics Integrated Backpropagation and In-loop Feedback Interface), a co-simulation engine that combines a time-domain coupled-mode ring model, gradient coupling to a production SPICE engine, and a finite-volume thermal solver on a common automatic-differentiation graph, linking the performance metrics from device, circuit, to thermal parameters. In the experiment on a CPO design, the validation in each physical domain shows close agreement with the existing tools. Based on the co-simulation results, we apply a gradient-based optimization to jointly tune the drive levels and the ring radius, restoring the PAM4 level uniformity that thermal drift destroys (RLM 0.001 → 0.949) and tripling the worst-case eye (from +0.700 to +2.211 µA). This result demonstrates the importance of considering thermal effects efficiently in CPO designs at early stages.

ABSTRACT. This work introduces a time-encoded analog photonic interposer that enables long-distance, high-fidelity transport of analog signals between spatially separated chiplets. Unlike prior silicon-photonic links limited to digital data, the interposer preserves analog information by converting amplitudes into timing intervals using an analog-to-time converter (ATC), transmitting them over a wavelength-division-multiplexed photonic link, and reconstructing values without ADC/DAC boundaries. Evaluated within a fully analog vision pipeline using an in-pixel computing (IPC) sensor, the system achieves a 2.04× improvement in energy–delay product (EDP) on the 560×560 Visual Wake Words dataset while maintaining 89.87% and 86.15% accuracy on ResNet18 and MobileNetV2.

ABSTRACT. Large language models (LLMs) have demonstrated remarkable capabilities in generating Verilog code from natural language descriptions. However, Verilog code inherently encodes the structural characteristics of hardware circuits. Effectively leveraging these structural characteristics to enhance the functional and syntactic correctness of LLM-based Verilog code generation remains a significant challenge. To address this challenge, we propose VeriGRAG, a novel framework that employs graph neural networks (GNNs) to extract structural graph embeddings from Verilog code. A multimodal retriever then selects the graph embeddings most relevant to the generation task. These graph embeddings are aligned with the code modality through the VeriFormer module to generate structure-aware soft prompts. Our experiments demonstrate that VeriGRAG substantially improves the correctness of Verilog code generation and consistently outperforms competitive baselines on both the VerilogEval and RTLLM benchmarks.

ABSTRACT. Large language models (LLMs) have recently shown promise in Verilog generation, but producing functionally correct RTL directly from natural-language specifications still remains a highly challenging task. Existing approaches improve LLM-based Verilog generation mainly with retrieval-augmented generation (RAG), self-planning, or few-shot prompting. However, these methods only focus on external or generic enhancement rather than strengthening the specification with task-specific constraints. In this work, we propose SpecLens, an automated framework for LLM-based Verilog generation that derives specification-based constraints by analyzing behavioral divergence among multiple candidate implementations, while using the original specification as the only external semantic source during generation. On the VerilogEval v2.0 spec-to-RTL, SpecLens reaches 86.2\% functional pass@1 ratio with o3-mini-medium and 89.4\% pass@1 ratio with o3-mini-high. On RTLLM v1.1 and v2.0, our analysis further shows that SpecLens is more specification-faithful and less prone to benchmark aligned priors. SpecLens achieves 100\% syntactic correctness on VerilogEval v2.0, 86.2\% on RTLLM v1.1, and 88\% on RTLLM v2.0, even without using costly compile-repair loops to revise generated code iteratively.\footnote{Anonymous code release: \url{https://anonymous.4open.science/r/SpecLens-4632/readme.md}.}

ABSTRACT. Automated RTL generation from natural-language specifications has shown considerable promise, yet existing multi-agent approaches still face uneven resource efficiency, limited repair-oriented testbench augmentation, and repeated debugging from scratch. Uniform resource allocation wastes computation on simple tasks while restricting exploration for difficult ones, and a fixed reference-backed testbench may provide a reliable oracle through the RefModule, but its original stimuli may still offer limited diagnostic coverage. To address these limitations, we present MAESTRO, which integrates complexity-aware resource allocation, candidate-conditioned testbench augmentation, and cross-task repair memory into a unified generation-and-repair loop. Before code generation, CARE derives a specification-only complexity tier by majority voting over three independent LLM judgments and selects the preset runtime configuration associated with that tier, including the model tier, candidate count, simulation retries, and edit trials. At the testing stage, AugTB starts from the provided golden testbench, preserves its original oracle and stimuli, adds first-mismatch checkpoints and bounded diagnostic traces, and, once an initial RTL candidate is available, augments the testbench with candidate-conditioned stimuli. Their weakness rationales enter repair alongside reference-confirmed failures. Successful repair strategies are stored by MEMOIR as structured error-signature-to-fix-action pairs and reused across tasks through semantic and symbolic retrieval. On VerilogEval-v2, MAESTRO achieves a Pass@1 of 98.7%, representing a 6.4 percentage-point improvement and a 68.8% lower inference cost compared with MAGE, with ablations showing that each component contributes to the overall gain.

ABSTRACT. LLM agents are rapidly shifting software development toward intent-driven vibe coding, yet their effectiveness drops sharply in high-level synthesis (HLS), where code optimization must jointly consider design structure, directive search, and downstream hardware constraints. Existing HLS optimization approaches, including both heuristic-based methods and recent LLM-assisted pipelines, typically operate at fixed abstraction levels or in weakly coupled stages, limiting their ability to leverage the strong interplay between source code restructuring and directive search outcomes.

Our key insight is that HLS optimization can be reframed from a fixed, hardwired transformation pipeline into a skill-based agentic control problem: an LLM agent equipped with modular, executable optimization skills and a feedback-driven orchestrator can autonomously navigate the coupled space of code restructuring and directive search. This motivates the design of HLSClaw, the first HLS-specific, skill-based agentic harness for holistic HLS optimization. On real-world HLS benchmarks, HLSClaw achieves a 39.12x geometric-mean latency speedup, outperforming the compiler baseline ScaleHLS by 1.98x, and surpassing the commercial coding agents Claude Code and Codex by 1.86x and 1.70x, respectively, while maintaining strong timing robustness.

ABSTRACT. Large language model (LLM) agents optimize the power, performance, and area (PPA) of register-transfer-level (RTL) designs by iterating over edits, synthesis, and PPA analysis, paying a dollar cost for every LLM call. Prior agents report the quality reached without its normalized cost, attribute that quality to an engineered cross-design memory, and hold the reasoning effort of every call fixed. We propose Ares with three corresponding innovations. (1) We introduce a normalized dollar cost per LLM call reported alongside the figure of merit (FoM), enabling fair comparison across effort levels and optimizers. (2) Using this accounting, we find the construction of the long-term memory matters little. An engineered memory brings no dependable gain over a plain concatenation of the same experience. (3) We instead adapt the per-call reasoning effort by escalating to deeper reasoning only once progress at a lower effort stalls, via a patience counter fit on 21 training designs, allocating reasoning where it pays rather than uniformly across all iterations. On three test designs unseen during training, the effort policy lowers the FoM by 23–27% where the best fixed effort reaches 16–23%, at equal normalized cost. Ares closes up to 83% of the gap from an LLM-drafted multiply-accumulate unit to its highly hand-optimized counterpart, and reaches a 25% deeper FoM than state-of-the-art Dr. RTL at 12% of its tokens.

ABSTRACT. Generating implementation-quality RTL with large language models (LLMs) remains difficult because direct generation must resolve microarchitecture while simultaneously producing and debugging low-level code. We present HINT, an executable hardware-intent intermediate representation layer between behavioral specifications or executable oracles and RTL. HINT makes RTL-relevant microarchitecture explicit, supports pre-RTL checking, and supplies explicit RTL-lowering obligations. We evaluate HINT using both a minimal single-agent flow and a full staged workflow. Across seven operator cases, the HINT-mediated route, with no post-synthesis QoR refinement, produces contract-compliant synthesizable RTL on 7/7 cases; Direct C2RTL and C2HLSC apply to five cases and succeed on 5/5 and 1/5, respectively. Under matched Design Compiler synthesis, HINT reduces area by 5.0%–26.2% relative to five manual RTL implementations and by 8.9%–86.1% relative to five accepted Direct C2RTL results. RealBench AES and SDC, together with a Vortex VPU synthesizing to 561.67k μm², further demonstrate specification-driven, protocol-rich, memory-rich, and hierarchical designs. In the controlled operator study, the HINT-mediated route shows better observed convergence and avoids the severe implementation-quality degradation seen in several direct-generation results.

ABSTRACT. Iterative physical-design optimization requires accurate timing feedback at proxy-timer speed. Conventional interconnect models expose an accuracy–efficiency tradeoff: Elmore delay is fast but loses waveform-shape information, whereas higher-order methods improve fidelity at the cost of more expensive distribution or waveform evaluation. We introduce RAPID, a ratio-based analytical proxy that moves Elmore delay toward higher-order timing fidelity through a positive, slew-aware delay-ratio correction. RAPID derives the correction from Wilson–Hilferty asymptotics of a moment-matched Gamma response and extends it to finite input transitions through normalized-slew dilution. The resulting ratio is computed by an Elmore-isomorphic linear-time traversal and used to correct interconnect delay and slew within an NLDM-compatible effective-load flow. On TAU benchmarks, RAPID achieves average R² = 0.9905 and end-to-end report_timing speedups of 9.84× over PrimeTime and 32.70× over OpenSTA. Without ARM retuning, it reaches average R² = 0.9949 and MAE = 0.526 ps on unseen industrial designs at Elmore-level runtime. In the evaluated repair flow, RAPID improves sign-off WNS and TNS by up to 22.28% and 15.44%, respectively.

ABSTRACT. Timing ECO flows repeatedly modify circuit topology, yet GPU-accelerated STA engines built on static sparse layouts commonly rebuild and resynchronize the GPU-visible topology after each edit. Existing GPU-accelerated STA work instead co-designs dynamic representations with application-specific kernels, exposing representation assumptions to consumers and limiting reuse with CSR-based analyses. We present PACT (Private Atomic Committed Topology), a runtime contract that keeps the mutation representation runtime-private behind a representation-independent committed-traversal contract. GPU traversal consumers observe only a committed CSR-compatible view. PACT maintains this view through a contract-preserving localized commit realization that maps objects created by or incident to each edit batch into affected CSR rows, rematerializes each complete affected CSR row, and exposes the new view after synchronization. Dependency-ordered contract composition applies the same contract to explicit netlist/parasitic edits and timing-state edits derived from their committed frontiers. The selected realization achieves average 3.59x the topology-maintenance throughput of a prior dynamic-CSR baseline. In an in-house CPU--GPU STA engine, PACT delivers 2.72x and 2.96x end-to-end speedups over full rebuild under two ECO schedules with identical complete timing outputs. Scalability studies further delimit its measured operating range across host thread counts and update-batch sizes.

ABSTRACT. Accurate static timing analysis (STA) requires clock-control logic and interacting clock constraints to be resolved before timing propagation. Academic timers lack a unified abstraction for such clock semantics and therefore entangle their resolution with downstream timing propagation, causing pessimism and spurious timing checks. We present a fast clock-aware timing propagation framework to address these limitations. The framework comprises three tightly coupled components: (1) a linear-time DFS-based clock-network search that identifies complete, valid clock trees and collects auto-inferred clock-gating (ACG) candidates; (2) a unified clock-gating analyzer that combines Liberty-guided handling of integrated clock-gating (ICG) cells with cofactor-based semantic inference for ACG structures; and (3) a state flow graph that resolves clock-control logic and hierarchical clock constraints into per-pin clock states. Built on this abstraction, tag-based propagation preserves clock/data arrival-time (AT) separation, while CPU- and GPU-based timing engines consume the same resolved clock semantics. On industrial benchmarks, the CPU version achieves up to 3.86x speedup over PrimeTime and 8.13x over OpenSTA. The GPU version further achieves up to 6.75x over PrimeTime and 14.22x over OpenSTA, while both maintain average relative error below 10^{-3}%.

ABSTRACT. Multi-corner static timing analysis (STA) is essential but costly, as full analysis must be repeated across process, voltage, and temperature (PVT) corners throughout timing closure. Existing learning-based predictors leverage netlist topology or cross-corner correlations, but remain limited when only a few anchor corners are analyzed, because endpoint slack depends on both PVT-dependent timing-arc delay shifts and STA propagation constraints. To address this challenge, we propose AnchorGNN, a cross-PVT corner timing prediction framework based on anchor-guided graph learning and STA-aware propagation. First, AnchorGNN uses analyzed anchor corners as timing references and conditions its predictions on the target PVT setting, decoupling the task into PVT-conditioned timing-arc delay estimation and structured timing recovery. Second, a PVT-conditioned adaptive multi-anchor fusion module selects and scales anchor delay references for each timing arc to estimate target-corner timing-arc delays. Finally, a differentiable STA propagation layer recovers endpoint slack from predicted timing-arc delays, avoiding direct endpoint-level regression. Experiments on 9 benchmark designs and 27 PVT corners show that, using only three anchor corners, AnchorGNN reduces normalized slack prediction error by 77.6% over TOTAL, a representative learning-based cross-corner timing prediction method, and achieves an average 96.1× speedup for single-corner inference.

ABSTRACT. Physical obstacles fundamentally complicate timing-driven buffering: although wires may traverse macros on upper metal layers, buffers cannot be placed inside them, so long over-the-block (OTB) segments can become electrically unbufferable and induce slew or timing failures. This paper presents an obstacle-aware framework that couples topology reconstruction with buffer insertion. Starting from a legal routing tree, we first perform pre-buffering and static timing analysis (STA) to extract sink criticalities and stage-level electrical states. We then construct an OTB-feasible reference graph that combines obstacle-avoiding routes with only those OTB crossings whose unbufferable spans satisfy a reach bound derived from slew feasibility. Guided by this graph, a timing-aware shallow-light reconstruction bounds root-to-sink path stretch with respect to obstacle-aware, buffer-feasible distances while prioritizing critical sinks for worst negative slack improvement. To further refine the solution efficiently, we introduce buffer-isolated local windows and LUT-based local rebuffering to evaluate legality-preserving topology moves. The proposed formulation embeds obstacle awareness directly into topology reconstruction, avoids hazardous OTB crossings by construction, and provides provable feasible-shallowness guarantees.

ABSTRACT. Routability prediction enables rapid evaluation of placement quality without performing routing, offering effective feedback for routability-driven placement optimization. Recent machine learning approaches have achieved efficient routability prediction through data-driven learning. However, their prediction performance highly depends on the capability of input representations to capture essential circuit information. To address the semantic incompleteness of existing circuit representations in simultaneously preserving logical topology, physical placement, and routing-resource information, this paper proposes HGRP, a heterogeneous graph neural network for routability prediction. The proposed method models cells, nets, and routing grids as different types of nodes and explicitly represents topological connectivity, spatial mapping, and grid adjacency, thereby constructing a heterogeneous graph representation that preserves multi-level circuit semantics. Based on this representation, a heterogeneous message passing mechanism is developed to enable information interaction and feature fusion among different types of nodes, effectively learning the complex correlations between circuit structures and routing behaviors. Experimental results on the CircuitNet dataset validate the effectiveness of the proposed model.

ABSTRACT. The growing complexity of modern chips poses significant challenges to hardware verification. In recent years, coverage-guided fuzzing has emerged as a promising approach for improving verification efficiency. However, existing hardware fuzzers still struggle to achieve high coverage and expose corner-case bugs, as they predominantly rely on heuristic strategies with limited ability to reason about the internal logic and semantic behavior of the design under test (DUT). In this work, we propose ChipFuzzer, a hardware fuzzing framework that leverages the semantic reasoning capabilities of large language models (LLMs) to improve fuzzing effectiveness. ChipFuzzer adopts a dual-stage workflow comprising a Coverage-Guided stage and a Bug-Guided stage. In the Coverage-Guided stage, ChipFuzzer employs control-flow similarity and discrepancy analysis to guide LLM-driven testcase generation, thereby improving coverage. In the Bug-Guided stage, ChipFuzzer leverages historical bug data to identify bug-prone code regions and prioritize testcase generation for those regions, thus enhancing bug discovery efficiency. Experimental results on three open-source CPU designs show that ChipFuzzer improves average condition coverage by 5.8 percentage points and bug detection rate by 21.1 percentage points over the strongest baseline.

ABSTRACT. The AMD Versal adaptive System-on-Chip (SoC) combines programmable logic with an Adaptive Intelligence Engine (AIE) array to accelerate AI inference and signal-processing workloads. The AIE has been adopted in safety- and mission-critical applications spanning automotive, space, and particle-physics triggering, yet its reliability against transient faults remains understudied. Existing approaches are restricted to costly radiation testing, while the closed AIE microarchitecture rules out register-transfer-level fault injection. We present CHAIDO, the first open-source simulation-based fault injection tool for the first-generation AIE (AIE-1), enabling fine-grained per-resource, per-workload reliability analysis required for fault tolerant design decisions. Modeling each fault as a Single Event Upset (SEU) in storage, we characterize the AIE-1 across five diverse workloads. The leading per-fault silent-data-corruption contributor is kernel-dependent (27–54%), while control-flow registers dominate detected unrecoverable errors on four of five workloads (21–34%), motivating hardware protection of these registers in future AIE generations. As a case study, we prioritize ECC-protected data-memory bank mapping which cuts the overall AVF by up to 93% on the matrix-multiplication kernels

ABSTRACT. Resistive Random Access Memory (RRAM)-based Compute-in-Memory (CIM) accelerators are promising for edge Spiking Neural Network (SNN) deployment, yet their practical viability is severely undermined by device non-idealities, including stochastic write noise and stuck-at faults (SAFs). Existing mitigation strategies---such as iterative weight reprogramming or algorithmic workarounds like Low-Rank Adaptation (LoRA)---incur prohibitive RRAM write costs or introduce additional multiply-accumulate (MAC) operations, fundamentally contradicting the ultra-low-power philosophy of edge CIM. In this paper, we propose \textbf{Neural Tuning via Intrinsic Plasticity (NT-IP)}, a novel hardware--software co-design framework that shifts the fault compensation burden from vulnerable synaptic weights to robust neuron dynamics. Rather than modifying frozen RRAM-mapped weights, NT-IP exclusively optimizes the intrinsic parameters of the Leaky Integrate-and-Fire (LIF) neuron---the membrane decay factor ($d$), firing threshold ($\theta$), and reset voltage ($v_r$)---to adaptively recover model accuracy. To physically realize this capability on-chip, we design a lightweight tunable digital LIF neuron architecture featuring a Shift-and-Add leaky module and SRAM-backed parameter registers, enabling precise runtime configuration with negligible area and energy overhead. Extensive experiments on DVSGesture, NMNIST, and BrailleLetter demonstrate that NT-IP recovers accuracy to the original fault-free model under severe mixed faults (e.g., 2.0\% SAF rate + 2.0\,$\mu$S noise), while achieving zero weight redeployment, zero additional synaptic MAC operations, and significantly lower parameter storage and inference energy compared to LoRA.

ABSTRACT. A large number of industrial chips are developed under stringent area and cost constraints, where even minimal nonvolatile memory, such as one-time programmable ROM, cannot be embedded. Consequently, conventional on-chip identification methods, such as physically unclonable functions or embedded ID storage, are impractical, leaving many real-world designs without traceability. This paper proposes TRAIT, a design-agnostic, test-based chip identification framework that exploits chip-specific performance trajectories to enable robust traceability throughout a chip's lifetime. TRAIT models the characteristic degradation trajectory of each chip using data collected during standard initial burn-in tests. The framework jointly infers chip identity and degradation state without requiring extra circuitry or modifications to the manufacturing process. Experimental evaluation on an industrial dataset comprising 21,977 chips demonstrates a Top-1 identification accuracy of 99.99\%, even at the highest observed degradation state. Compared with conventional static fingerprinting methods, TRAIT reduces wafer-level misidentification from 118 chips to one. TRAIT provides a practical, scalable, and manufacturing-compatible solution for chip traceability, particularly in designs where additional area, memory, or design-for-identification logic is prohibitively constrained.

ABSTRACT. As SoC verification cycles accelerate, timely analysis of the root cause of test failures becomes increasingly critical. Software-driven tests are favored for their reusability, but their system-level scale and cross-layer software-hardware interactions make root cause analysis particularly challenging. Existing analysis methods loosely combines the strengths of symbolic algorithms and LLMs, but are bounded by the symbolic rigidness and information loss in derived signal excerpts, preventing them from scaling to SoC. We propose WaveAce, an LLM-driven root cause analysis framework powered by direct waveform inspection. It features Chaser, an iterative workflow that cross-validates code and waveform to converge on the causal chain, and Tracer, a waveform textualization tool that uses the software call tree as its backbone for comprehensive observation. We evaluate WaveAce on both the established benchmark UVLLM and the real-world OpenTitan SoC. On the established benchmark, WaveAce substantially improves first-iteration localization performance over the baseline, raising the average F1 from 52.4% to 69.7%. On OpenTitan, WaveAce raises the pass@1 from 26.1% to 73.9%, compared to the baseline of general purpose coding agents.

ABSTRACT. SRAM peripheral circuits are shared across many bitcells. They are traditionally sized through single-cell or worst-case corner analysis, never searched jointly with the bitcell under a realistic array-level yield constraint. This is not merely a matter of cost: naive array-level yield evaluation requires variation parameters that scale with array size, reaching tens of thousands of dimensions for a modest macro, where neither brute-force Monte Carlo nor learned surrogates remain tractable. We introduce a physically derived equivalent-circuit reduction, validated against full-array simulation (delay error <0.22%, power error <1.68%), that confines process variation to the accessed read/write path---one row, one column, and the peripheral circuits---reducing the relevant dimensionality from quadratic in array size to linear in sub-array dimensions. This makes it possible, for the first time, to train a yield estimator offline and query it online, jointly searching bitcell, peripheral, and array architecture under a 90% yield constraint. Across eight optimization algorithms, the best-performing solution cuts read delay by 47.8% and area by 26.8% while meeting the yield target, suggesting conventional peripheral designs carry recoverable margin.The framework is publicly available at SramOpt.