Conference Room 3

Technical Session

Session 1D (Jan 25 13:30-15:30) The Inference Engine: From Speculative Decoding to Compiler-Driven Hardware Generation
Session 2D (Jan 25 15:50-17:50) On-Chip Networks and Memory Hierarchies
Session 3D (Jan 26 11:00-12:00) Beyond Conventional Synthesis: Superconducting Logic Mapping and Verified Microarchitecture Replacement
Session 4D (Jan 26 13:00-15:00) Breaking the Memory Wall: Emerging Memory Architectures for LLM KV Caches and Long-Context Inference
Session 5D (Jan 26 15:20-17:20) Silicon Meets Action: Accelerators for Embodied, Visual, and Edge Intelligence
Session 7D (Jan 27 10:20-12:20) Memory-Centric Computing and Efficient LLM Inference
Session 8D (Jan 27 13:20-15:20) Design Space Exploration and Co-Design for Emerging Architectures
Session 9D (Jan 27 15:40-17:40) Advanced Logic Synthesis and Optimization
Session 10D (Jan 28 10:20-12:20) Every Bit Counts: Quantization and Low-Precision Arithmetic for Neural Inference
Session 11D (Jan 28 13:20-15:20) Parallel, Physical, and 3D-Aware Logic Synthesis
Session 12D (Jan 28 15:40-17:40) LLM and Agentic Methods for RTL and HLS Generation