ASP-DAC 2027: 32ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE

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Abouzeid, Fady	ALTO: Joint Track-Height and Placement Optimization for Non-Integer Mixed-Cell-Height Designs
Adhi, Boma	Enabling Efficient Quantized LLM Inference on Floating-Point CGRAs via Lightweight Integer Extensions
Afarin, Mahbod	GenMLIR: An MLIR Compiler for Dynamic Programming Workloads on Tier-Aware 3D-DRAM PIM
Ahmad, Afzal	HLSClaw: Bringing Vibe Coding to High-Level Synthesis through Skill-Based Agentic Harness
Ai, Zhilin	ScaleLUT: A Fully-Parallel Configurable LUT-Based Accelerator for Real-Time Multi-Scale Super-Resolution
Akbulut, Mehmet Emre	MemFLoRA: Memory-Floor LoRA for CNN Adaptation at the Edge
Al Faruque, Mohammad	EdgeDAE: Acceleration of Diffusion Action Experts for Real-Time Physical AI with Tiny VLAs on Edge FPGA-GPU Systems
An, Borui	APRQ: Adaptive Prediction-Driven Residual Quantization Accelerator for Diffusion Transformers
An, Lihua	Hit-SME: A High-throughput Hybrid SNN-based MLP Engine for Neural Volume Rendering A Two Stage Learning-Based Thermal-Aware Framework for 3D Fixed-Outline Soft-Module Floorplanning across Chip Sizes
An, Wenbo	GLARE: Generalizable Large-scale Analog Sizing via Reinforcement Learning with Covariance-Guided Exploration
Ananthanarayanan, Gayathri	CRANE: Criticality-Aware Concurrent Neural Inference on Heterogeneous Edge Platforms
Andriamisaina, Caaliph	GRACE: GRAph-based power Consumption Estimator with Parallel Switching Activity Propagation
Ang, James	FUSE: Five-Block MVM Energy Comparison
Anghel, Lorena	SURE-AI: Single-pass Uncertainty Estimation for Reliable Edge AI Accelerators
Ansaloni, Giovanni	Compiler-driven Optimizations for Efficient Host and Near-DRAM Co-Execution CCD-KV: Exploiting High-Density 3D Charge-Coupled Device Memory for Efficient On-Device LLM KV Caches From Compiler to Silicon: A Co-Design Approach to High-Performance CGRAs
Antonio, Ryan	CABLE: A Cached Bidirectional and Multi-lane Item Memory\\for Efficient Hyperdimensional Computing
Ao, Ruichu	MX-like Tensor Core for LLM Inference with NPU Integration via Hardware-Software Co-Design Exploration
Aparicio-Téllez, Raúl	Power and EM Side-Channel Leakage Mitigation in Oscillator-Based PUFs via Sampling Techniques
Arora, Aman	VPR-Evolve: Multi-Agent-Driven Algorithm Evolution for FPGA Place and Route
Atienza, David	Compiler-driven Optimizations for Efficient Host and Near-DRAM Co-Execution CCD-KV: Exploiting High-Density 3D Charge-Coupled Device Memory for Efficient On-Device LLM KV Caches From Compiler to Silicon: A Co-Design Approach to High-Performance CGRAs
Aviles, Robert	qLevelPlace: A Level-Based Placement Framework for RSFQ Circuits
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Baek, Sanghoon	Multi-Output-Guided Transistor Network Synthesis and Layout for Sequential Cells
Bai, Chen	FADiff: Fusion-Aware Differentiable Optimization for DNN Scheduling on Tensor Accelerators UACC: A Chiplet-Based Auxiliary Cache for Cost-Effective Performance Scaling in Multicore Processors
Banerjee, Ansuman	Decompose Transform Refine Verify: A new approach for scalable formal verification
Bao, Yungang	ChronosDSE: Stability-Aware Design Space Exploration for GPGPUs MinVNS: Minimal Virtual Network Separation for Deadlock Avoidance in Modular Network-on-Chip Towards Leveraging the Software Ecosystem to Facilitate Hardware Verification
Bao, Zhixuan	CABAgent: A Cross-Stage Agentic Framework for Generating PDK-Compatible and Layout-Verified Analog Circuit Benchmarks
Barker, Kevin	Memory-Aware Design-Space Exploration for Multi-Threaded HLS Accelerators
Becker, Juergen	CHAIDO: Open-Source Simulation-Based Fault Injection for the AMD Versal AI Engine
Beerel, Peter	qLevelPlace: A Level-Based Placement Framework for RSFQ Circuits
Bel, Oceane	Memory-Aware Design-Space Exploration for Multi-Threaded HLS Accelerators FUSE: Five-Block MVM Energy Comparison
Bieman, Rob	SHARD: Sub-Transformer Harnessing for Adaptive Resource-Aware Deployment
Bing, Wen	SpecLens: LLM-Based Verilog Generation with Specification-Derived Constraints via Behavioral Divergence
Bishnoi, Rajendra	OMNI-DC: One-shot Multi-input Neural-Inference-Based Data Converter for Analog Computation-in-Memory
Biswas, Dwaipayan	Compiler-driven Optimizations for Efficient Host and Near-DRAM Co-Execution CCD-KV: Exploiting High-Density 3D Charge-Coupled Device Memory for Efficient On-Device LLM KV Caches
Biyani, Yashvardhan	OMNI-DC: One-shot Multi-input Neural-Inference-Based Data Converter for Analog Computation-in-Memory
Bradley, Dave	An In-situ Self Clock-Gated 7474 Style Scan-Mux-D Low Power Flip-Flop
Brempong Jnr, Osei W	ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Exploration
Brichart, Clément	GRACE: GRAph-based power Consumption Estimator with Parallel Switching Activity Propagation
Bringmann, Oliver	Compiler-driven Generation of Domain-Specific AI Hardware Accelerators for Edge Devices Hardware-Retargetable Grammar-Based NAS from Declarative Device Specifications
C
Cai, Hao	APRQ: Adaptive Prediction-Driven Residual Quantization Accelerator for Diffusion Transformers TriM: Efficient MoE Inference on Edge CPU-GPU Systems via Fused Quantization and Sensitivity-Guided Scheduling
Cai, Junfeng	PARFuzzer: Path-Aware RTL Fuzzing with Controlled BTB Conflict Injection for Branch-Predictor Security Validation
Cai, Linlin	Cross-Family Graph Learning for Sparse Aging-Aware Timing Characterization of Standard-Cell Libraries
Cai, Siyang	When Fuzzing Meets Understanding: LLM-Driven Semantic Test Generation for RTL Verification
Cai, Xuefeng	TriM: Efficient MoE Inference on Edge CPU-GPU Systems via Fused Quantization and Sensitivity-Guided Scheduling
Caliskan, Arda	Fanout-Multiplicity-Aware Technology Mapping for Multi-Output Superconducting Logic
Cao, Jiacheng	Efficient End-to-End Hyperprior-Based Learned Image Compression on Edge GPUs via Thread-Level Parallel Entropy Coding
Cao, Peng	PDN-Aware Graph Transformer-based Dynamic IR Drop Prediction with Criticality-Guided Subgraph Construction XCTS: Cross-Tier-Aware Differentiable Clock Tree Synthesis for 3D Integrated Circuits
Cao, Xin	TriM: Efficient MoE Inference on Edge CPU-GPU Systems via Fused Quantization and Sensitivity-Guided Scheduling
Cao, Yu	SiliDiff: Post-Silicon Thermal and Power Reconstruction from Sparse Sensing with a Cascaded Conditional Diffusion Model
Cao, Zhengyang	Declared Event Semantics: Cross-Layer Memory-Hierarchy Co-Design for Latency-Critical Systems
Celma, Santiago	Power and EM Side-Channel Leakage Mitigation in Oscillator-Based PUFs via Sampling Techniques
Chae, Youngjin	Clock Distribution Network with Backside Clock Mesh in BSPDN Architecture
Chakrabarty, Krishnendu	Chiplet Assembly and Pre-Bond Qualification Planning for Heterogeneous Integrated Systems
Chakraborty, Subhradip	NVM-in-Cache: Repurposing Commodity 6T SRAM Cache into NVM Analog Processing-in-Memory Engine using a Novel Compute-on-Powerline Scheme A Time-Encoded Analog Photonic Interposer for Energy-Efficient Integration of Analog Vision Sensors and Analog Accelerators
Chang, Che-Ming	Encoding Symmetries into Operator Learning: Towards Accurate Multi-Physics Simulation in Advanced Packaging
Chang, Haodong	AccTTS: Characterizing and Optimizing Workload Dynamics in Test-Time Scaling
Chang, Haoju	Network Flow Guided Routing and Force Directed Offset Via Placement for Advanced Chiplet Interconnect
Chang, Ik-Joon	AlignQuant: Alignment First Two-Stage Integer Microscaling Format for Systolic Native LLM Inference
Chang, Jiaming	CertIR: Certified Static IR-Drop Estimation with Physics-Anchored Neural Correction
Chang, Kaiyan	When Fuzzing Meets Understanding: LLM-Driven Semantic Test Generation for RTL Verification
Chang, Rui	DFAC: Dataflow-Aided Intra-cluster Coalescer for AI Accelerators
Chang, Shih-Chieh	A Dual-Branch GAT-MLP Framework for Efficient Bump-Level Dynamic IR Drop Prediction in Flip-Chip Packages
Chang, Yao-Wen	Learning-Guided Adaptive Cell-Wise Optimization for Mixed-Size Global Placement
Chang, Yao-Wen	Encoding Symmetries into Operator Learning: Towards Accurate Multi-Physics Simulation in Advanced Packaging Efficient Concurrent Die-to-Die Routing with Teardrop and Offset-Via Awareness A Consensus-Optimization Framework for Progressive Clearance-Aware PCB Legalization with Irregular Components
Chang, Yong-Fong	A Dual-Branch GAT-MLP Framework for Efficient Bump-Level Dynamic IR Drop Prediction in Flip-Chip Packages
Chao, Huize	RASP-LLM: Radiation-Aware Design-Space Exploration of Precision and Selective Protection for On-Orbit LLM Inference
Chen, Cailian	MAESTRO: Memo-Augmented Multi-Agent Engine for Self-Testing RTL Code Generation with Resource Orchestration
Chen, Chen	Inverter Redistribution through Self-Dual and Self-Anti-Dual Function Transformation
Chen, Chih Yen	Multi-Agent LLM Serving with SSD-Based KV-Cache Offloading
Chen, Deming	Naviq: An Open-Source System-on-Chip Simulator for Rapid Prototyping, Verification, and Design Space Exploration PFHE: Partial Fully Homomorphic Encryption on CNN Inference
Chen, Gengjie	Logic Resynthesis for Cross-Die Dependencies in Hybrid Bonded 3D ICs
Chen, Hung-Ming	Learning-Guided Adaptive Cell-Wise Optimization for Mixed-Size Global Placement Network Flow Guided Routing and Force Directed Offset Via Placement for Advanced Chiplet Interconnect
Chen, Jia	PSD-CIM:A Computing-In-Memory Attention Accelerator with Predictor-Free Sparsity search and Distribution Shaping
Chen, Jian-Feng	Physics-Informed Generative Model Based Aging Library Characterization
Chen, Jiangwen	Taming Irregular Sparsity with a Regular Systolic Array for Efficient DNN Training
Chen, Jianli	CertIR: Certified Static IR-Drop Estimation with Physics-Anchored Neural Correction
Chen, Jiansheng	DISSECT: Cross-Family RTL Trojan Localization by Auditing Structural–Functional Disagreement
Chen, Jiashuo	3D-VASE: Volumetric-Aware Scalable and Efficient Multi-Layer Design Synthesis for 3D-Printed Microfluidics
Chen, Junda	KV3D: KV Cache-Centric Monolithic 3D-Stackable DRAM-Based Accelerator for LLM Serving
Chen, Ke	MATE: Model-Assisted Trade-off Exploration for Quality-Aware Approximate Matrix Computing
Chen, Kehao	A HeteroGNN-Based Hierarchical Co-Optimization Framework for Floorplanning and Routing in Advanced Packaging
Chen, Lei	DeepResub: Towards Learned Logic Optimization Operators PP2Tree: Learning-Guided Frontier Partitioning for Scalable Parallel Logic Synthesis
Chen, Muyang	CONTOUR: Continuous Topology Search for System-Level RFICs via Bi-Level Optimization and Neural-Analytical Co-Modeling
Chen, Qin	From DRAM Architecture to Protocol State: A Resource-Grounded Executable Semantics for LPDDR5
Chen, Ruogu	CoEvoP&R: Co-Evolving Placement Objectives with Routing Feedback via Large Language Models
Chen, Shao-Hsiang	Efficient Concurrent Die-to-Die Routing with Teardrop and Offset-Via Awareness
Chen, Shuangliang	A Waferscale Memory Architecture for Efficient LLM Inference
Chen, Shuo-Han	Prefix-Branch Software Co-Design for Random Forest Acceleration on Embedded Hybrid TCAMs
Chen, Silin	ResistONet: Cascade Operator Network for Photoresist Simulation Chain of SRAF Generation: A Large Reasoning Model for Sub-resolution Assist Features Curvilinear OPC via Diffeomorphic Deformation EtchMO: A Differentiable Etch Model for Mask Optimization
Chen, Song	VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts
Chen, Tianlong	T3R: Training-Free Two-Stage Token Refinement Towards Efficient and Robust VLA Models
Chen, Ting-Wei	Spec2Plan: An LLM-Powered Framework for Comprehensive Verification Plan Generation
Chen, Tinghuan	GAS: GPU Accelerated Schema Aware Exact Subcircuit Matching for Large-Scale Circuits
Chen, Tung-Chieh	Placement Guidance Generation via Timing-Aware Hypergraph Partitioning and Multi-Criteria Cluster Selection
Chen, Wangyong	Cross-Family Graph Learning for Sparse Aging-Aware Timing Characterization of Standard-Cell Libraries
Chen, Wei-Ting	MIBIFI: Differentiable Electronic–Photonic–Thermal Co-Simulation for Co-Packaged Optics Designs
Chen, Weiyu	CktHVR: A Convergence-Aware GNN-VLM Hypothesize-Verify-Refine Framework for Analog Circuit Topology Rectification
Chen, Weiyu	Archive-Guided MOEA/D for Constrained Many-Objective Analog Circuit Sizing
Chen, Xiao	Towards Leveraging the Software Ecosystem to Facilitate Hardware Verification
Chen, Xinyang	APRQ: Adaptive Prediction-Driven Residual Quantization Accelerator for Diffusion Transformers
Chen, Xinyang	TriM: Efficient MoE Inference on Edge CPU-GPU Systems via Fused Quantization and Sensitivity-Guided Scheduling
Chen, Xizi	Taming Irregular Sparsity with a Regular Systolic Array for Efficient DNN Training
Chen, Xu	A XNOR-SRAM-Based Computing-in-Memory Macro for Memory-Augmented Neural Networks RACE-FFN: Runtime-Adaptive Co-Execution in a Heterogeneous SA-CIM Architecture for Efficient MoE-FFN Acceleration
Chen, Xuanqi	MoL-PAM: Joint P/G TSV Planning and Macro Refinement for Memory-on-Logic 3D ICs via a Benders-Type Decomposition Heuristic
Chen, Xuming	NVM-in-Cache: Repurposing Commodity 6T SRAM Cache into NVM Analog Processing-in-Memory Engine using a Novel Compute-on-Powerline Scheme A Time-Encoded Analog Photonic Interposer for Energy-Efficient Integration of Analog Vision Sensors and Analog Accelerators
Chen, Yean-Ru	A Resource-Efficient Quantum Circuit for Fixed-Point Logarithm Operations with Analytical Error Bounds
Chen, Yi-Hang	Spec2Plan: An LLM-Powered Framework for Comprehensive Verification Plan Generation
Chen, Yijun	Timing-Aware Routing and Heterogeneous TDM Assignment for Multi-Level FPGA-Based Emulation Systems
Chen, Yijun	CCPart: Timing-Aware Multi-Level Partitioning for Multi-FPGA Systems with Incremental Timing Analysis
Chen, Yiran	SCALE: Self-Supervised Constraint-Aware Layout Generation for Local P&R DRV Fixing at Advanced Nodes
Chen, Yizhe	InfoCIM: An Information-Theoretic Framework for Modeling and Design of Noise-Limited Analog CIM STRIDE: Sparse Thermal Reconstruction-Informed Differential Encoding for Thermally Stable 3D-Integrated Analog CIM ABNAT: Attention-Based Noise-Aware Training for Robust Transformers on Analog Compute-in-Memory Systems NANQ: Noise-Aware Mixed-Precision Non-Uniform Quantization for Neural Networks on Analog Compute-in-Memory ASSERT: Adaptive Stochastic Sampling for Robust Diffusion Models on Analog Compute-in-Memory Hardware
Chen, Yu-Chung	A Resource-Efficient Quantum Circuit for Fixed-Point Logarithm Operations with Analytical Error Bounds
Chen, Yun-Chih	Multi-Agent LLM Serving with SSD-Based KV-Cache Offloading
Chen, Yung-Chih	A Dual-Branch GAT-MLP Framework for Efficient Bump-Level Dynamic IR Drop Prediction in Flip-Chip Packages
Chen, Yuxi	Weight-Stationary Fault Recovery via Neuron Tuning in RRAM-Based CIM Neuromorphic Accelerators
Chen, Zhenghao	Opening the Black Box: A Self-Correcting LLM Agent for EDA Toolchains Based on Source-Code Analysis
Chen, Zhengrui	A DTCO-Oriented Early Digital Bring-Up Framework under Incomplete PDK and Standard-Cell Assets
Chen, Zhenyang	T3R: Training-Free Two-Stage Token Refinement Towards Efficient and Robust VLA Models
Chen, Zhibin	Cross-Family Graph Learning for Sparse Aging-Aware Timing Characterization of Standard-Cell Libraries
Chen, Zhiheng	EdgeDAE: Acceleration of Diffusion Action Experts for Real-Time Physical AI with Tiny VLAs on Edge FPGA-GPU Systems
Chen, Zhuoyi	CRAFT: Constraint-Guided Region-Adaptive Search over Broad Design Spaces for High-Dimensional Analog Circuit Sizing
Chen, Zihao	MinVNS: Minimal Virtual Network Separation for Deadlock Avoidance in Modular Network-on-Chip
Cheng, Chung-Kuan	Multi-Output-Guided Transistor Network Synthesis and Layout for Sequential Cells
Cheng, Hsien-Han Cheng	Physics-Informed Generative Model Based Aging Library Characterization
Cheng, Quan	CircuitsDNA: Discovering Unconventional Multi-Accuracy Arithmetic Circuits via Evolutionary Synthesis
Cheng, Tairan	HINT: Toward an Executable Hardware-Intent Intermediate Representation Layer for LLM-Driven RTL Generation
Cheng, Yuanqing	RAPID: An Efficient and Accurate Ratio-Based Analytical Proxy for Interconnect Delay
Cheng, Zijin	AgenticPD: A Stage-Aware Agentic Framework for Closed-Loop Physical Design Optimization
Chennagouni, Nishanth	Multi-Feature Demographic Decoupling via LPC Cross-Synthesis for Privacy-Preserving Audio Anonymization
Cherukuri, Nikhil Kumar	SiliDiff: Post-Silicon Thermal and Power Reconstruction from Sparse Sensing with a Cascaded Conditional Diffusion Model
Chhabria, Vidya	VPR-Evolve: Multi-Agent-Driven Algorithm Evolution for FPGA Place and Route EvoDRC: A Self-Evolving Agentic Framework for Automated DRC Violation Repair
Chi, Taiyun	CONTOUR: Continuous Topology Search for System-Level RFICs via Bi-Level Optimization and Neural-Analytical Co-Modeling
Chiang, Cheng-Yu	Learning-Guided Adaptive Cell-Wise Optimization for Mixed-Size Global Placement
Chiang, Chun-Yao	Gradient-Guided Thermal-Aware Timing Robustness Optimization Under Temperature Inversion
Chiu, Po-Chien	Network Flow Guided Routing and Force Directed Offset Via Placement for Advanced Chiplet Interconnect
Cho, Hyunjung	SpectraPlace2.5D: Thermal-aware Chiplet Placement via Topology-guided MILP and Spectral Thermal Modeling
Choi, Ilhuan	IMPACT: IoT SNN Inference with a Metadata-Guided Pulse-Width Control Architecture for Conductance-Time Weight Representation in RRAM
Choi, Jeonghyun	Phase-Aware Monte Carlo Tree Search with LLM-Guided Proposal for Multi-Objective Physical Design Tuning
Choi, Seungkyu	AlignQuant: Alignment First Two-Stage Integer Microscaling Format for Systolic Native LLM Inference
Choi, Woo-Seok	IMPACT: IoT SNN Inference with a Metadata-Guided Pulse-Width Control Architecture for Conductance-Time Weight Representation in RRAM
Chong, Yue Jiet	A System-Level Typed-Graph Environment for Traceable Cycle-Level Co-Design of Heterogeneous AI Accelerators
Chou, Yi	Structure-Preserving Density Modeling for Electrostatics-Based Analytical Placement
Cong, Guangwei	Observability-Aware Runtime Reliability for MZI-Based Optical Neural Networks
Constantinescu, Denisa-Andreea	From Compiler to Silicon: A Co-Design Approach to High-Performance CGRAs
Cui, Yijun	A Lightweight Microring-Resonator PUF Design for Silicon Photonics Transceivers
Cui, Yucheng	CAS: A Ferroelectric Compute-in-Memory Annealer for Sparse Combinatorial Optimization Problems
Cuyckens, Stef	MX-like Tensor Core for LLM Inference with NPU Integration via Hardware-Software Co-Design Exploration ARES: Adaptive Reasoning-Effort Steering for PPA- and Cost-Aware RTL Optimization with LLM Agents
D
Dai, Bill	PFHE: Partial Fully Homomorphic Encryption on CNN Inference
Dai, Chenyang	AX-AGENT: Contract-Driven Closed-Loop Framework for Error-Bounded PPA-Aware Approximate RTL Generation
Dai, Guohao	DeferKV: Long-Context LLM Attention Acceleration with Per-Token Scale Folding and Bank-Local Softmax on PIM CRISP: Paged Sparse Attention on DRAM-PIM with Row-Band-Aware KV Allocation and Frame-Derived Addressing Cross-Bank ECC Strategy for LLM-Oriented Hybrid-Bonded 3D DRAM Architecture MTPMoE: Exploiting Activation Skewness in Single-GPU MoE Multi-Token Prediction via Parallel Dense-Sparse Computing PowerPilot: Preserving Verified Progress in LLM-Based Power-Intent ECO Repair
Dai, Liangtao	SLED-IFV: Solver-Validated LLM-Guided Decomposition for Scalable Hardware Information-Flow Verification
Dai, Yutao	CCPart: Timing-Aware Multi-Level Partitioning for Multi-FPGA Systems with Incremental Timing Analysis
Dasari, Sai Teja	CRANE: Criticality-Aware Concurrent Neural Inference on Heterogeneous Edge Platforms
Datta, Gourav	NVM-in-Cache: Repurposing Commodity 6T SRAM Cache into NVM Analog Processing-in-Memory Engine using a Novel Compute-on-Powerline Scheme A Time-Encoded Analog Photonic Interposer for Energy-Efficient Integration of Analog Vision Sensors and Analog Accelerators
Datta, Rajesh Kumar	Cube-based Finite-State-Machine Extraction via SAT Generalizations
Debin, Cao	Thermal-Aware Chiplet Placement Integrating Evolutionary Reinforcement Learning and Monte Carlo Tree Search
Deng, Erya	Low-Power Approximate MRAM CAM with Dynamic-Reference for HDC Associative Search A Reliability-Enhanced SOT-MTJ PUF with Obfuscated Write-Back for Physical-State Exposure Mitigation
Deng, Yi	AutoIsing: An Automated Compiler for Programmable Ising Machine
Deptuch, Grzegorz	FUSE: Five-Block MVM Energy Comparison
Di, Kangjian	Curvilinear OPC via Diffeomorphic Deformation
Di, Sheng	FLARE: A Dataflow-Aware and Scalable Hardware Architecture for Neural-Hybrid Scientific Lossy Compression
Di, Zhaohai	GAS: GPU Accelerated Schema Aware Exact Subcircuit Matching for Large-Scale Circuits
Ding, Chenchen	ScaleLUT: A Fully-Parallel Configurable LUT-Based Accelerator for Real-Time Multi-Scale Super-Resolution Weight-Stationary Fault Recovery via Neuron Tuning in RRAM-Based CIM Neuromorphic Accelerators
Ding, Li	Physics-Informed Generative Model Based Aging Library Characterization
Ding, Yifan	ATLAS: A Thermal-Aware 3D-Stacked Heterogeneous Architecture For LLM Multi-Turn Dialogue Serving
Dong, Minghao	PARFuzzer: Path-Aware RTL Fuzzing with Controlled BTB Conflict Injection for Branch-Predictor Security Validation
Dong, Ran	Reasoning and Modeling of Instruction Corruption of MCU under EMFI
Dong, Wenxuan	MaxIM: A Plug-and-Play Maxwellian Engine via Interface Modification for Thick-Mask Lithography MAGI-OPC: Manhattan Area–Edge Learning Guided by High-Quality ILT for Optical Proximity Correction
Du, Linfeng	HLSClaw: Bringing Vibe Coding to High-Level Synthesis through Skill-Based Agentic Harness
Duan, Zhenwei	ChronosDSE: Stability-Aware Design Space Exploration for GPGPUs
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Eiki, Makoto	TRAIT: Trajectory-based Robust Aging-aware Chip Identification for Traceability
Eles, Petru	Progressive Computation Scheduling for Deadline-Critical Tasks in Hierarchical Edge Networks
Emami, Ava	Online Open-World Wafer Defect Discovery using Hyperdimensional Computing
Er, Ilgaz	IMPACT: Constraint-Aware Search for Imperfectly Factorized Accelerator Mappings
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Fan, Guangxi	Sample-Efficient Neural Compact Modeling for Design-Technology Co-Optimization Based on Process-Aware Adaptation
Fan, Liang Ting	Structure-Preserving Density Modeling for Electrostatics-Based Analytical Placement
Fan, Pengcheng	PDN-Aware Graph Transformer-based Dynamic IR Drop Prediction with Criticality-Guided Subgraph Construction
Fan, Weijian	CRAFT: Constraint-Guided Region-Adaptive Search over Broad Design Spaces for High-Dimensional Analog Circuit Sizing
Fan, Yibo	Declared Event Semantics: Cross-Layer Memory-Hierarchy Co-Design for Latency-Critical Systems
Fang, Chao	MX-like Tensor Core for LLM Inference with NPU Integration via Hardware-Software Co-Design Exploration ARES: Adaptive Reasoning-Effort Steering for PPA- and Cost-Aware RTL Optimization with LLM Agents
Fang, Cheng-You	Reducing Read Retries by Skipping Similar Adjacent Read Voltage Parameters in 3D TLC NAND Flash
Fang, Yidong	CONTOUR: Continuous Topology Search for System-Level RFICs via Bi-Level Optimization and Neural-Analytical Co-Modeling
Fayazi, Morteza	ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Exploration
Fazzini, Leonardo	A Minimal MMU for Memory Virtualization on Microcontrollers for time-sensitive applications
Feng, Lang	PI-Aware Co-Layer Signal Routing and Power Plane Synthesis for Chiplet Interposers
Feng, Xincheng	NOVA-CIM: Noise- and Correlation-Tolerant Stochastic Interfaces for Analog Compute-in-Memory
Feng, Yu	An Efficient Layout Decomposition Framework via Unsatisfiable Core
Feng, Yuannuo	InfoCIM: An Information-Theoretic Framework for Modeling and Design of Noise-Limited Analog CIM ABNAT: Attention-Based Noise-Aware Training for Robust Transformers on Analog Compute-in-Memory Systems NANQ: Noise-Aware Mixed-Precision Non-Uniform Quantization for Neural Networks on Analog Compute-in-Memory ASSERT: Adaptive Stochastic Sampling for Robust Diffusion Models on Analog Compute-in-Memory Hardware
Feng, Zhuo	FRESHPart: Feedback-Reshaped Spectral Embedding for Hypergraph Partitioning
Ferber, Torben	CHAIDO: Open-Source Simulation-Based Fault Injection for the AMD Versal AI Engine
Ferrandi, Fabrizio	Memory-Aware Design-Space Exploration for Multi-Threaded HLS Accelerators
Fettweis, Gerhard	Accelerating 5G NR Channel Estimation with a Complex-Arithmetic RISC-V Vector Extension
Filip, Silviu-Ioan	SWAPPER: Dynamic Operand Swapping in Non-commutative Approximate Circuits for Online Error Reduction
Fiorito, Michele	Memory-Aware Design-Space Exploration for Multi-Threaded HLS Accelerators
Firoz, Jesun	Memory-Aware Design-Space Exploration for Multi-Threaded HLS Accelerators FUSE: Five-Block MVM Energy Comparison
Foik, Conrad	MAP-DSE: A Fast Performance Simulator for Large-Scale Microarchitectural Design Space Exploration
Fong, Xuanyao	A System-Level Typed-Graph Environment for Traceable Cycle-Level Co-Design of Heterogeneous AI Accelerators
Fu, Chao	S-cache Directory: Efficient Sharer Tracking for Entry-Constrained Coherence Directories
Fu, Jiamu	TreePIM: A Heterogeneous Processing-in-Memory Architecture for Tree-based Speculative Decoding
Fu, Rongliang	AgenticPD: A Stage-Aware Agentic Framework for Closed-Loop Physical Design Optimization
Fu, Yuxiang	AX-AGENT: Contract-Driven Closed-Loop Framework for Error-Bounded PPA-Aware Approximate RTL Generation
Fu, Zhaojing	CONTOUR: Continuous Topology Search for System-Level RFICs via Bi-Level Optimization and Neural-Analytical Co-Modeling
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Gajavelly, Raj Kumar	Decompose Transform Refine Verify: A new approach for scalable formal verification
Galuzzi, Carlo	Compiler-driven Optimizations for Efficient Host and Near-DRAM Co-Execution
Gamatié, Abdoulaye	GRACE: GRAph-based power Consumption Estimator with Parallel Switching Activity Propagation
Gangi, Nicholas	OptiClear: Differentiable Curvilinear Design Rule Legalization for Inverse-Designed Photonic Device
Gao, Bin	LUMEN: A Compressed-LUT-based Processing-Near-Memory Architecture for Efficient LLM Inference at the Edge ACED: An Algorithm–Hardware Co-Designed VLA Accelerator Exploiting Dynamic Weight-Precision Switching ActRAM: A Hybrid Analog/Digital Action-Expert Accelerator Architecture for Vision-Language-Action Models
Gao, Dongzhu	MATE: Model-Assisted Trade-off Exploration for Quality-Aware Approximate Matrix Computing
Gao, Fantao	From Isolate to Co-Deployment Risk: Coupling-Aware Mapping for ACIM-Digital AI Accelerator Device-Circuit Co-Optimization of SOT-MRAM with Accurate PPA Evaluation for Edge AI Training
Gao, Feiyang	AHEAD: A Fast and Efficient MoE Speculative Decoding System via Dynamic Draft–Verify Coordination
Gao, Huibo	Enabling Energy-Efficient TinyML Inference via Fused Tensor Architecture
Gao, Jianzhen	Q-COMPASS: A Circuit-Calibrated Simulation Framework for QDI NoC Architecture Exploration
Gao, Mingyu	Investigation of Karatsuba Algorithm for Large-Bitwidth Modular Multiplication
Gao, Xiaohan	APPlace: Co-Optimizing Device Locations and Access Points for Routing-Aware Analog Placement
Gao, Yimin	SLED-IFV: Solver-Validated LLM-Guided Decomposition for Scalable Hardware Information-Flow Verification
Gao, Ying	CoSim: A Cross-Layer Simulation Framework for System-Hardware Co-Design of LLM Inference
Gao, Yiwen	TraceMorph: Real-Trace-Guided Execution-Level Obfuscation for RAPL-Based DNN Architecture Protection
Gao, Yuan	CABAgent: A Cross-Stage Agentic Framework for Generating PDK-Compatible and Layout-Verified Analog Circuit Benchmarks
Gao, Zibo	ChronosDSE: Stability-Aware Design Space Exploration for GPGPUs
Garcia, Remi	SWAPPER: Dynamic Operand Swapping in Non-commutative Approximate Circuits for Online Error Reduction
Garcia Redondo, Fernando	CCD-KV: Exploiting High-Density 3D Charge-Coupled Device Memory for Efficient On-Device LLM KV Caches
Garcia-Bosque, Miguel	Power and EM Side-Channel Leakage Mitigation in Oscillator-Based PUFs via Sampling Techniques
Gardner, Isabella Venancia	aigverse: A Unified Infrastructure for Machine Learning-Driven Logic Synthesis
Gaydadjiev, Georgi	Compiler-driven Optimizations for Efficient Host and Near-DRAM Co-Execution IMPACT: Constraint-Aware Search for Imperfectly Factorized Accelerator Mappings
Ge, Guojing	LMSACO: LLM-Guided Multi-Objective State-Adaptive Analog Circuit Sizing Optimization
Ge, Jinming	HLSClaw: Bringing Vibe Coding to High-Level Synthesis through Skill-Based Agentic Harness
Ge, Ziang	Fast Delay-oriented Logic Optimization with Parallel SOP Generation
Geier, Johannes	MemFLoRA: Memory-Floor LoRA for CNN Adaptation at the Edge
Geng, Hao	MaxIM: A Plug-and-Play Maxwellian Engine via Interface Modification for Thick-Mask Lithography MAGI-OPC: Manhattan Area–Edge Learning Guided by High-Quality ILT for Optical Proximity Correction
Gerum, Christoph	Compiler-driven Generation of Domain-Specific AI Hardware Accelerators for Edge Devices
Goh, Wang Ling	CABAgent: A Cross-Stage Agentic Framework for Generating PDK-Compatible and Layout-Verified Analog Circuit Benchmarks
Gong, Ding	VoxPMC: A Fast Voxel-Based Particle Monte Carlo Simulator for Feature-Scale Process Topography Simulation
Gong, Yu	APRQ: Adaptive Prediction-Driven Residual Quantization Accelerator for Diffusion Transformers MATE: Model-Assisted Trade-off Exploration for Quality-Aware Approximate Matrix Computing TriM: Efficient MoE Inference on Edge CPU-GPU Systems via Fused Quantization and Sensitivity-Guided Scheduling
Gozzi, Giovanni	Memory-Aware Design-Space Exploration for Multi-Threaded HLS Accelerators
Graening, Alexander	Chiplet Assembly and Pre-Bond Qualification Planning for Heterogeneous Integrated Systems
Gu, Chongyan	A Lightweight Microring-Resonator PUF Design for Silicon Photonics Transceivers Lightweight Key-Based Hardware Device-ID Authentication: A Reliable, ML-Resistant Alternative to PUFs Power and EM Side-Channel Leakage Mitigation in Oscillator-Based PUFs via Sampling Techniques
Gu, Jiaqi	OptiClear: Differentiable Curvilinear Design Rule Legalization for Inverse-Designed Photonic Device
Guan, Haibing	MARCO: Markov Decision-based Adaptive Path Selection for Dynamic Layer Skipping
Gui, Yuhan	TriM: Efficient MoE Inference on Edge CPU-GPU Systems via Fused Quantization and Sensitivity-Guided Scheduling
Gui, Yupeng	Declared Event Semantics: Cross-Layer Memory-Hierarchy Co-Design for Latency-Critical Systems
Gungor, Onat	NgramRL: Accelerating RL Post-Training for Structured Generation via Rollout-Aware N-gram Speculative Decoding
Guo, Guannan	Logic Resynthesis for Cross-Die Dependencies in Hybrid Bonded 3D ICs RAPID: An Efficient and Accurate Ratio-Based Analytical Proxy for Interconnect Delay Anonymous: A CPU-GPU Heterogeneous Engine for Glitch-Aware Time-Based Gate-Level Power Analysis PACT: A Runtime Contract for Sparse-Topology Updates in GPU-Accelerated Timing ECOs Anonymous: Fast Clock-Aware Timing Propagation for Complex Clock Logic and Constraints with State Flow Graph Abstraction
Guo, Jiaqi	Efficient End-to-End Hyperprior-Based Learned Image Compression on Edge GPUs via Thread-Level Parallel Entropy Coding
Guo, Kairong	PACT: A Runtime Contract for Sparse-Topology Updates in GPU-Accelerated Timing ECOs
Guo, Luanzheng	FLARE: A Dataflow-Aware and Scalable Hardware Architecture for Neural-Hybrid Scientific Lossy Compression
Guo, Pengcheng	CRAFT: Constraint-Guided Region-Adaptive Search over Broad Design Spaces for High-Dimensional Analog Circuit Sizing
Guo, Ruiqi	TreePIM: A Heterogeneous Processing-in-Memory Architecture for Tree-based Speculative Decoding
Guo, Shengkai	AnchorGNN: Cross-PVT Corner Timing Prediction via Anchor-Guided Graph Learning and STA-Aware Propagation
Guo, Xiaotian	HB-VGGT: Exploiting Head-Wise Complementary Redundancy for Efficient VGGT Inference on Hybrid-Bonded Architecture
Guo, Zetao	VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts
Guo, Zizheng	RAPID: An Efficient and Accurate Ratio-Based Analytical Proxy for Interconnect Delay Anonymous: A CPU-GPU Heterogeneous Engine for Glitch-Aware Time-Based Gate-Level Power Analysis PACT: A Runtime Contract for Sparse-Topology Updates in GPU-Accelerated Timing ECOs Anonymous: Fast Clock-Aware Timing Propagation for Complex Clock Logic and Constraints with State Flow Graph Abstraction Obstacle-Aware Timing-Driven Buffer Insertion via Feasible Shallow-Light Topology Reconstruction
Gupta, Puneet	Chiplet Assembly and Pre-Bond Qualification Planning for Heterogeneous Integrated Systems
Gupta, Sumeet Kumar	BLINK: Batch NormaLization-based INtegrity ChecKpoints for In-Situ Detection and Mitigation of Diverse Weight Corruptions in DNN Accelerators
H
Habib, Mohammed Ayman	ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Exploration
Hamdioui, Said	OMNI-DC: One-shot Multi-input Neural-Inference-Based Data Converter for Analog Computation-in-Memory IMPACT: Constraint-Aware Search for Imperfectly Factorized Accelerator Mappings
Han, Jaeduk	An Explainable Analog/Mixed-Signal Routing Agent using Deterministic Constraint-Conflict Diagnosis
Han, Jie	REASON: RNG-Aware Finite-State Machines for Hardware-Realistic Stochastic Nonlinear Approximation CoEvoP&R: Co-Evolving Placement Objectives with Routing Feedback via Large Language Models
Han, Jun	S-cache Directory: Efficient Sharer Tracking for Entry-Constrained Coherence Directories
Han, Yaohui	AgenticPD: A Stage-Aware Agentic Framework for Closed-Loop Physical Design Optimization
Han, Yinhe	PI-Aware Co-Layer Signal Routing and Power Plane Synthesis for Chiplet Interposers When Fuzzing Meets Understanding: LLM-Driven Semantic Test Generation for RTL Verification
Han, Ziwei	Device-Circuit Co-Optimization of SOT-MRAM with Accurate PPA Evaluation for Edge AI Training
Hannig, Frank	CoD-MiCo: Co-Design of Mixed-Compression RISC-V Extensions for Neural Networks on FPGAs
Hanumolu, Pavan Kumar	A Waferscale Memory Architecture for Efficient LLM Inference
Hao, Ze	Thermal-Aware Chiplet Placement Integrating Evolutionary Reinforcement Learning and Monte Carlo Tree Search
Harbaum, Tanja	CHAIDO: Open-Source Simulation-Based Fault Injection for the AMD Versal AI Engine
Hashimoto, Masanori	Fine-Grained Compiler-Assisted Hardening via Tolerant-Output Analysis for SDC–Runtime Trade-offs
Hassan, Amna	UniCASE: A Unified 16-bit Floating Point Format with Criticality-Aware Selective ECC for Efficient DNN Protection
Hassan, Mohammed	T3R: Training-Free Two-Stage Token Refinement Towards Efficient and Robust VLA Models
Hayakawa, Soga	TRAIT: Trajectory-based Robust Aging-aware Chip Identification for Traceability
He, Han	Declared Event Semantics: Cross-Layer Memory-Hierarchy Co-Design for Latency-Critical Systems
He, Houbo	CONTOUR: Continuous Topology Search for System-Level RFICs via Bi-Level Optimization and Neural-Analytical Co-Modeling
He, Jiaji	PARFuzzer: Path-Aware RTL Fuzzing with Controlled BTB Conflict Injection for Branch-Predictor Security Validation DISSECT: Cross-Family RTL Trojan Localization by Auditing Structural–Functional Disagreement
He, Liu	SSR-VAR: Exploiting Spatial- and Scale-aware Redundancy for Lightweight Inference of Visual Autoregressive Models
He, Maoshuo	HINT: Toward an Executable Hardware-Intent Intermediate Representation Layer for LLM-Driven RTL Generation
He, Ruihao	An Area-Efficient CIM-Based Ising Annealer with Folded Mapping and Cooling-Scheduled Parallel Swaps Strategy for Large-Scale Traveling Salesman Problem
He, Songxuan	Cross-Family Graph Learning for Sparse Aging-Aware Timing Characterization of Standard-Cell Libraries
He, Yixuan	TriM: Efficient MoE Inference on Edge CPU-GPU Systems via Fused Quantization and Sensitivity-Guided Scheduling
He, Zhuolun	FormalPCell: Formal DRC Verification of Parameterized Layout Cells via Symbolic Interpretation and SMT Solving
Hefenbrock, Michael	SURE-AI: Single-pass Uncertainty Estimation for Reliable Edge AI Accelerators
Hemaram, Surendra	OMNI-DC: One-shot Multi-input Neural-Inference-Based Data Converter for Analog Computation-in-Memory
Hirasawa, Shoichi	Observability-Aware Runtime Reliability for MZI-Based Optical Neural Networks
Ho, Chia-Tung	SCALE: Self-Supervised Constraint-Aware Layout Generation for Local P&R DRV Fixing at Advanced Nodes EvoDRC: A Self-Evolving Agentic Framework for Automated DRC Violation Repair
Ho, Chien-Chung	Reducing Read Retries by Skipping Similar Adjacent Read Voltage Parameters in 3D TLC NAND Flash
Ho, Tsung-Yi	A HeteroGNN-Based Hierarchical Co-Optimization Framework for Floorplanning and Routing in Advanced Packaging HOIST: A High-Order Interaction Surrogate for Sample-Efficient High-Sigma Yield Estimation in High-Dimensional Circuits AgenticPD: A Stage-Aware Agentic Framework for Closed-Loop Physical Design Optimization MoL-PAM: Joint P/G TSV Planning and Macro Refinement for Memory-on-Logic 3D ICs via a Benders-Type Decomposition Heuristic
Holmes, Steven	Online Open-World Wafer Defect Discovery using Hyperdimensional Computing
Hong, Jingkai	Fanout-Multiplicity-Aware Technology Mapping for Multi-Output Superconducting Logic qLevelPlace: A Level-Based Placement Framework for RSFQ Circuits
Hong, Puyang	TriM: Efficient MoE Inference on Edge CPU-GPU Systems via Fused Quantization and Sensitivity-Guided Scheduling
Honkote, Vinayak	SiliDiff: Post-Silicon Thermal and Power Reconstruction from Sparse Sensing with a Cascaded Conditional Diffusion Model
Hsieh, Ming-Hui	Spec2Plan: An LLM-Powered Framework for Comprehensive Verification Plan Generation
Hsu, Chen-Hao	ARC: Any-Angle PCB Routing with Obstacle Avoidance under Complex Design Rules
Hsu, Po-Kai	HAVEN: High-Bandwidth Flash Augmented Vector ENgine for Large-Scale Approximate Nearest-Neighbor Search Acceleration
Hsu, Yang	ARC: Any-Angle PCB Routing with Obstacle Avoidance under Complex Design Rules
Hsu, Yi-An	Prefix-Branch Software Co-Design for Random Forest Acceleration on Embedded Hybrid TCAMs
Hu, Bo	APRQ: Adaptive Prediction-Driven Residual Quantization Accelerator for Diffusion Transformers
Hu, Chenxi	NOVA-CIM: Noise- and Correlation-Tolerant Stochastic Interfaces for Analog Compute-in-Memory
Hu, Guangyu	Inverter Redistribution through Self-Dual and Self-Anti-Dual Function Transformation
Hu, Hailiang	AccTTS: Characterizing and Optimizing Workload Dynamics in Test-Time Scaling
Hu, Jiang	AccTTS: Characterizing and Optimizing Workload Dynamics in Test-Time Scaling
Hu, Jinhai	CABAgent: A Cross-Stage Agentic Framework for Generating PDK-Compatible and Layout-Verified Analog Circuit Benchmarks
Hu, Liguo	VoxPMC: A Fast Voxel-Based Particle Monte Carlo Simulator for Feature-Scale Process Topography Simulation
Hu, Xiangfei	HINT: Toward an Executable Hardware-Intent Intermediate Representation Layer for LLM-Driven RTL Generation
Hu, Yang	TreePIM: A Heterogeneous Processing-in-Memory Architecture for Tree-based Speculative Decoding
Hu, Yichen	APRQ: Adaptive Prediction-Driven Residual Quantization Accelerator for Diffusion Transformers
Hu, Ying	LMSACO: LLM-Guided Multi-Objective State-Adaptive Analog Circuit Sizing Optimization
Hu, Zhewen	FLARE: A Dataflow-Aware and Scalable Hardware Architecture for Neural-Hybrid Scientific Lossy Compression
Hua, Qiao	PDN-Aware Graph Transformer-based Dynamic IR Drop Prediction with Criticality-Guided Subgraph Construction
Hua, Shenglu	PACT: A Runtime Contract for Sparse-Topology Updates in GPU-Accelerated Timing ECOs
Huang, Alyssa	Naviq: An Open-Source System-on-Chip Simulator for Rapid Prototyping, Verification, and Design Space Exploration
Huang, Binxiao	ScaleLUT: A Fully-Parallel Configurable LUT-Based Accelerator for Real-Time Multi-Scale Super-Resolution
Huang, Chung-Yang Ric	Spec2Plan: An LLM-Powered Framework for Comprehensive Verification Plan Generation
Huang, Kai	Enabling Energy-Efficient TinyML Inference via Fused Tensor Architecture
Huang, Kaiqi	SRAM Bitcell-Peripheral Co-Optimization Under Array-Level Yield Constraints
Huang, Pei-Yu	ThTrace: A High-Efficiency Displacement Field Simulator for Advanced Packaging
Huang, Rena	OptiClear: Differentiable Curvilinear Design Rule Legalization for Inverse-Designed Photonic Device
Huang, Ru	ABNAT: Attention-Based Noise-Aware Training for Robust Transformers on Analog Compute-in-Memory Systems
Huang, Shanshi	SpikeFold: An FPGA-based Neuromorphic Processor with DSP Optimization and Parallel Weight Update STDP
Huang, Sheng-Yang	Placement Guidance Generation via Timing-Aware Hypergraph Partitioning and Multi-Criteria Cluster Selection
Huang, Sitao	EdgeDAE: Acceleration of Diffusion Action Experts for Real-Time Physical AI with Tiny VLAs on Edge FPGA-GPU Systems
Huang, Xianmin	CAS: A Ferroelectric Compute-in-Memory Annealer for Sparse Combinatorial Optimization Problems
Huang, Yafan	FLARE: A Dataflow-Aware and Scalable Hardware Architecture for Neural-Hybrid Scientific Lossy Compression
Huang, Yi	Thermal-Aware Chiplet Placement Integrating Evolutionary Reinforcement Learning and Monte Carlo Tree Search
Huang, Yiqi	A HeteroGNN-Based Hierarchical Co-Optimization Framework for Floorplanning and Routing in Advanced Packaging
Huang, Zirun	MAESTRO: Memo-Augmented Multi-Agent Engine for Self-Testing RTL Code Generation with Resource Orchestration
Hung, Yu-Ting	A Dual-Branch GAT-MLP Framework for Efficient Bump-Level Dynamic IR Drop Prediction in Flip-Chip Packages
Huo, Zongliang	AHEAD: A Fast and Efficient MoE Speculative Decoding System via Dynamic Draft–Verify Coordination
Hwang, Seung-Eon	TempoGS: Temporal Binning and Expiration-Aware Gaussian Loading for Memory-Efficient 4D Gaussian Splatting Acceleration
Hwang, Yejin	CalNet: Temperature-Robust ADC Calibration via Learned BGR Behavior and LUT Correction
I
Ide, Tsuyoshi	Online Open-World Wafer Defect Discovery using Hyperdimensional Computing
Ishiura, Shokei	Scalable Quantum Circuits Partitioning via Shortest-Path Search and Circuit Transformation
Ito, Hisako	Resource-Efficient Heterogeneous CGRA for Kernels with Control Flow
Ivantsiv, Austin	Compiler-driven Optimizations for Efficient Host and Near-DRAM Co-Execution
J
Jafri, Taizun	VPR-Evolve: Multi-Agent-Driven Algorithm Evolution for FPGA Place and Route
Jaipuria, Saumya	Decompose Transform Refine Verify: A new approach for scalable formal verification
Jaiswal, Akhilesh	NVM-in-Cache: Repurposing Commodity 6T SRAM Cache into NVM Analog Processing-in-Memory Engine using a Novel Compute-on-Powerline Scheme A Time-Encoded Analog Photonic Interposer for Energy-Efficient Integration of Analog Vision Sensors and Analog Accelerators
Jang, Shinhyoung	Reducing Cascaded Speech-to-Speech Latency via Speculative Prefilling and Incremental Cache Recovery
Jeon, Chanhong	CalNet: Temperature-Robust ADC Calibration via Learned BGR Behavior and LUT Correction
Jeon, Gangmin	Thermal-Aware Chiplet Placement and Shape Co-Optimization under D2D Interconnect Constraints for 2.5D Integration
Jeon, Seunggu	IMPACT: IoT SNN Inference with a Metadata-Guided Pulse-Width Control Architecture for Conductance-Time Weight Representation in RRAM
Ji, Keyi	ATLAS: A Thermal-Aware 3D-Stacked Heterogeneous Architecture For LLM Multi-Turn Dialogue Serving
Ji, Yuede	FLARE: A Dataflow-Aware and Scalable Hardware Architecture for Neural-Hybrid Scientific Lossy Compression
Ji, Yuhao	Logic Resynthesis for Cross-Die Dependencies in Hybrid Bonded 3D ICs MoL-PAM: Joint P/G TSV Planning and Macro Refinement for Memory-on-Logic 3D ICs via a Benders-Type Decomposition Heuristic Obstacle-Aware Timing-Driven Buffer Insertion via Feasible Shallow-Light Topology Reconstruction
Jia, Bo Wen	LMSACO: LLM-Guided Multi-Objective State-Adaptive Analog Circuit Sizing Optimization
Jia, Bonian	SPICE: Speculative Prefetching with Low-Rank Expert Surrogates and Heterogeneous Orchestration for MoE Inference Acceleration
Jia, Hongyang	SSR-VAR: Exploiting Spatial- and Scale-aware Redundancy for Lightweight Inference of Visual Autoregressive Models
Jia, Shuao	FADiff: Fusion-Aware Differentiable Optimization for DNN Scheduling on Tensor Accelerators
Jia, Tianyu	DREAM:3D-stacked Token-wise Caching Diffusion Accelerator with Resource-Aware Mapping ATLAS: A Thermal-Aware 3D-Stacked Heterogeneous Architecture For LLM Multi-Turn Dialogue Serving
Jia, Wen	From Isolate to Co-Deployment Risk: Coupling-Aware Mapping for ACIM-Digital AI Accelerator
Jia, Wenqi	FLARE: A Dataflow-Aware and Scalable Hardware Architecture for Neural-Hybrid Scientific Lossy Compression
Jia, Yufan	S-cache Directory: Efficient Sharer Tracking for Entry-Constrained Coherence Directories
Jiang, Baizhou	ScaleLUT: A Fully-Parallel Configurable LUT-Based Accelerator for Real-Time Multi-Scale Super-Resolution
Jiang, Dejun	MinVNS: Minimal Virtual Network Separation for Deadlock Avoidance in Modular Network-on-Chip
Jiang, Haoning	GLARE: Generalizable Large-scale Analog Sizing via Reinforcement Learning with Covariance-Guided Exploration
Jiang, Hongwu	An Area-Efficient CIM-Based Ising Annealer with Folded Mapping and Cooling-Scheduled Parallel Swaps Strategy for Large-Scale Traveling Salesman Problem
Jiang, Iris Hui-Ru	Gradient-Guided Thermal-Aware Timing Robustness Optimization Under Temperature Inversion Physics-Informed Generative Model Based Aging Library Characterization
Jiang, Jiaxi	MoL-PAM: Joint P/G TSV Planning and Macro Refinement for Memory-on-Logic 3D ICs via a Benders-Type Decomposition Heuristic
Jiang, Jingbo	Taming Irregular Sparsity with a Regular Systolic Array for Efficient DNN Training
Jiang, Junmin	GLARE: Generalizable Large-scale Analog Sizing via Reinforcement Learning with Covariance-Guided Exploration
Jiang, Ke	Progressive Computation Scheduling for Deadline-Critical Tasks in Hierarchical Edge Networks
Jiang, Li	MARCO: Markov Decision-based Adaptive Path Selection for Dynamic Layer Skipping
Jiang, Xinting	CircuitsDNA: Discovering Unconventional Multi-Accuracy Arithmetic Circuits via Evolutionary Synthesis
Jiang, Yuming	QoS Analysis for UCIe-based Cross-die Communication using Network Calculus
Jiang, Yuxiao	UnO-NeSy: Optimizing Neuro-Symbolic Computing with Unified FeFET Based In-Memory System
Jiao, Changzhe	FlowMapper: Detection-Guided Topology Reconstruction of Circuit Block Diagrams
Jiao, Junming	XCTS: Cross-Tier-Aware Differentiable Clock Tree Synthesis for 3D Integrated Circuits
Jiaqi, Yu	MfSpGEMM: Merger-Free Row-Wise SpGEMM with Bitmap Accumulation and HBM-Aware Mapping
Jin, Leilei	AgenticPD: A Stage-Aware Agentic Framework for Closed-Loop Physical Design Optimization
Jin, Sian	FLARE: A Dataflow-Aware and Scalable Hardware Architecture for Neural-Hybrid Scientific Lossy Compression
Jing, Guocheng	A Reliability-Enhanced SOT-MTJ PUF with Obfuscated Write-Back for Physical-State Exposure Mitigation
Jing, Minge	Declared Event Semantics: Cross-Layer Memory-Hierarchy Co-Design for Latency-Critical Systems
Jivanescu, Mihaela	ARES: Adaptive Reasoning-Effort Steering for PPA- and Cost-Aware RTL Optimization with LLM Agents
Josh, Rajiv	Online Open-World Wafer Defect Discovery using Hyperdimensional Computing
Joshi, Chinmay P	An In-situ Self Clock-Gated 7474 Style Scan-Mux-D Low Power Flip-Flop
K
Kalra, Sudaksh	SHARD: Sub-Transformer Harnessing for Adaptive Resource-Aware Deployment
Kang, Byeonggon	Multi-Output-Guided Transistor Network Synthesis and Layout for Sequential Cells
Kang, Mingu	KV3D: KV Cache-Centric Monolithic 3D-Stackable DRAM-Based Accelerator for LLM Serving
Kang, Seokhyeong	DPSQ : Dynamic Partial Sum Quantization with Mixed Granularity SpectraPlace2.5D: Thermal-aware Chiplet Placement via Topology-guided MILP and Spectral Thermal Modeling Phase-Aware Monte Carlo Tree Search with LLM-Guided Proposal for Multi-Objective Physical Design Tuning Multi-Output-Guided Transistor Network Synthesis and Layout for Sequential Cells Operation-Aware Twisting of Folded Bit-Lines for Crosstalk Cancellation in Wafer-Bonded DRAM
Kang, Taewook	CalNet: Temperature-Robust ADC Calibration via Learned BGR Behavior and LUT Correction
Kang, Wang	InfoCIM: An Information-Theoretic Framework for Modeling and Design of Noise-Limited Analog CIM STRIDE: Sparse Thermal Reconstruction-Informed Differential Encoding for Thermally Stable 3D-Integrated Analog CIM NANQ: Noise-Aware Mixed-Precision Non-Uniform Quantization for Neural Networks on Analog Compute-in-Memory ASSERT: Adaptive Stochastic Sampling for Robust Diffusion Models on Analog Compute-in-Memory Hardware
Karn, Rupesh Raj	Functional Retrieval for Resynthesis-Robust Hardware Trojan Detection in Gate-Level Netlists Functionality-Aware Is Not Synthesis-Invariant: An End-to-End Audit of Circuit-GNN Representations
Karri, Ramesh	CoEvoP&R: Co-Evolving Placement Objectives with Routing Feedback via Large Language Models
Khailany, Brucek	SCALE: Self-Supervised Constraint-Aware Layout Generation for Local P&R DRV Fixing at Advanced Nodes FRESHPart: Feedback-Reshaped Spectral Embedding for Hypergraph Partitioning EvoDRC: A Self-Evolving Agentic Framework for Automated DRC Violation Repair
Khalili Sadaghiani, Abdolvahab	ACCORD-IC: Contract-Checked Relation Transactions for Low-Bit Dynamic CNN–GNN Inference
Khan, Marzia	BLINK: Batch NormaLization-based INtegrity ChecKpoints for In-Situ Detection and Mitigation of Diverse Weight Corruptions in DNN Accelerators
Kielian, Gregory	CircuitsDNA: Discovering Unconventional Multi-Accuracy Arithmetic Circuits via Evolutionary Synthesis
Kim, Changbeom	Multi-Output-Guided Transistor Network Synthesis and Layout for Sequential Cells
Kim, Gyumin	Power Network Topology Optimization for Top Dies in Backside-Powered F2F 3D ICs
Kim, Hayoung	Multi-Output-Guided Transistor Network Synthesis and Layout for Sequential Cells
Kim, Hojeong	Reducing Cascaded Speech-to-Speech Latency via Speculative Prefilling and Incremental Cache Recovery
Kim, Hyunwoo	SpectraPlace2.5D: Thermal-aware Chiplet Placement via Topology-guided MILP and Spectral Thermal Modeling
Kim, Ikkyum	DiffTherm: A Differentiable Thermal Formulation for Cell-Via Co-Optimization in 3D ICs Thermal-Aware Chiplet Placement and Shape Co-Optimization under D2D Interconnect Constraints for 2.5D Integration A Comprehensive Clock Tree Synthesis with Useful Skew for 3D ICs
Kim, Jaehyun	CalNet: Temperature-Robust ADC Calibration via Learned BGR Behavior and LUT Correction
Kim, Joo-Young	PaFeDSE: Pareto-Feedback-Guided Microarchitecture Design Space Exploration for Efficient Pareto Search
Kim, Joonseok	DPSQ : Dynamic Partial Sum Quantization with Mixed Granularity
Kim, Sehyeon	Multi-Output-Guided Transistor Network Synthesis and Layout for Sequential Cells
Kim, Seohyun	Clock Distribution Network with Backside Clock Mesh in BSPDN Architecture
Kim, Seojin	CalNet: Temperature-Robust ADC Calibration via Learned BGR Behavior and LUT Correction
Kim, Seungsu	GD-PIM: A Low-Cost Gustavson Dataflow-Based Processing-in-Memory Architecture for SpGEMM
Kim, Yeseong	Reducing Cascaded Speech-to-Speech Latency via Speculative Prefilling and Incremental Cache Recovery
Kim, Younghyun	DPSQ : Dynamic Partial Sum Quantization with Mixed Granularity
Klein, Joshua	Compiler-driven Optimizations for Efficient Host and Near-DRAM Co-Execution CCD-KV: Exploiting High-Density 3D Charge-Coupled Device Memory for Efficient On-Device LLM KV Caches
Knechtel, Johann	Functional Retrieval for Resynthesis-Robust Hardware Trojan Detection in Gate-Level Netlists Functionality-Aware Is Not Synthesis-Invariant: An End-to-End Audit of Circuit-GNN Representations
Koibuchi, Michihiro	Observability-Aware Runtime Reliability for MZI-Based Optical Neural Networks
Kojima, Takuya	Resource-Efficient Heterogeneous CGRA for Kernels with Control Flow
Kong, Jason	NgramRL: Accelerating RL Post-Training for Structured Generation via Rollout-Aware N-gram Speculative Decoding
Kong, Qifeng	Low-Power Approximate MRAM CAM with Dynamic-Reference for HDC Associative Search
Kook, Myungjun	Operation-Aware Twisting of Folded Bit-Lines for Crosstalk Cancellation in Wafer-Bonded DRAM
Kotyad, Munawira	BB8: Blocking Buffer for breaking head-of-line stalling in GPGPUs via Instruction Bypassing.
Kritikakou, Angeliki	SWAPPER: Dynamic Operand Swapping in Non-commutative Approximate Circuits for Online Error Reduction
Kuan, Ta-Yu	Placement Guidance Generation via Timing-Aware Hypergraph Partitioning and Multi-Criteria Cluster Selection
Kukić, Patrik	Compiler-driven Optimizations for Efficient Host and Near-DRAM Co-Execution
Kumar, Rakesh	A Waferscale Memory Architecture for Efficient LLM Inference
Kuo, Ming-Yi	Multi-Agent LLM Serving with SSD-Based KV-Cache Offloading
Kuo, Yen-Ting	Placement Guidance Generation via Timing-Aware Hypergraph Partitioning and Multi-Criteria Cluster Selection
Kwan, Bryan	GREG: A Graphical Static Analysis Framework for Early Hardware Security Verification
Kwon, Dowon	DPSQ : Dynamic Partial Sum Quantization with Mixed Granularity
L
Lai, Chengtao	DFAC: Dataflow-Aided Intra-cluster Coalescer for AI Accelerators
Lai, Jinmei	Efficient End-to-End Hyperprior-Based Learned Image Compression on Edge GPUs via Thread-Level Parallel Entropy Coding
Lai, Xunqin	SpikeFold: An FPGA-based Neuromorphic Processor with DSP Optimization and Parallel Weight Update STDP
Lan, Yi-Xin	Gradient-Guided Thermal-Aware Timing Robustness Optimization Under Temperature Inversion
Lanz, Marissa	Naviq: An Open-Source System-on-Chip Simulator for Rapid Prototyping, Verification, and Design Space Exploration
Lao, Yingjie	DRS: Unified Fully Homomorphic Encryption Hardware Accelerator with Scheme-Switching
Laurie, Ben	CircuitsDNA: Discovering Unconventional Multi-Accuracy Arithmetic Circuits via Evolutionary Synthesis
Lee, Dalhee	Multi-Output-Guided Transistor Network Synthesis and Layout for Sequential Cells
Lee, Donghyuk	Placement-Aware Logic Resynthesis with Cooperative Multi-Agent Reinforcement Learning
Lee, Donghyun	An Explainable Analog/Mixed-Signal Routing Agent using Deterministic Constraint-Conflict Diagnosis
Lee, Dongyoung	AlignQuant: Alignment First Two-Stage Integer Microscaling Format for Systolic Native LLM Inference
Lee, Hyeonjae	SpectraPlace2.5D: Thermal-aware Chiplet Placement via Topology-guided MILP and Spectral Thermal Modeling
Lee, Hyojeong	PaFeDSE: Pareto-Feedback-Guided Microarchitecture Design Space Exploration for Efficient Pareto Search
Lee, Hyunsei	Reducing Cascaded Speech-to-Speech Latency via Speculative Prefilling and Incremental Cache Recovery
Lee, Janie	MIBIFI: Differentiable Electronic–Photonic–Thermal Co-Simulation for Co-Packaged Optics Designs
Lee, Jason Jaesung	IMPACT: IoT SNN Inference with a Metadata-Guided Pulse-Width Control Architecture for Conductance-Time Weight Representation in RRAM
Lee, Jeongmin	CalNet: Temperature-Robust ADC Calibration via Learned BGR Behavior and LUT Correction
Lee, Jongeun	DRAC: A Static Analysis for DRAM Row Activation Count Toward Efficient Processing-in-Memory Code Generation GD-PIM: A Low-Cost Gustavson Dataflow-Based Processing-in-Memory Architecture for SpGEMM
Lee, Junyoung	Reducing Cascaded Speech-to-Speech Latency via Speculative Prefilling and Incremental Cache Recovery
Lee, Ming-Chao	Gradient-Guided Thermal-Aware Timing Robustness Optimization Under Temperature Inversion
Lee, Sangdong	AlignQuant: Alignment First Two-Stage Integer Microscaling Format for Systolic Native LLM Inference
Lee, Seungjong	CalNet: Temperature-Robust ADC Calibration via Learned BGR Behavior and LUT Correction
Lee, Shang-Che	Cross-Layer Reinforcement Learning for Power-Via Optimization in Multilayer RDL Power/Ground Plane Synthesis
Lee, Shih-Kai	Physics-Informed Generative Model Based Aging Library Characterization
Lee, Yu-Chen	Multi-Agent LLM Serving with SSD-Based KV-Cache Offloading
Lee, Yu-Min	ThTrace: A High-Efficiency Displacement Field Simulator for Advanced Packaging
Lei, Tao	Security-Aware Runtime Control for Mitigating Token-Acceptance Side Channels in PIM/3D-Memory Speculative LLM Inference Architectures
Li, Bing	SpecLens: LLM-Based Verilog Generation with Specification-Derived Constraints via Behavioral Divergence
Li, Bo	CktHVR: A Convergence-Aware GNN-VLM Hypothesize-Verify-Refine Framework for Analog Circuit Topology Rectification
Li, Boyu	ScaleLUT: A Fully-Parallel Configurable LUT-Based Accelerator for Real-Time Multi-Scale Super-Resolution
Li, Cangyuan	When Fuzzing Meets Understanding: LLM-Driven Semantic Test Generation for RTL Verification
Li, Chaojian	T3R: Training-Free Two-Stage Token Refinement Towards Efficient and Robust VLA Models
Li, Guoxiang	HB-VGGT: Exploiting Head-Wise Complementary Redundancy for Efficient VGGT Inference on Hybrid-Bonded Architecture
Li, Huimin	Secure Reconfiguration for Multi-Tenant FPGAs
Li, Jiale	ResistONet: Cascade Operator Network for Photoresist Simulation Chain of SRAF Generation: A Large Reasoning Model for Sub-resolution Assist Features Curvilinear OPC via Diffeomorphic Deformation EtchMO: A Differentiable Etch Model for Mask Optimization
Li, Jiaming	ActRAM: A Hybrid Analog/Digital Action-Expert Accelerator Architecture for Vision-Language-Action Models
Li, Jiancong	PSD-CIM:A Computing-In-Memory Attention Accelerator with Predictor-Free Sparsity search and Distribution Shaping
Li, Jiayi	Hit-SME: A High-throughput Hybrid SNN-based MLP Engine for Neural Volume Rendering A Two Stage Learning-Based Thermal-Aware Framework for 3D Fixed-Outline Soft-Module Floorplanning across Chip Sizes
Li, Jingyuan	CoSim: A Cross-Layer Simulation Framework for System-Hardware Co-Design of LLM Inference
Li, Jintao	SPGLA-Net: A Slotline-Aware Port-Graph Linear Attention Residual Network for Sub-THz On-Chip Passive Modeling
Li, Ke	From Communities to Coordinates: Hierarchical Clustering–Guided Placement for Large-Scale FPGAs
Li, Li	AX-AGENT: Contract-Driven Closed-Loop Framework for Error-Bounded PPA-Aware Approximate RTL Generation
Li, Linyang	Sample-Efficient Neural Compact Modeling for Design-Technology Co-Optimization Based on Process-Aware Adaptation
Li, Mengming	RAP: Resource‑Aware Scheduling for GPU Accelerated Hypergraph Partitioning UnifyPower: A Unified Framework of Architecture-Level Power Model for Processors
Li, Min	Adaptive BTOR2 Reformulation via Solver-Aware Equality Saturation
Li, Ning	SPICE: Speculative Prefetching with Low-Rank Expert Surrogates and Heterogeneous Orchestration for MoE Inference Acceleration
Li, Pengjia	GAS: GPU Accelerated Schema Aware Exact Subcircuit Matching for Large-Scale Circuits
Li, Qiuyu	Declared Event Semantics: Cross-Layer Memory-Hierarchy Co-Design for Latency-Critical Systems
Li, Renchao	EMPUF: A Leakage-Controlled Pre-Fabrication Benchmark for PCB Spectral Fingerprints
Li, Sensen	CONTOUR: Continuous Topology Search for System-Level RFICs via Bi-Level Optimization and Neural-Analytical Co-Modeling
Li, Shangkun	HLSClaw: Bringing Vibe Coding to High-Level Synthesis through Skill-Based Agentic Harness
Li, Shaoxuan	An Area-Efficient CIM-Based Ising Annealer with Folded Mapping and Cooling-Scheduled Parallel Swaps Strategy for Large-Scale Traveling Salesman Problem
Li, Tong	PSD-CIM:A Computing-In-Memory Attention Accelerator with Predictor-Free Sparsity search and Distribution Shaping
Li, Wantong	SymbOperon: Composable and Cost-Efficient Symbolic Reasoning Operators for Neuro-Symbolic Edge Perception
Li, Wenkai	RAP: Resource‑Aware Scheduling for GPU Accelerated Hypergraph Partitioning UnifyPower: A Unified Framework of Architecture-Level Power Model for Processors
Li, Xiaofei	RobotCFU: A Tightly Coupled Multi-Operator CFU for Embedded RISC-V Robot Control
Li, Xiaoli	CABAgent: A Cross-Stage Agentic Framework for Generating PDK-Compatible and Layout-Verified Analog Circuit Benchmarks
Li, Xing	PP2Tree: Learning-Guided Frontier Partitioning for Scalable Parallel Logic Synthesis
Li, Xueqing	Security-Aware Runtime Control for Mitigating Token-Acceptance Side Channels in PIM/3D-Memory Speculative LLM Inference Architectures
Li, Yaguang	SCALE: Self-Supervised Constraint-Aware Layout Generation for Local P&R DRV Fixing at Advanced Nodes
Li, Yanchen	Enabling Efficient Quantized LLM Inference on Floating-Point CGRAs via Lightweight Integer Extensions
Li, Yanfeng	From DRAM Architecture to Protocol State: A Resource-Grounded Executable Semantics for LPDDR5
Li, Yanqin	UnifyPower: A Unified Framework of Architecture-Level Power Model for Processors
Li, Yapeng	GAS: GPU Accelerated Schema Aware Exact Subcircuit Matching for Large-Scale Circuits
Li, Yi	PSD-CIM:A Computing-In-Memory Attention Accelerator with Predictor-Free Sparsity search and Distribution Shaping
Li, Yi-Ting	A Dual-Branch GAT-MLP Framework for Efficient Bump-Level Dynamic IR Drop Prediction in Flip-Chip Packages
Li, Yun	SPGLA-Net: A Slotline-Aware Port-Graph Linear Attention Residual Network for Sub-THz On-Chip Passive Modeling
Li, Zepeng	A HeteroGNN-Based Hierarchical Co-Optimization Framework for Floorplanning and Routing in Advanced Packaging
Li, Zewen	GARDEN: GPU-Accelerated Rapid Divisor Extraction
Li, Zheyu	Cross-Layer Co-Designed In-Memory Hyperdimensional Computing Accelerator for Proteomics at the Edge
Li, Zhijun	CktHVR: A Convergence-Aware GNN-VLM Hypothesize-Verify-Refine Framework for Analog Circuit Topology Rectification
Liang, Jiawei	GLARE: Generalizable Large-scale Analog Sizing via Reinforcement Learning with Covariance-Guided Exploration HLSClaw: Bringing Vibe Coding to High-Level Synthesis through Skill-Based Agentic Harness
Liang, Rongjian	FRESHPart: Feedback-Reshaped Spectral Embedding for Hypergraph Partitioning AccTTS: Characterizing and Optimizing Workload Dynamics in Test-Time Scaling
Liang, Sen	MinVNS: Minimal Virtual Network Separation for Deadlock Avoidance in Modular Network-on-Chip
Liang, Xiaoxiao	RT-DRC: Accelerating Design Rule Checking Using GPU Ray-Tracing Cores
Liang, Yixun	Nexus: Activity-Aware Capacity-Constrained Neuron Partitioning for Multicore SNN Accelerators
Liang, Yun	Anonymous: A CPU-GPU Heterogeneous Engine for Glitch-Aware Time-Based Gate-Level Power Analysis Anonymous: Fast Clock-Aware Timing Propagation for Complex Clock Logic and Constraints with State Flow Graph Abstraction
Liang, Zhao	MfSpGEMM: Merger-Free Row-Wise SpGEMM with Bitmap Accumulation and HBM-Aware Mapping
Liao, Han-Yu	Reducing Read Retries by Skipping Similar Adjacent Read Voltage Parameters in 3D TLC NAND Flash
Lim, Hyerin	TempoGS: Temporal Binning and Expiration-Aware Gaussian Loading for Memory-Efficient 4D Gaussian Splatting Acceleration
Lim, Sung Kyu	Encoding Symmetries into Operator Learning: Towards Accurate Multi-Physics Simulation in Advanced Packaging Grad-BSS: Differentiable Optimization for Full-Stack Backside Signal Routing
Lin, Bill	Multi-Output-Guided Transistor Network Synthesis and Layout for Sequential Cells
Lin, Guangyao	Q-COMPASS: A Circuit-Calibrated Simulation Framework for QDI NoC Architecture Exploration
Lin, Jai Ming	Structure-Preserving Density Modeling for Electrostatics-Based Analytical Placement
Lin, Jiaming	APRQ: Adaptive Prediction-Driven Residual Quantization Accelerator for Diffusion Transformers
Lin, Mark Po-Hung	Cross-Layer Reinforcement Learning for Power-Via Optimization in Multilayer RDL Power/Ground Plane Synthesis
Lin, Ning	AutoIsing: An Automated Compiler for Programmable Ising Machine
Lin, Ning	Weight-Stationary Fault Recovery via Neuron Tuning in RRAM-Based CIM Neuromorphic Accelerators
Lin, Po-Jen	Efficient Concurrent Die-to-Die Routing with Teardrop and Offset-Via Awareness
Lin, Ranxi	Hit-SME: A High-throughput Hybrid SNN-based MLP Engine for Neural Volume Rendering
Lin, Shang-Wei	A Resource-Efficient Quantum Circuit for Fixed-Point Logarithm Operations with Analytical Error Bounds
Lin, Shiju	Node Reduction via Targeted ODC-Based Wire Additions for AIG Optimization Inverter Redistribution through Self-Dual and Self-Anti-Dual Function Transformation
Lin, Xiaokun	PI-Aware Co-Layer Signal Routing and Power Plane Synthesis for Chiplet Interposers
Lin, Yibo	SPLIT-MOR: Fast and Accurate Model Order Reduction for Nonlinear Transient Thermal Simulation of 2.5D/3D ICs CRAFT: Constraint-Guided Region-Adaptive Search over Broad Design Spaces for High-Dimensional Analog Circuit Sizing RAPID: An Efficient and Accurate Ratio-Based Analytical Proxy for Interconnect Delay Anonymous: A CPU-GPU Heterogeneous Engine for Glitch-Aware Time-Based Gate-Level Power Analysis PACT: A Runtime Contract for Sparse-Topology Updates in GPU-Accelerated Timing ECOs MoL-PAM: Joint P/G TSV Planning and Macro Refinement for Memory-on-Logic 3D ICs via a Benders-Type Decomposition Heuristic Anonymous: Fast Clock-Aware Timing Propagation for Complex Clock Logic and Constraints with State Flow Graph Abstraction Obstacle-Aware Timing-Driven Buffer Insertion via Feasible Shallow-Light Topology Reconstruction
Lin, Yingyan	T3R: Training-Free Two-Stage Token Refinement Towards Efficient and Robust VLA Models
Lin, Yong-Han	ThTrace: A High-Efficiency Displacement Field Simulator for Advanced Packaging
Lin, Zhuofan	Node Reduction via Targeted ODC-Based Wire Additions for AIG Optimization
Lin, Zhuoyi	CABAgent: A Cross-Stage Agentic Framework for Generating PDK-Compatible and Layout-Verified Analog Circuit Benchmarks
Ling, Xiang	Between The Cracks: Uncovering Illegal-Instruction Bugs in RISC-V Processors by Exploring the Unified Encoding Space WaveAce: Analyzing the Root Cause of SoC Test Failures via LLMs' Direct Waveform Inspection
Ling, Zichao	FADiff: Fusion-Aware Differentiable Optimization for DNN Scheduling on Tensor Accelerators UACC: A Chiplet-Based Auxiliary Cache for Cost-Effective Performance Scaling in Multicore Processors
Liu, Biao	NaCo3D: Native and Compact 3D Floorplanning via Reinforcement Learning
Liu, Bingyang	ARC: Any-Angle PCB Routing with Obstacle Avoidance under Complex Design Rules APPlace: Co-Optimizing Device Locations and Access Points for Routing-Aware Analog Placement
Liu, Bo	APRQ: Adaptive Prediction-Driven Residual Quantization Accelerator for Diffusion Transformers TriM: Efficient MoE Inference on Edge CPU-GPU Systems via Fused Quantization and Sensitivity-Guided Scheduling
Liu, Bo	A XNOR-SRAM-Based Computing-in-Memory Macro for Memory-Augmented Neural Networks RACE-FFN: Runtime-Adaptive Co-Execution in a Heterogeneous SA-CIM Architecture for Efficient MoE-FFN Acceleration
Liu, Chang	CertIR: Certified Static IR-Drop Estimation with Physics-Anchored Neural Correction
Liu, Chang	Less is More: KV Cache Scheduling for Bandwidth-Efficient LLM Inference on FPGA Speculate, Verify, Repeat: Faster Decoding via Speculative KV Access and Verification Feedback
Liu, Chengjie	Archive-Guided MOEA/D for Constrained Many-Objective Analog Circuit Sizing CktHVR: A Convergence-Aware GNN-VLM Hypothesize-Verify-Refine Framework for Analog Circuit Topology Rectification
Liu, Chien-Nan	Network Flow Guided Routing and Force Directed Offset Via Placement for Advanced Chiplet Interconnect MIBIFI: Differentiable Electronic–Photonic–Thermal Co-Simulation for Co-Packaged Optics Designs
Liu, Cong	PP2Tree: Learning-Guided Frontier Partitioning for Scalable Parallel Logic Synthesis
Liu, Dong	Less is More: KV Cache Scheduling for Bandwidth-Efficient LLM Inference on FPGA Speculate, Verify, Repeat: Faster Decoding via Speculative KV Access and Verification Feedback
Liu, Fangxin	MARCO: Markov Decision-based Adaptive Path Selection for Dynamic Layer Skipping
Liu, Fangzhou	Logic Resynthesis for Cross-Die Dependencies in Hybrid Bonded 3D ICs
Liu, Genggeng	A HeteroGNN-Based Hierarchical Co-Optimization Framework for Floorplanning and Routing in Advanced Packaging AnchorGNN: Cross-PVT Corner Timing Prediction via Anchor-Guided Graph Learning and STA-Aware Propagation
Liu, Haichuan	RAPID: An Efficient and Accurate Ratio-Based Analytical Proxy for Interconnect Delay PACT: A Runtime Contract for Sparse-Topology Updates in GPU-Accelerated Timing ECOs
Liu, Han	DREAM:3D-stacked Token-wise Caching Diffusion Accelerator with Resource-Aware Mapping
Liu, Haobo	NOVA-CIM: Noise- and Correlation-Tolerant Stochastic Interfaces for Analog Compute-in-Memory
Liu, Hongyuan	RT-DRC: Accelerating Design Rule Checking Using GPU Ray-Tracing Cores
Liu, Jiaheng	Enabling Efficient Quantized LLM Inference on Floating-Point CGRAs via Lightweight Integer Extensions
Liu, Jiaqi	MaxIM: A Plug-and-Play Maxwellian Engine via Interface Modification for Thick-Mask Lithography MAGI-OPC: Manhattan Area–Edge Learning Guided by High-Quality ILT for Optical Proximity Correction
Liu, Jiawei	Logic Resynthesis for Cross-Die Dependencies in Hybrid Bonded 3D ICs
Liu, Jincheng	Towards Leveraging the Software Ecosystem to Facilitate Hardware Verification
Liu, Meng	RobotCFU: A Tightly Coupled Multi-Operator CFU for Embedded RISC-V Robot Control
Liu, Qiang	Reasoning and Modeling of Instruction Corruption of MCU under EMFI
Liu, Qunyou	HAVEN: High-Bandwidth Flash Augmented Vector ENgine for Large-Scale Approximate Nearest-Neighbor Search Acceleration
Liu, Runsheng	Cross-Family Graph Learning for Sparse Aging-Aware Timing Characterization of Standard-Cell Libraries
Liu, Shang	RAP: Resource‑Aware Scheduling for GPU Accelerated Hypergraph Partitioning HLSClaw: Bringing Vibe Coding to High-Level Synthesis through Skill-Based Agentic Harness UnifyPower: A Unified Framework of Architecture-Level Power Model for Processors
Liu, Shukai	MAESTRO: Memo-Augmented Multi-Agent Engine for Self-Testing RTL Code Generation with Resource Orchestration
Liu, Siting	MoL-PAM: Joint P/G TSV Planning and Macro Refinement for Memory-on-Logic 3D ICs via a Benders-Type Decomposition Heuristic
Liu, Siting	REASON: RNG-Aware Finite-State Machines for Hardware-Realistic Stochastic Nonlinear Approximation
Liu, Tianji	GARDEN: GPU-Accelerated Rapid Divisor Extraction Fast Delay-oriented Logic Optimization with Parallel SOP Generation
Liu, Weiqiang	Low-Power Approximate MRAM CAM with Dynamic-Reference for HDC Associative Search MATE: Model-Assisted Trade-off Exploration for Quality-Aware Approximate Matrix Computing A Lightweight Microring-Resonator PUF Design for Silicon Photonics Transceivers
Liu, Xiaohan	Atomic and Hierarchy-Safe Cross-Module Undo/Redo for Analog IC Design
Liu, Yanfang	HOIST: A High-Order Interaction Surrogate for Sample-Efficient High-Sigma Yield Estimation in High-Dimensional Circuits
Liu, Yang	Multi-modal LLM-Driven Generation of Processor Performance Simulators from Datasheet Specifications
Liu, Yi	CCPart: Timing-Aware Multi-Level Partitioning for Multi-FPGA Systems with Incremental Timing Analysis
Liu, Yi	HINT: Toward an Executable Hardware-Intent Intermediate Representation Layer for LLM-Driven RTL Generation
Liu, Yi-Chih	Physics-Informed Generative Model Based Aging Library Characterization
Liu, Yijin	AX-AGENT: Contract-Driven Closed-Loop Framework for Error-Bounded PPA-Aware Approximate RTL Generation
Liu, Yikai	A Two Stage Learning-Based Thermal-Aware Framework for 3D Fixed-Outline Soft-Module Floorplanning across Chip Sizes
Liu, Yixin	LU-Evolve: Agent-Based Algorithm Exploration for Sparse LU Solvers
Liu, Yongpan	SSR-VAR: Exploiting Spatial- and Scale-aware Redundancy for Lightweight Inference of Visual Autoregressive Models 3DToMe: A Morton-Local and Interaction-Aware Token-Merging Accelerator for Efficient 3D Diffusion Policy Inference
Liu, Yuejun	TraceMorph: Real-Trace-Guided Execution-Level Obfuscation for RAPL-Based DNN Architecture Protection
Liu, Zhengwu	Weight-Stationary Fault Recovery via Neuron Tuning in RRAM-Based CIM Neuromorphic Accelerators NOVA-CIM: Noise- and Correlation-Tolerant Stochastic Interfaces for Analog Compute-in-Memory
Liu, Zhengyan	Reasoning and Modeling of Instruction Corruption of MCU under EMFI
Liu, Zhuohua	SRAM Bitcell-Peripheral Co-Optimization Under Array-Level Yield Constraints
Liu, Ziyu	Fanout-Multiplicity-Aware Technology Mapping for Multi-Output Superconducting Logic qLevelPlace: A Level-Based Placement Framework for RSFQ Circuits
Lo, Shao-Yu	Encoding Symmetries into Operator Learning: Towards Accurate Multi-Physics Simulation in Advanced Packaging
Long, Xing	GLARE: Generalizable Large-scale Analog Sizing via Reinforcement Learning with Covariance-Guided Exploration
Lou, Xin	Hit-SME: A High-throughput Hybrid SNN-based MLP Engine for Neural Volume Rendering
Lu, Hang	MinVNS: Minimal Virtual Network Separation for Deadlock Avoidance in Modular Network-on-Chip
Lu, Hao	EMPUF: A Leakage-Controlled Pre-Fabrication Benchmark for PCB Spectral Fingerprints
Lu, Haodong	DSEAgent: Agentic AI Accelerator Design Space Exploration via Expert-level Reinforcement Learning
Lu, Jia-En	A Consensus-Optimization Framework for Progressive Clearance-Aware PCB Legalization with Irregular Components
Lu, Qianlin	PDN-Aware Graph Transformer-based Dynamic IR Drop Prediction with Criticality-Guided Subgraph Construction
Lu, Tsung-Han	GenMLIR: An MLIR Compiler for Dynamic Programming Workloads on Tier-Aware 3D-DRAM PIM
Lu, Yao	SiliDiff: Post-Silicon Thermal and Power Reconstruction from Sparse Sensing with a Cascaded Conditional Diffusion Model UnifyPower: A Unified Framework of Architecture-Level Power Model for Processors
Lu, Yingming	STRIDE: Sparse Thermal Reconstruction-Informed Differential Encoding for Thermally Stable 3D-Integrated Analog CIM
Lu, Yuntao	MoL-PAM: Joint P/G TSV Planning and Macro Refinement for Memory-on-Logic 3D ICs via a Benders-Type Decomposition Heuristic
Lu, Zhonghai	RESCUE: Runtime Setup Resilience for TDM-Based Circuit-Switched NoCs QoS Analysis for UCIe-based Cross-die Communication using Network Calculus
Luo, Hao	Opening the Black Box: A Self-Correcting LLM Agent for EDA Toolchains Based on Source-Code Analysis
Luo, Huanlin	Efficient End-to-End Hyperprior-Based Learned Image Compression on Edge GPUs via Thread-Level Parallel Entropy Coding
Luo, Hui-Jie	Network Flow Guided Routing and Force Directed Offset Via Placement for Advanced Chiplet Interconnect
Luo, Junyi	CircuitsDNA: Discovering Unconventional Multi-Accuracy Arithmetic Circuits via Evolutionary Synthesis
Luo, Tianyue	Between The Cracks: Uncovering Illegal-Instruction Bugs in RISC-V Processors by Exploring the Unified Encoding Space WaveAce: Analyzing the Root Cause of SoC Test Failures via LLMs' Direct Waveform Inspection
Luo, Xudong	TraceMorph: Real-Trace-Guided Execution-Level Obfuscation for RAPL-Based DNN Architecture Protection
Lyu, Hao	WaveAce: Analyzing the Root Cause of SoC Test Failures via LLMs' Direct Waveform Inspection
Lyu, Lyu	Sample-Efficient Neural Compact Modeling for Design-Technology Co-Optimization Based on Process-Aware Adaptation
Lyu, Yongqiang	PARFuzzer: Path-Aware RTL Fuzzing with Controlled BTB Conflict Injection for Branch-Predictor Security Validation
Lyu, Yongxiang	SPICE: Speculative Prefetching with Low-Rank Expert Surrogates and Heterogeneous Orchestration for MoE Inference Acceleration
M
Ma, Guyu	Archive-Guided MOEA/D for Constrained Many-Objective Analog Circuit Sizing
Ma, Junhao	Topology as a Design Variable: Joint Architecture-Sizing Optimization for SRAM SRAM Bitcell-Peripheral Co-Optimization Under Array-Level Yield Constraints
Ma, Xunqi	Reasoning and Modeling of Instruction Corruption of MCU under EMFI
Ma, Yufei	HB-VGGT: Exploiting Head-Wise Complementary Redundancy for Efficient VGGT Inference on Hybrid-Bonded Architecture
Ma, Yuzhe	A Unified Framework for Circuit-Aware Tapped-Inductor Inverse Design with Topology-Aware Sequence Representation RT-DRC: Accelerating Design Rule Checking Using GPU Ray-Tracing Cores
Ma, Zihang	DSEAgent: Agentic AI Accelerator Design Space Exploration via Expert-level Reinforcement Learning
Mahmoud, Abdulqader	OMNI-DC: One-shot Multi-input Neural-Inference-Based Data Converter for Analog Computation-in-Memory
Mak, Wai-Kei	Placement Guidance Generation via Timing-Aware Hypergraph Partitioning and Multi-Criteria Cluster Selection
Malhotra, Akul	BLINK: Batch NormaLization-based INtegrity ChecKpoints for In-Situ Detection and Mitigation of Diverse Weight Corruptions in DNN Accelerators
Mangadahalli Siddaramu, Shanmukha	SURE-AI: Single-pass Uncertainty Estimation for Reliable Edge AI Accelerators
Manzano, Joseph	Memory-Aware Design-Space Exploration for Multi-Threaded HLS Accelerators
Mao, Yihan	UnO-NeSy: Optimizing Neuro-Symbolic Computing with Unified FeFET Based In-Memory System
Matsuo, Atsushi	Scalable Quantum Circuits Partitioning via Shortest-Path Search and Circuit Transformation Reducing T-depth in quantum circuits through adaptive allocation of ancillae between T-par and H-gadgets
Matsutani, Hiroki	Observability-Aware Runtime Reliability for MZI-Based Optical Neural Networks
Matus, Emil	Accelerating 5G NR Channel Estimation with a Complex-Arithmetic RISC-V Vector Extension
Meng, Chang	3D-Syn: 3D-aware Synthesis Flow for Heterogeneous LogicFolding 3D ICs
Meng, Xiaodong	ResistONet: Cascade Operator Network for Photoresist Simulation
Meschkov, Sergej	FlexRF: Retention-Aware Compilation for Low-power and Area-Efficient Flexible Microprocessors using IGZO DRAM-style Register File
Miao, Xiangshui	AHEAD: A Fast and Efficient MoE Speculative Decoding System via Dynamic Draft–Verify Coordination PSD-CIM:A Computing-In-Memory Attention Accelerator with Predictor-Free Sparsity search and Distribution Shaping
Miquel, Jonathan	SURE-AI: Single-pass Uncertainty Estimation for Reliable Edge AI Accelerators
Miskelly, Jack	Lightweight Key-Based Hardware Device-ID Authentication: A Reliable, ML-Resistant Alternative to PUFs
Misyats, Nazar	SWAPPER: Dynamic Operand Swapping in Non-commutative Approximate Circuits for Online Error Reduction
Mitake, Yuta	TRAIT: Trajectory-based Robust Aging-aware Chip Identification for Traceability
Mondelli, Andrea	UnifyPower: A Unified Framework of Architecture-Level Power Model for Processors
Moore, James	Lightweight Key-Based Hardware Device-ID Authentication: A Reliable, ML-Resistant Alternative to PUFs Power and EM Side-Channel Leakage Mitigation in Oscillator-Based PUFs via Sampling Techniques
Morsali, Melika	SLED-IFV: Solver-Validated LLM-Guided Decomposition for Scalable Hardware Information-Flow Verification
Mu, Pengyu	Q-COMPASS: A Circuit-Calibrated Simulation Framework for QDI NoC Architecture Exploration
Mueller-Gritschneder, Daniel	MAP-DSE: A Fast Performance Simulator for Large-Scale Microarchitectural Design Space Exploration Multi-modal LLM-Driven Generation of Processor Performance Simulators from Datasheet Specifications
Mukim, Prashansa	FUSE: Five-Block MVM Energy Comparison
N
Naeemi, Azad	Cross-Layer Co-Designed In-Memory Hyperdimensional Computing Accelerator for Proteomics at the Edge
Nakamura, Hiroshi	Resource-Efficient Heterogeneous CGRA for Kernels with Control Flow
Nan, Tianxiang	From Isolate to Co-Deployment Risk: Coupling-Aware Mapping for ACIM-Digital AI Accelerator Device-Circuit Co-Optimization of SOT-MRAM with Accurate PPA Evaluation for Edge AI Training
Nashimoto, Shoei	Staggered Instruction-Fetch Duplication: A Lightweight Processor-Level Countermeasure Against Fault Injection
Naviner, Lirida	ALTO: Joint Track-Height and Placement Optimization for Non-Integer Mixed-Cell-Height Designs
Nayan, Md Mizanur Rahaman	Cross-Layer Co-Designed In-Memory Hyperdimensional Computing Accelerator for Proteomics at the Edge
Neu, Marc	CHAIDO: Open-Source Simulation-Based Fault Injection for the AMD Versal AI Engine
Ng, Yin Cheang	VoxPMC: A Fast Voxel-Based Particle Monte Carlo Simulator for Feature-Scale Process Topography Simulation
Ni, Zhaojun	REASON: RNG-Aware Finite-State Machines for Hardware-Realistic Stochastic Nonlinear Approximation
Ning, Zhiyuan	ABNAT: Attention-Based Noise-Aware Training for Robust Transformers on Analog Compute-in-Memory Systems
Nishi, Yoshi	SCALE: Self-Supervised Constraint-Aware Layout Generation for Local P&R DRV Fixing at Advanced Nodes
Nunez-Yanez, Jose	ACCORD-IC: Contract-Checked Relation Transactions for Low-Bit Dynamic CNN–GNN Inference
O
O'Neill, Maire	Lightweight Key-Based Hardware Device-ID Authentication: A Reliable, ML-Resistant Alternative to PUFs Power and EM Side-Channel Leakage Mitigation in Oscillator-Based PUFs via Sampling Techniques
Oh, Jaeyun	CalNet: Temperature-Robust ADC Calibration via Learned BGR Behavior and LUT Correction
Ortega, Eduardo	Chiplet Assembly and Pre-Bond Qualification Planning for Heterogeneous Integrated Systems
Ouyang, Zhuoli	GLARE: Generalizable Large-scale Analog Sizing via Reinforcement Learning with Covariance-Guided Exploration
P
Pal, Saptadeep	A Waferscale Memory Architecture for Efficient LLM Inference
Palacios Almendros, Pedro	CCD-KV: Exploiting High-Density 3D Charge-Coupled Device Memory for Efficient On-Device LLM KV Caches
Palomero Bernardo, Paul	Compiler-driven Generation of Domain-Specific AI Hardware Accelerators for Edge Devices
Pan, David	CONTOUR: Continuous Topology Search for System-Level RFICs via Bi-Level Optimization and Neural-Analytical Co-Modeling ARC: Any-Angle PCB Routing with Obstacle Avoidance under Complex Design Rules APPlace: Co-Optimizing Device Locations and Access Points for Routing-Aware Analog Placement
Pan, Gung-Yu	Spec2Plan: An LLM-Powered Framework for Comprehensive Verification Plan Generation
Pan, Hong	VoxPMC: A Fast Voxel-Based Particle Monte Carlo Simulator for Feature-Scale Process Topography Simulation
Pan, Jiayi	MTPMoE: Exploiting Activation Skewness in Single-GPU MoE Multi-Token Prediction via Parallel Dense-Sparse Computing
Pan, Queran	LUMEN: A Compressed-LUT-based Processing-Near-Memory Architecture for Efficient LLM Inference at the Edge ACED: An Algorithm–Hardware Co-Designed VLA Accelerator Exploiting Dynamic Weight-Precision Switching ActRAM: A Hybrid Analog/Digital Action-Expert Accelerator Architecture for Vision-Language-Action Models
Pan, Yue	KV3D: KV Cache-Centric Monolithic 3D-Stackable DRAM-Based Accelerator for LLM Serving
Pandey, Nilesh Prasad	NgramRL: Accelerating RL Post-Training for Structured Generation via Rollout-Aware N-gram Speculative Decoding
Pao, Hsun-Wei	A Dual-Branch GAT-MLP Framework for Efficient Bump-Level Dynamic IR Drop Prediction in Flip-Chip Packages
Paraskevas, Foivos	CHAIDO: Open-Source Simulation-Based Fault Injection for the AMD Versal AI Engine
Parhi, Keshab	DRS: Unified Fully Homomorphic Encryption Hardware Accelerator with Scheme-Switching
Park, Geonhyeong	A Comprehensive Clock Tree Synthesis with Useful Skew for 3D ICs
Park, Heechun	DiffTherm: A Differentiable Thermal Formulation for Cell-Via Co-Optimization in 3D ICs Thermal-Aware Chiplet Placement and Shape Co-Optimization under D2D Interconnect Constraints for 2.5D Integration Wirelength-Driven Mixed-Cell-Height Detailed Placement with Multi-Row Cell Relocation Power Network Topology Optimization for Top Dies in Backside-Powered F2F 3D ICs A Comprehensive Clock Tree Synthesis with Useful Skew for 3D ICs Placement-Aware Logic Resynthesis with Cooperative Multi-Agent Reinforcement Learning
Park, Hyungjoo	An Explainable Analog/Mixed-Signal Routing Agent using Deterministic Constraint-Conflict Diagnosis
Park, Jaewoo	DRAC: A Static Analysis for DRAM Row Activation Count Toward Efficient Processing-in-Memory Code Generation
Park, Jangseon	NgramRL: Accelerating RL Post-Training for Structured Generation via Rollout-Aware N-gram Speculative Decoding
Park, Jia	IMPACT: IoT SNN Inference with a Metadata-Guided Pulse-Width Control Architecture for Conductance-Time Weight Representation in RRAM
Park, Jongsun	TempoGS: Temporal Binning and Expiration-Aware Gaussian Loading for Memory-Efficient 4D Gaussian Splatting Acceleration
Park, Joonyong	PaFeDSE: Pareto-Feedback-Guided Microarchitecture Design Space Exploration for Efficient Pareto Search
Park, Min Gyu	Grad-BSS: Differentiable Optimization for Full-Stack Backside Signal Routing
Passow, Micheal	Online Open-World Wafer Defect Discovery using Hyperdimensional Computing
Pedram, Massoud	Fanout-Multiplicity-Aware Technology Mapping for Multi-Output Superconducting Logic qLevelPlace: A Level-Based Placement Framework for RSFQ Circuits
Pei, Chunyan	CCPart: Timing-Aware Multi-Level Partitioning for Multi-FPGA Systems with Incremental Timing Analysis Timing-Aware Routing and Heterogeneous TDM Assignment for Multi-Level FPGA-Based Emulation Systems
Pei, Zehua	VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts
Pena Trevino, Luis Humberto	ALTO: Joint Track-Height and Placement Optimization for Non-Integer Mixed-Cell-Height Designs
Peng, Shichen	Declared Event Semantics: Cross-Layer Memory-Hierarchy Co-Design for Latency-Critical Systems
Peng, Tien-Hsin	A Dual-Branch GAT-MLP Framework for Efficient Bump-Level Dynamic IR Drop Prediction in Flip-Chip Packages
Peng, Zebo	Progressive Computation Scheduling for Deadline-Critical Tasks in Hierarchical Edge Networks
Peón-Quirós, Miguel	From Compiler to Silicon: A Co-Design Approach to High-Performance CGRAs
Pinge, Sumukh	Cross-Layer Co-Designed In-Memory Hyperdimensional Computing Accelerator for Proteomics at the Edge
Poddar, Souradip	APPlace: Co-Optimizing Device Locations and Access Points for Routing-Aware Analog Placement
Poddar, Vivan	ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Exploration
Pomante, Luigi	A Minimal MMU for Memory Virtualization on Microcontrollers for time-sensitive applications
Ponzina, Flavio	Cross-Layer Co-Designed In-Memory Hyperdimensional Computing Accelerator for Proteomics at the Edge
Prenat, Guillaume	SURE-AI: Single-pass Uncertainty Estimation for Reliable Edge AI Accelerators
Pu, Yuan	FormalPCell: Formal DRC Verification of Parameterized Layout Cells via Symbolic Interpretation and SMT Solving
Pudukotai Dinakarrao, Sai Manoj	ML-AccelBench: A Benchmark for Evaluating LLM-Based ML Accelerator RTL Generation
Q
Qi, Benyang	GAS: GPU Accelerated Schema Aware Exact Subcircuit Matching for Large-Scale Circuits
Qi, Ruichen	CircuitsDNA: Discovering Unconventional Multi-Accuracy Arithmetic Circuits via Evolutionary Synthesis
Qi, Xiaojuan	Weight-Stationary Fault Recovery via Neuron Tuning in RRAM-Based CIM Neuromorphic Accelerators
Qi, Zanhe	Scalable Quantum Circuits Partitioning via Shortest-Path Search and Circuit Transformation Reducing T-depth in quantum circuits through adaptive allocation of ancillae between T-par and H-gadgets
Qian, He	LUMEN: A Compressed-LUT-based Processing-Near-Memory Architecture for Efficient LLM Inference at the Edge ACED: An Algorithm–Hardware Co-Designed VLA Accelerator Exploiting Dynamic Weight-Precision Switching ActRAM: A Hybrid Analog/Digital Action-Expert Accelerator Architecture for Vision-Language-Action Models
Qian, Weikang	3D-Syn: 3D-aware Synthesis Flow for Heterogeneous LogicFolding 3D ICs
Qian, Xilin	XCTS: Cross-Tier-Aware Differentiable Clock Tree Synthesis for 3D Integrated Circuits
Qian, Yu	CAS: A Ferroelectric Compute-in-Memory Annealer for Sparse Combinatorial Optimization Problems
Qiao, Ye	EdgeDAE: Acceleration of Diffusion Action Experts for Real-Time Physical AI with Tiny VLAs on Edge FPGA-GPU Systems
Qin, Qi	LUMEN: A Compressed-LUT-based Processing-Near-Memory Architecture for Efficient LLM Inference at the Edge ACED: An Algorithm–Hardware Co-Designed VLA Accelerator Exploiting Dynamic Weight-Precision Switching ActRAM: A Hybrid Analog/Digital Action-Expert Accelerator Architecture for Vision-Language-Action Models
Qin, Xian Rong	LMSACO: LLM-Guided Multi-Objective State-Adaptive Analog Circuit Sizing Optimization
Qin, Yuhan	FormalPCell: Formal DRC Verification of Parameterized Layout Cells via Symbolic Interpretation and SMT Solving
Qiu, Le	3DToMe: A Morton-Local and Interaction-Aware Token-Merging Accelerator for Efficient 3D Diffusion Policy Inference
Qiu, Rui	GA2-CT: GPU-Accelerated Genetic Algorithm for Low-Power Compression-Tree Rewiring
Qu, Yuwei	TensorLUT: Exact Batched RTL Simulation via ANF-Lifted Tensor-Core GEMM
Quan, Chenghao	DRAC: A Static Analysis for DRAM Row Activation Count Toward Efficient Processing-in-Memory Code Generation
R
Raghunathan, Anand	TADA: Technology Aware DNN Accelerator Performance and Energy Estimator
Rahman, Amaan	Grad-BSS: Differentiable Optimization for Full-Stack Backside Signal Routing
Rao, Jia	DISSECT: Cross-Family RTL Trojan Localization by Auditing Structural–Functional Disagreement
Rathore, Yashvardhan	BB8: Blocking Buffer for breaking head-of-line stalling in GPGPUs via Instruction Bypassing.
Razmkhah, Sasan	Fanout-Multiplicity-Aware Technology Mapping for Multi-Output Superconducting Logic qLevelPlace: A Level-Based Placement Framework for RSFQ Circuits
Rehman, Semeen	UniCASE: A Unified 16-bit Floating Point Format with Criticality-Aware Selective ECC for Efficient DNN Protection
Reiber, Moritz	Hardware-Retargetable Grammar-Based NAS from Declarative Device Specifications
Reibold, Johannes	SURE-AI: Single-pass Uncertainty Estimation for Reliable Edge AI Accelerators
Ren, Jiachen	ScaleLUT: A Fully-Parallel Configurable LUT-Based Accelerator for Real-Time Multi-Scale Super-Resolution
Ren, Jiachen	NOVA-CIM: Noise- and Correlation-Tolerant Stochastic Interfaces for Analog Compute-in-Memory
Ren, Shuo	AgenticPD: A Stage-Aware Agentic Framework for Closed-Loop Physical Design Optimization
Ren, Yuhao	From Communities to Coordinates: Hierarchical Clustering–Guided Placement for Large-Scale FPGAs
Riener, Heinz	Inverter Redistribution through Self-Dual and Self-Anti-Dual Function Transformation
Rodríguez Álvarez, Rubén	From Compiler to Silicon: A Co-Design Approach to High-Performance CGRAs
Rosing, Tajana	KV3D: KV Cache-Centric Monolithic 3D-Stackable DRAM-Based Accelerator for LLM Serving Cross-Layer Co-Designed In-Memory Hyperdimensional Computing Accelerator for Proteomics at the Edge NgramRL: Accelerating RL Post-Training for Structured Generation via Rollout-Aware N-gram Speculative Decoding GenMLIR: An MLIR Compiler for Dynamic Programming Workloads on Tier-Aware 3D-DRAM PIM Online Open-World Wafer Defect Discovery using Hyperdimensional Computing HAVEN: High-Bandwidth Flash Augmented Vector ENgine for Large-Scale Approximate Nearest-Neighbor Search Acceleration
Rostami, Mohamadreza	Secure Reconfiguration for Multi-Tenant FPGAs
Roy, Kaushik	TADA: Technology Aware DNN Accelerator Performance and Energy Estimator
Ru, Junjia	A Unified Framework for Circuit-Aware Tapped-Inductor Inverse Design with Topology-Aware Sequence Representation
Rui, Yibo	PDG-CORDIC: A Posit-Decode-Guided Low-Latency CORDIC for Activation Function
Rui, Zhiqing	WaveAce: Analyzing the Root Cause of SoC Test Failures via LLMs' Direct Waveform Inspection
S
Sabih, Muhammed	CoD-MiCo: Co-Design of Mixed-Compression RISC-V Extensions for Neural Networks on FPGAs
Sadadou, Kamel-Eddine	SURE-AI: Single-pass Uncertainty Estimation for Reliable Edge AI Accelerators
Sadeghi, Ahmad-Reza	Secure Reconfiguration for Multi-Tenant FPGAs
Saleem, Nimrah	SymbOperon: Composable and Cost-Efficient Symbolic Reasoning Operators for Neuro-Symbolic Edge Perception
Saligane, Mehdi	CircuitsDNA: Discovering Unconventional Multi-Accuracy Arithmetic Circuits via Evolutionary Synthesis
Sano, Kentaro	Enabling Efficient Quantized LLM Inference on Floating-Point CGRAs via Lightweight Integer Extensions
Santora, Alexander	Multi-Feature Demographic Decoupling via LPC Cross-Synthesis for Privacy-Preserving Audio Anonymization
Sapatnekar, Sachin S.	SiliDiff: Post-Silicon Thermal and Power Reconstruction from Sparse Sensing with a Cascaded Conditional Diffusion Model
Sapra, Dolly	SHARD: Sub-Transformer Harnessing for Adaptive Resource-Aware Deployment
Saravanan, Raghul	ML-AccelBench: A Benchmark for Evaluating LLM-Based ML Accelerator RTL Generation
Sassatelli, Gilles	GRACE: GRAph-based power Consumption Estimator with Parallel Switching Activity Propagation
Sato, Takashi	TRAIT: Trajectory-based Robust Aging-aware Chip Identification for Traceability
Sayyah Ensan, Sina	An In-situ Self Clock-Gated 7474 Style Scan-Mux-D Low Power Flip-Flop
Schlichtmann, Ulf	MemFLoRA: Memory-Floor LoRA for CNN Adaptation at the Edge MAP-DSE: A Fast Performance Simulator for Large-Scale Microarchitectural Design Space Exploration 3D-VASE: Volumetric-Aware Scalable and Efficient Multi-Layer Design Synthesis for 3D-Printed Microfluidics
Schmid, Patrick	Compiler-driven Generation of Domain-Specific AI Hardware Accelerators for Edge Devices
Selvam, Surya	TADA: Technology Aware DNN Accelerator Performance and Energy Estimator
Seo, Hyungjoo	CalNet: Temperature-Robust ADC Calibration via Learned BGR Behavior and LUT Correction
Seo, Jaemin	Phase-Aware Monte Carlo Tree Search with LLM-Guided Proposal for Multi-Objective Physical Design Tuning
Seo, Joonyoung	SpectraPlace2.5D: Thermal-aware Chiplet Placement via Topology-guided MILP and Spectral Thermal Modeling
Sesli, Batuhan	CoD-MiCo: Co-Design of Mixed-Compression RISC-V Extensions for Neural Networks on FPGAs
Shaji, Sandra	Grad-BSS: Differentiable Optimization for Full-Stack Backside Signal Routing
Shamsi, Kaveh	Cube-based Finite-State-Machine Extraction via SAT Generalizations
Shang, Ninghui	HB-VGGT: Exploiting Head-Wise Complementary Redundancy for Efficient VGGT Inference on Hybrid-Bonded Architecture
Shanmukhi, Ganesh Sai	BB8: Blocking Buffer for breaking head-of-line stalling in GPGPUs via Instruction Bypassing.
Shao, Hanyong	ABNAT: Attention-Based Noise-Aware Training for Robust Transformers on Analog Compute-in-Memory Systems
Shao, Leilai	Sample-Efficient Neural Compact Modeling for Design-Technology Co-Optimization Based on Process-Aware Adaptation
Sharma, Tanvi	TADA: Technology Aware DNN Accelerator Performance and Energy Estimator
Shen, Cong	SiliDiff: Post-Silicon Thermal and Power Reconstruction from Sparse Sensing with a Cascaded Conditional Diffusion Model
Shen, Jiacheng	Sample-Efficient Neural Compact Modeling for Design-Technology Co-Optimization Based on Process-Aware Adaptation
Shen, Jian	Timing-Aware Routing and Heterogeneous TDM Assignment for Multi-Level FPGA-Based Emulation Systems
Shen, Libo	AgenticPD: A Stage-Aware Agentic Framework for Closed-Loop Physical Design Optimization
Shen, Linxiao	CRAFT: Constraint-Guided Region-Adaptive Search over Broad Design Spaces for High-Dimensional Analog Circuit Sizing
Shen, Shan	Topology as a Design Variable: Joint Architecture-Sizing Optimization for SRAM HGRP: Heterogeneous Graph Neural Network for Routability Prediction SRAM Bitcell-Peripheral Co-Optimization Under Array-Level Yield Constraints
Shen, Zhongkun	Low-Power Approximate MRAM CAM with Dynamic-Reference for HDC Associative Search A Reliability-Enhanced SOT-MTJ PUF with Obfuscated Write-Back for Physical-State Exposure Mitigation
Sheng, Yule	HGRP: Heterogeneous Graph Neural Network for Routability Prediction
Shi, Chenlin	Enabling Efficient Quantized LLM Inference on Floating-Point CGRAs via Lightweight Integer Extensions
Shi, Dandan	From DRAM Architecture to Protocol State: A Resource-Grounded Executable Semantics for LPDDR5
Shi, Junwei	LUMEN: A Compressed-LUT-based Processing-Near-Memory Architecture for Efficient LLM Inference at the Edge ACED: An Algorithm–Hardware Co-Designed VLA Accelerator Exploiting Dynamic Weight-Precision Switching ActRAM: A Hybrid Analog/Digital Action-Expert Accelerator Architecture for Vision-Language-Action Models
Shi, Kan	Towards Leveraging the Software Ecosystem to Facilitate Hardware Verification
Shi, Menghan	Reducing T-depth in quantum circuits through adaptive allocation of ancillae between T-par and H-gadgets
Shi, Wenqing	ScaleLUT: A Fully-Parallel Configurable LUT-Based Accelerator for Real-Time Multi-Scale Super-Resolution
Shi, Xizhe	Anonymous: A CPU-GPU Heterogeneous Engine for Glitch-Aware Time-Based Gate-Level Power Analysis Anonymous: Fast Clock-Aware Timing Propagation for Complex Clock Logic and Constraints with State Flow Graph Abstraction
Shi, Yifan	MoL-PAM: Joint P/G TSV Planning and Macro Refinement for Memory-on-Logic 3D ICs via a Benders-Type Decomposition Heuristic Obstacle-Aware Timing-Driven Buffer Insertion via Feasible Shallow-Light Topology Reconstruction
Shi, Zebin	SPLIT-MOR: Fast and Accurate Model Order Reduction for Nonlinear Transient Thermal Simulation of 2.5D/3D ICs
Shi, Zhengyuan	Adaptive BTOR2 Reformulation via Solver-Aware Equality Saturation HINT: Toward an Executable Hardware-Intent Intermediate Representation Layer for LLM-Driven RTL Generation
Shi, Zhiguo	UnO-NeSy: Optimizing Neuro-Symbolic Computing with Unified FeFET Based In-Memory System
Shih, Wei-Kai	Physics-Informed Generative Model Based Aging Library Characterization
Shin, Yeongbae	DRAC: A Static Analysis for DRAM Row Activation Count Toward Efficient Processing-in-Memory Code Generation
Shin, Youngsoo	Clock Distribution Network with Backside Clock Mesh in BSPDN Architecture
Shintani, Michihiro	TRAIT: Trajectory-based Robust Aging-aware Chip Identification for Traceability
Shulin, Zhu	MfSpGEMM: Merger-Free Row-Wise SpGEMM with Bitmap Accumulation and HBM-Aware Mapping
Siek, Liter	CABAgent: A Cross-Stage Agentic Framework for Generating PDK-Compatible and Layout-Verified Analog Circuit Benchmarks
Sinanoglu, Ozgur	Functional Retrieval for Resynthesis-Robust Hardware Trojan Detection in Gate-Level Netlists Functionality-Aware Is Not Synthesis-Invariant: An End-to-End Audit of Circuit-GNN Representations
Singh, Ankur	NVM-in-Cache: Repurposing Commodity 6T SRAM Cache into NVM Analog Processing-in-Memory Engine using a Novel Compute-on-Powerline Scheme
Singh, Nikhilesh	Secure Reconfiguration for Multi-Tenant FPGAs
Singh, Virendra	BB8: Blocking Buffer for breaking head-of-line stalling in GPGPUs via Instruction Bypassing.
Smith, Scott	Naviq: An Open-Source System-on-Chip Simulator for Rapid Prototyping, Verification, and Design Space Exploration
Somasekhar, Dinesh	An In-situ Self Clock-Gated 7474 Style Scan-Mux-D Low Power Flip-Flop
Song, Bingqian	From Isolate to Co-Deployment Risk: Coupling-Aware Mapping for ACIM-Digital AI Accelerator Device-Circuit Co-Optimization of SOT-MRAM with Accurate PPA Evaluation for Edge AI Training
Song, Fangyuan	Towards Leveraging the Software Ecosystem to Facilitate Hardware Verification
Song, Siwen	Timing-Aware Routing and Heterogeneous TDM Assignment for Multi-Level FPGA-Based Emulation Systems
Song, Sunghyun	Wirelength-Driven Mixed-Cell-Height Detailed Placement with Multi-Row Cell Relocation
Sotiropoulos, Georgios	CHAIDO: Open-Source Simulation-Based Fault Injection for the AMD Versal AI Engine
Spyrou, Theofilos	IMPACT: Constraint-Aware Search for Imperfectly Factorized Accelerator Mappings
Stan, Mircea	SLED-IFV: Solver-Validated LLM-Guided Decomposition for Scalable Hardware Information-Flow Verification
Stavrakakis, Dimitrios	IMPACT: Constraint-Aware Search for Imperfectly Factorized Accelerator Mappings
Stavrakakis, Konstantinos	IMPACT: Constraint-Aware Search for Imperfectly Factorized Accelerator Mappings
Sui, Tianle	Device-Circuit Co-Optimization of SOT-MRAM with Accurate PPA Evaluation for Edge AI Training
Sun, Baixi	FLARE: A Dataflow-Aware and Scalable Hardware Architecture for Neural-Hybrid Scientific Lossy Compression
Sun, Daying	HGRP: Heterogeneous Graph Neural Network for Routability Prediction
Sun, Hao	AHEAD: A Fast and Efficient MoE Speculative Decoding System via Dynamic Draft–Verify Coordination
Sun, Huajun	AHEAD: A Fast and Efficient MoE Speculative Decoding System via Dynamic Draft–Verify Coordination
Sun, Kaixuan	NaCo3D: Native and Compact 3D Floorplanning via Reinforcement Learning
Sun, Qi	CAS: A Ferroelectric Compute-in-Memory Annealer for Sparse Combinatorial Optimization Problems A DTCO-Oriented Early Digital Bring-Up Framework under Incomplete PDK and Standard-Cell Assets
Sun, Wenyu	3DToMe: A Morton-Local and Interaction-Aware Token-Merging Accelerator for Efficient 3D Diffusion Policy Inference
Sur-Kolay, Susmita	Multi-Output-Guided Transistor Network Synthesis and Layout for Sequential Cells
Sylvester, Dennis	CircuitsDNA: Discovering Unconventional Multi-Accuracy Arithmetic Circuits via Evolutionary Synthesis
T
Tahoori, Mehdi	FlexRF: Retention-Aware Compilation for Low-power and Area-Efficient Flexible Microprocessors using IGZO DRAM-style Register File SURE-AI: Single-pass Uncertainty Estimation for Reliable Edge AI Accelerators
Takase, Hideki	Resource-Efficient Heterogeneous CGRA for Kernels with Control Flow
Talukdar, Jonti	Chiplet Assembly and Pre-Bond Qualification Planning for Heterogeneous Integrated Systems
Tamamoto, Jion	Scalable Quantum Circuits Partitioning via Shortest-Path Search and Circuit Transformation
Tan, Benjamin	GREG: A Graphical Static Analysis Framework for Early Hardware Security Verification
Tan, Chaoliang	Weight-Stationary Fault Recovery via Neuron Tuning in RRAM-Based CIM Neuromorphic Accelerators
Tan, Zexu	Accelerating 5G NR Channel Estimation with a Complex-Arithmetic RISC-V Vector Extension
Tanaka, Tomonari	Fine-Grained Compiler-Assisted Hardening via Tolerant-Output Analysis for SDC–Runtime Trade-offs
Tang, Jianshi	From Isolate to Co-Deployment Risk: Coupling-Aware Mapping for ACIM-Digital AI Accelerator Device-Circuit Co-Optimization of SOT-MRAM with Accurate PPA Evaluation for Edge AI Training LUMEN: A Compressed-LUT-based Processing-Near-Memory Architecture for Efficient LLM Inference at the Edge ACED: An Algorithm–Hardware Co-Designed VLA Accelerator Exploiting Dynamic Weight-Precision Switching ActRAM: A Hybrid Analog/Digital Action-Expert Accelerator Architecture for Vision-Language-Action Models
Tang, Jie	From DRAM Architecture to Protocol State: A Resource-Grounded Executable Semantics for LPDDR5
Tang, Kechao	ABNAT: Attention-Based Noise-Aware Training for Robust Transformers on Analog Compute-in-Memory Systems NANQ: Noise-Aware Mixed-Precision Non-Uniform Quantization for Neural Networks on Analog Compute-in-Memory NOVA-CIM: Noise- and Correlation-Tolerant Stochastic Interfaces for Analog Compute-in-Memory
Tang, Ruiqi	Declared Event Semantics: Cross-Layer Memory-Hierarchy Co-Design for Latency-Critical Systems
Tang, Shengnan	VoxPMC: A Fast Voxel-Based Particle Monte Carlo Simulator for Feature-Scale Process Topography Simulation
Tang, Yawei	A Reliability-Enhanced SOT-MTJ PUF with Obfuscated Write-Back for Physical-State Exposure Mitigation
Tang, Zhexiang	AccTTS: Characterizing and Optimizing Workload Dynamics in Test-Time Scaling
Teich, Jürgen	CoD-MiCo: Co-Design of Mixed-Compression RISC-V Extensions for Neural Networks on FPGAs
Teng, Xiaopeng	Progressive Computation Scheduling for Deadline-Critical Tasks in Hierarchical Edge Networks
Thangellamudi, Jayanth	ML-AccelBench: A Benchmark for Evaluating LLM-Based ML Accelerator RTL Generation
Tian, Jiannan	FLARE: A Dataflow-Aware and Scalable Hardware Architecture for Neural-Hybrid Scientific Lossy Compression
Tian, Kanglin	Thermal-Aware Chiplet Placement Integrating Evolutionary Reinforcement Learning and Monte Carlo Tree Search Opening the Black Box: A Self-Correcting LLM Agent for EDA Toolchains Based on Source-Code Analysis
Tian, Wanting	AgenticPD: A Stage-Aware Agentic Framework for Closed-Loop Physical Design Optimization
Tong, Shengbo	CCPart: Timing-Aware Multi-Level Partitioning for Multi-FPGA Systems with Incremental Timing Analysis
Traiola, Marcello	SWAPPER: Dynamic Operand Swapping in Non-commutative Approximate Circuits for Online Error Reduction
Tsaras, Dimitrios	DeepResub: Towards Learned Logic Optimization Operators PP2Tree: Learning-Guided Frontier Partitioning for Scalable Parallel Logic Synthesis
Tseng, Tsun-Ming	3D-VASE: Volumetric-Aware Scalable and Efficient Multi-Layer Design Synthesis for 3D-Printed Microfluidics
Tseng, Tzu-Wei	Spec2Plan: An LLM-Powered Framework for Comprehensive Verification Plan Generation
Tseng, Wei-Hsiang	Learning-Guided Adaptive Cell-Wise Optimization for Mixed-Size Global Placement
Tsou, Chien-Hao	A Consensus-Optimization Framework for Progressive Clearance-Aware PCB Legalization with Irregular Components
Tsui, Chi-Ying	Taming Irregular Sparsity with a Regular Systolic Array for Efficient DNN Training
Tu, Chen-Jui	Prefix-Branch Software Co-Design for Random Forest Acceleration on Embedded Hybrid TCAMs
Tu, Jindong	GAS: GPU Accelerated Schema Aware Exact Subcircuit Matching for Large-Scale Circuits
Tumeo, Antonino	Memory-Aware Design-Space Exploration for Multi-Threaded HLS Accelerators
Turner, Walker	SCALE: Self-Supervised Constraint-Aware Layout Generation for Local P&R DRV Fixing at Advanced Nodes
U
Utyanskiy, Dmitry	Accelerating 5G NR Channel Estimation with a Complex-Arithmetic RISC-V Vector Extension
V
Valente, Giacomo	A Minimal MMU for Memory Virtualization on Microcontrollers for time-sensitive applications
van der Wolf, Pieter	Accelerating 5G NR Channel Estimation with a Complex-Arithmetic RISC-V Vector Extension
Van Durme, Maxime	CABLE: A Cached Bidirectional and Multi-lane Item Memory\\for Efficient Hyperdimensional Computing
Vergos, Polykarpos	FlexRF: Retention-Aware Compilation for Low-power and Area-Efficient Flexible Microprocessors using IGZO DRAM-style Register File
Vergos, Theofanis	FlexRF: Retention-Aware Compilation for Low-power and Area-Efficient Flexible Microprocessors using IGZO DRAM-style Register File
Verhelst, Marian	CABLE: A Cached Bidirectional and Multi-lane Item Memory\\for Efficient Hyperdimensional Computing
Verhelst, Marian	MX-like Tensor Core for LLM Inference with NPU Integration via Hardware-Software Co-Design Exploration ARES: Adaptive Reasoning-Effort Steering for PPA- and Cost-Aware RTL Optimization with LLM Agents
W
Walter, Marcel	aigverse: A Unified Infrastructure for Machine Learning-Driven Logic Synthesis
Wan, Rui	DeferKV: Long-Context LLM Attention Acceleration with Per-Token Scale Folding and Bank-Local Softmax on PIM CRISP: Paged Sparse Attention on DRAM-PIM with Row-Band-Aware KV Allocation and Frame-Derived Addressing PowerPilot: Preserving Verified Progress in LLM-Based Power-Intent ECO Repair
Wan, Zhuoheng	DSEAgent: Agentic AI Accelerator Design Space Exploration via Expert-level Reinforcement Learning
Wang, Antian	DRS: Unified Fully Homomorphic Encryption Hardware Accelerator with Scheme-Switching
Wang, Bowen	CCD-KV: Exploiting High-Density 3D Charge-Coupled Device Memory for Efficient On-Device LLM KV Caches
Wang, Can	Topology as a Design Variable: Joint Architecture-Sizing Optimization for SRAM SRAM Bitcell-Peripheral Co-Optimization Under Array-Level Yield Constraints
Wang, Chao	AgenticPD: A Stage-Aware Agentic Framework for Closed-Loop Physical Design Optimization
Wang, Chenghua	A Lightweight Microring-Resonator PUF Design for Silicon Photonics Transceivers
Wang, Ching-Hung	Structure-Preserving Density Modeling for Electrostatics-Based Analytical Placement
Wang, Chun-Yao	A Dual-Branch GAT-MLP Framework for Efficient Bump-Level Dynamic IR Drop Prediction in Flip-Chip Packages
Wang, Cong	An Area-Efficient CIM-Based Ising Annealer with Folded Mapping and Cooling-Scheduled Parallel Swaps Strategy for Large-Scale Traveling Salesman Problem
Wang, Daoce	FLARE: A Dataflow-Aware and Scalable Hardware Architecture for Neural-Hybrid Scientific Lossy Compression
Wang, Ernest	Chiplet Assembly and Pre-Bond Qualification Planning for Heterogeneous Integrated Systems
Wang, Guangyao	NANQ: Noise-Aware Mixed-Precision Non-Uniform Quantization for Neural Networks on Analog Compute-in-Memory
Wang, Han	Weight-Stationary Fault Recovery via Neuron Tuning in RRAM-Based CIM Neuromorphic Accelerators
Wang, Han	AutoIsing: An Automated Compiler for Programmable Ising Machine
Wang, Hanzhen	MTPMoE: Exploiting Activation Skewness in Single-GPU MoE Multi-Token Prediction via Parallel Dense-Sparse Computing
Wang, Hao	From DRAM Architecture to Protocol State: A Resource-Grounded Executable Semantics for LPDDR5
Wang, Haoyu	An Efficient Layout Decomposition Framework via Unsatisfiable Core
Wang, Jen-Yi	ThTrace: A High-Efficiency Displacement Field Simulator for Advanced Packaging
Wang, Jiacheng	GLARE: Generalizable Large-scale Analog Sizing via Reinforcement Learning with Covariance-Guided Exploration
Wang, Jiageng	CABAgent: A Cross-Stage Agentic Framework for Generating PDK-Compatible and Layout-Verified Analog Circuit Benchmarks
Wang, Jian	Efficient End-to-End Hyperprior-Based Learned Image Compression on Edge GPUs via Thread-Level Parallel Entropy Coding
Wang, Jianfeng	Security-Aware Runtime Control for Mitigating Token-Acceptance Side Channels in PIM/3D-Memory Speculative LLM Inference Architectures
Wang, Jianghan	GLARE: Generalizable Large-scale Analog Sizing via Reinforcement Learning with Covariance-Guided Exploration
Wang, Jing	ChronosDSE: Stability-Aware Design Space Exploration for GPGPUs
Wang, Jingren	Inverter Redistribution through Self-Dual and Self-Anti-Dual Function Transformation
Wang, Junjie	MARCO: Markov Decision-based Adaptive Path Selection for Dynamic Layer Skipping
Wang, Junyue	Towards Leveraging the Software Ecosystem to Facilitate Hardware Verification
Wang, Kaiqi	Device-Circuit Co-Optimization of SOT-MRAM with Accurate PPA Evaluation for Edge AI Training
Wang, Kun	CertIR: Certified Static IR-Drop Estimation with Physics-Anchored Neural Correction
Wang, Kun	When Fuzzing Meets Understanding: LLM-Driven Semantic Test Generation for RTL Verification
Wang, Kun	DSEAgent: Agentic AI Accelerator Design Space Exploration via Expert-level Reinforcement Learning
Wang, Lingli	TensorLUT: Exact Batched RTL Simulation via ANF-Lifted Tensor-Core GEMM Formally Verified Contract-Aware Replacement of Ready/Valid Microarchitectures CoSim: A Cross-Layer Simulation Framework for System-Hardware Co-Design of LLM Inference
Wang, Liping	MATE: Model-Assisted Trade-off Exploration for Quality-Aware Approximate Matrix Computing
Wang, Liuke	MaxIM: A Plug-and-Play Maxwellian Engine via Interface Modification for Thick-Mask Lithography
Wang, Mingjun	HOIST: A High-Order Interaction Surrogate for Sample-Efficient High-Sigma Yield Estimation in High-Dimensional Circuits Logic Resynthesis for Cross-Die Dependencies in Hybrid Bonded 3D ICs
Wang, Qianxu	DREAM:3D-stacked Token-wise Caching Diffusion Accelerator with Resource-Aware Mapping ATLAS: A Thermal-Aware 3D-Stacked Heterogeneous Architecture For LLM Multi-Turn Dialogue Serving
Wang, Rongfang	FlowMapper: Detection-Guided Topology Reconstruction of Circuit Block Diagrams
Wang, Rui	CCPart: Timing-Aware Multi-Level Partitioning for Multi-FPGA Systems with Incremental Timing Analysis
Wang, Runsheng	SPLIT-MOR: Fast and Accurate Model Order Reduction for Nonlinear Transient Thermal Simulation of 2.5D/3D ICs CRAFT: Constraint-Guided Region-Adaptive Search over Broad Design Spaces for High-Dimensional Analog Circuit Sizing RAPID: An Efficient and Accurate Ratio-Based Analytical Proxy for Interconnect Delay Anonymous: A CPU-GPU Heterogeneous Engine for Glitch-Aware Time-Based Gate-Level Power Analysis Anonymous: Fast Clock-Aware Timing Propagation for Complex Clock Logic and Constraints with State Flow Graph Abstraction
Wang, Sa	Towards Leveraging the Software Ecosystem to Facilitate Hardware Verification
Wang, Saiya	InfoCIM: An Information-Theoretic Framework for Modeling and Design of Noise-Limited Analog CIM STRIDE: Sparse Thermal Reconstruction-Informed Differential Encoding for Thermally Stable 3D-Integrated Analog CIM NANQ: Noise-Aware Mixed-Precision Non-Uniform Quantization for Neural Networks on Analog Compute-in-Memory
Wang, Shao-Chen	Gradient-Guided Thermal-Aware Timing Robustness Optimization Under Temperature Inversion
Wang, Shizhang	A DTCO-Oriented Early Digital Bring-Up Framework under Incomplete PDK and Standard-Cell Assets
Wang, Shuoqiu	PDN-Aware Graph Transformer-based Dynamic IR Drop Prediction with Criticality-Guided Subgraph Construction
Wang, Ting-Chi	Placement Guidance Generation via Timing-Aware Hypergraph Partitioning and Multi-Criteria Cluster Selection
Wang, Weihao	RT-DRC: Accelerating Design Rule Checking Using GPU Ray-Tracing Cores
Wang, Xiangyu	EMPUF: A Leakage-Controlled Pre-Fabrication Benchmark for PCB Spectral Fingerprints
Wang, Xiaomeng	Taming Irregular Sparsity with a Regular Systolic Array for Efficient DNN Training
Wang, Ya	DFAC: Dataflow-Aided Intra-cluster Coalescer for AI Accelerators
Wang, Yang	TreePIM: A Heterogeneous Processing-in-Memory Architecture for Tree-based Speculative Decoding
Wang, Yihao	RobotCFU: A Tightly Coupled Multi-Operator CFU for Embedded RISC-V Robot Control
Wang, Yikai	SRAM Bitcell-Peripheral Co-Optimization Under Array-Level Yield Constraints
Wang, Yikai	Topology as a Design Variable: Joint Architecture-Sizing Optimization for SRAM
Wang, Yike	MATE: Model-Assisted Trade-off Exploration for Quality-Aware Approximate Matrix Computing
Wang, Ying	PI-Aware Co-Layer Signal Routing and Power Plane Synthesis for Chiplet Interposers When Fuzzing Meets Understanding: LLM-Driven Semantic Test Generation for RTL Verification
Wang, Yiqing	ResistONet: Cascade Operator Network for Photoresist Simulation Chain of SRAF Generation: A Large Reasoning Model for Sub-resolution Assist Features EtchMO: A Differentiable Etch Model for Mask Optimization
Wang, Yiwen	DeepResub: Towards Learned Logic Optimization Operators PP2Tree: Learning-Guided Frontier Partitioning for Scalable Parallel Logic Synthesis
Wang, Yu	DeferKV: Long-Context LLM Attention Acceleration with Per-Token Scale Folding and Bank-Local Softmax on PIM CRISP: Paged Sparse Attention on DRAM-PIM with Row-Band-Aware KV Allocation and Frame-Derived Addressing PowerPilot: Preserving Verified Progress in LLM-Based Power-Intent ECO Repair
Wang, Yu	RASP-LLM: Radiation-Aware Design-Space Exploration of Precision and Selective Protection for On-Orbit LLM Inference Cross-Bank ECC Strategy for LLM-Oriented Hybrid-Bonded 3D DRAM Architecture
Wang, Yujie	PI-Aware Co-Layer Signal Routing and Power Plane Synthesis for Chiplet Interposers
Wang, Yujin	SSR-VAR: Exploiting Spatial- and Scale-aware Redundancy for Lightweight Inference of Visual Autoregressive Models
Wang, Yusa	Nexus: Activity-Aware Capacity-Constrained Neuron Partitioning for Multicore SNN Accelerators
Wang, Yutong	REASON: RNG-Aware Finite-State Machines for Hardware-Realistic Stochastic Nonlinear Approximation
Wang, Yuxuan	From Compiler to Silicon: A Co-Design Approach to High-Performance CGRAs
Wang, Zhen	APRQ: Adaptive Prediction-Driven Residual Quantization Accelerator for Diffusion Transformers TriM: Efficient MoE Inference on Edge CPU-GPU Systems via Fused Quantization and Sensitivity-Guided Scheduling
Wang, Zhen	MAGI-OPC: Manhattan Area–Edge Learning Guided by High-Quality ILT for Optical Proximity Correction
Wang, Zheng	T3R: Training-Free Two-Stage Token Refinement Towards Efficient and Robust VLA Models
Wang, Zhenghua	Sample-Efficient Neural Compact Modeling for Design-Technology Co-Optimization Based on Process-Aware Adaptation
Wang, Zhenkai	RobotCFU: A Tightly Coupled Multi-Operator CFU for Embedded RISC-V Robot Control
Wang, Zhenrui	AccTTS: Characterizing and Optimizing Workload Dynamics in Test-Time Scaling
Wang, Zhiang	Learning-Augmented Multilevel Hypergraph Partitioning with Net-Level Cut Priors 3D-Syn: 3D-aware Synthesis Flow for Heterogeneous LogicFolding 3D ICs From Communities to Coordinates: Hierarchical Clustering–Guided Placement for Large-Scale FPGAs
Wang, Zhongrui	AutoIsing: An Automated Compiler for Programmable Ising Machine Weight-Stationary Fault Recovery via Neuron Tuning in RRAM-Based CIM Neuromorphic Accelerators
Wang, Zhuangfei	Anonymous: A CPU-GPU Heterogeneous Engine for Glitch-Aware Time-Based Gate-Level Power Analysis
Wang, Ziheng	GLARE: Generalizable Large-scale Analog Sizing via Reinforcement Learning with Covariance-Guided Exploration
Wang, Zimo	Enabling Energy-Efficient TinyML Inference via Fused Tensor Architecture
Wang, Ziyi	CCPart: Timing-Aware Multi-Level Partitioning for Multi-FPGA Systems with Incremental Timing Analysis
Wang, Ziyi	Learning-Augmented Multilevel Hypergraph Partitioning with Net-Level Cut Priors
Wang, Ziyu	RASP-LLM: Radiation-Aware Design-Space Exploration of Precision and Selective Protection for On-Orbit LLM Inference
Waris, Haroon	AX-AGENT: Contract-Driven Closed-Loop Framework for Error-Bounded PPA-Aware Approximate RTL Generation
Wei, Min	CertIR: Certified Static IR-Drop Estimation with Physics-Anchored Neural Correction
Wei, Xufeng	A DTCO-Oriented Early Digital Bring-Up Framework under Incomplete PDK and Standard-Cell Assets
Weng, Huiyao	CCPart: Timing-Aware Multi-Level Partitioning for Multi-FPGA Systems with Incremental Timing Analysis Timing-Aware Routing and Heterogeneous TDM Assignment for Multi-Level FPGA-Based Emulation Systems
Weng, Jian	TraceMorph: Real-Trace-Guided Execution-Level Obfuscation for RAPL-Based DNN Architecture Protection
Wille, Robert	aigverse: A Unified Infrastructure for Machine Learning-Driven Logic Synthesis
Wong, Kachun	TACO: Topology-Aware Compression via Hardware–Software Co-Design for Robust CiM-Accelerated Edge RAG Retrieval
Wong, Kwunhang	AutoIsing: An Automated Compiler for Programmable Ising Machine Weight-Stationary Fault Recovery via Neuron Tuning in RRAM-Based CIM Neuromorphic Accelerators
Wong, Ngai	ScaleLUT: A Fully-Parallel Configurable LUT-Based Accelerator for Real-Time Multi-Scale Super-Resolution ASSERT: Adaptive Stochastic Sampling for Robust Diffusion Models on Analog Compute-in-Memory Hardware NOVA-CIM: Noise- and Correlation-Tolerant Stochastic Interfaces for Analog Compute-in-Memory
Wong, Stephan	IMPACT: Constraint-Aware Search for Imperfectly Factorized Accelerator Mappings
Woo, Huijeong	CalNet: Temperature-Robust ADC Calibration via Learned BGR Behavior and LUT Correction
Wu, Bing-Yue	EvoDRC: A Self-Evolving Agentic Framework for Automated DRC Violation Repair
Wu, Guanghong	TreePIM: A Heterogeneous Processing-in-Memory Architecture for Tree-based Speculative Decoding
Wu, Han	GLARE: Generalizable Large-scale Analog Sizing via Reinforcement Learning with Covariance-Guided Exploration
Wu, Huaqiang	LUMEN: A Compressed-LUT-based Processing-Near-Memory Architecture for Efficient LLM Inference at the Edge ACED: An Algorithm–Hardware Co-Designed VLA Accelerator Exploiting Dynamic Weight-Precision Switching ActRAM: A Hybrid Analog/Digital Action-Expert Accelerator Architecture for Vision-Language-Action Models
Wu, Jingtai	LUMEN: A Compressed-LUT-based Processing-Near-Memory Architecture for Efficient LLM Inference at the Edge ACED: An Algorithm–Hardware Co-Designed VLA Accelerator Exploiting Dynamic Weight-Precision Switching ActRAM: A Hybrid Analog/Digital Action-Expert Accelerator Architecture for Vision-Language-Action Models
Wu, Jingzheng	Between The Cracks: Uncovering Illegal-Instruction Bugs in RISC-V Processors by Exploring the Unified Encoding Space WaveAce: Analyzing the Root Cause of SoC Test Failures via LLMs' Direct Waveform Inspection
Wu, Lichao	Secure Reconfiguration for Multi-Tenant FPGAs
Wu, Ming-Chen	A Dual-Branch GAT-MLP Framework for Efficient Bump-Level Dynamic IR Drop Prediction in Flip-Chip Packages
Wu, Qihang	VPR-Evolve: Multi-Agent-Driven Algorithm Evolution for FPGA Place and Route
Wu, Tongkai	GAS: GPU Accelerated Schema Aware Exact Subcircuit Matching for Large-Scale Circuits
Wu, Yiheng	SRAM Bitcell-Peripheral Co-Optimization Under Array-Level Yield Constraints
Wu, Yun	A Lightweight Microring-Resonator PUF Design for Silicon Photonics Transceivers
Wu, Zhen	A System-Level Typed-Graph Environment for Traceable Cycle-Level Co-Design of Heterogeneous AI Accelerators
X
Xi, Yuechen	RASP-LLM: Radiation-Aware Design-Space Exploration of Precision and Selective Protection for On-Orbit LLM Inference Cross-Bank ECC Strategy for LLM-Oriented Hybrid-Bonded 3D DRAM Architecture
Xia, Shouming	Atomic and Hierarchy-Safe Cross-Module Undo/Redo for Analog IC Design
Xia, Yang	EtchMO: A Differentiable Etch Model for Mask Optimization
Xia, Zihan	KV3D: KV Cache-Centric Monolithic 3D-Stackable DRAM-Based Accelerator for LLM Serving
Xiang, Meng	AX-AGENT: Contract-Driven Closed-Loop Framework for Error-Bounded PPA-Aware Approximate RTL Generation
Xiao, Cancheng	From Isolate to Co-Deployment Risk: Coupling-Aware Mapping for ACIM-Digital AI Accelerator Device-Circuit Co-Optimization of SOT-MRAM with Accurate PPA Evaluation for Edge AI Training
Xiao, Shanlin	Nexus: Activity-Aware Capacity-Constrained Neuron Partitioning for Multicore SNN Accelerators Q-COMPASS: A Circuit-Calibrated Simulation Framework for QDI NoC Architecture Exploration
Xiao, Weihua	CoEvoP&R: Co-Evolving Placement Objectives with Routing Feedback via Large Language Models
Xiao, Zixuan	TensorLUT: Exact Batched RTL Simulation via ANF-Lifted Tensor-Core GEMM
Xie, Baohui	GAS: GPU Accelerated Schema Aware Exact Subcircuit Matching for Large-Scale Circuits
Xie, Biwei	ChronosDSE: Stability-Aware Design Space Exploration for GPGPUs
Xie, Jiafeng	PFHE: Partial Fully Homomorphic Encryption on CNN Inference
Xie, Tongxin	Cross-Bank ECC Strategy for LLM-Oriented Hybrid-Bonded 3D DRAM Architecture
Xie, Xinzhe	CABAgent: A Cross-Stage Agentic Framework for Generating PDK-Compatible and Layout-Verified Analog Circuit Benchmarks
Xie, Yuan	Cross-Bank ECC Strategy for LLM-Oriented Hybrid-Bonded 3D DRAM Architecture
Xie, Yunlong	Towards Leveraging the Software Ecosystem to Facilitate Hardware Verification
Xie, Yuxin	InfoCIM: An Information-Theoretic Framework for Modeling and Design of Noise-Limited Analog CIM ASSERT: Adaptive Stochastic Sampling for Robust Diffusion Models on Analog Compute-in-Memory Hardware
Xie, Zhiyao	RAP: Resource‑Aware Scheduling for GPU Accelerated Hypergraph Partitioning DeepResub: Towards Learned Logic Optimization Operators UnifyPower: A Unified Framework of Architecture-Level Power Model for Processors PP2Tree: Learning-Guided Frontier Partitioning for Scalable Parallel Logic Synthesis
Xing, Tianyu	A DTCO-Oriented Early Digital Bring-Up Framework under Incomplete PDK and Standard-Cell Assets
Xing, Wei	Topology as a Design Variable: Joint Architecture-Sizing Optimization for SRAM SRAM Bitcell-Peripheral Co-Optimization Under Array-Level Yield Constraints
Xiong, Dongliang	Enabling Energy-Efficient TinyML Inference via Fused Tensor Architecture
Xiong, Shisheng	An Efficient Layout Decomposition Framework via Unsatisfiable Core
Xiong, Yizhe	RESCUE: Runtime Setup Resilience for TDM-Based Circuit-Switched NoCs
Xiong, Zhongru	HOIST: A High-Order Interaction Surrogate for Sample-Efficient High-Sigma Yield Estimation in High-Dimensional Circuits
Xu, Huiyao	CktHVR: A Convergence-Aware GNN-VLM Hypothesize-Verify-Refine Framework for Analog Circuit Topology Rectification
Xu, Jiahao	Obstacle-Aware Timing-Driven Buffer Insertion via Feasible Shallow-Light Topology Reconstruction
Xu, Jiaming	MTPMoE: Exploiting Activation Skewness in Single-GPU MoE Multi-Token Prediction via Parallel Dense-Sparse Computing
Xu, Jiang	HLSClaw: Bringing Vibe Coding to High-Level Synthesis through Skill-Based Agentic Harness
Xu, Ning	LMSACO: LLM-Guided Multi-Objective State-Adaptive Analog Circuit Sizing Optimization
Xu, Qiang	GA2-CT: GPU-Accelerated Genetic Algorithm for Low-Power Compression-Tree Rewiring Adaptive BTOR2 Reformulation via Solver-Aware Equality Saturation HINT: Toward an Executable Hardware-Intent Intermediate Representation Layer for LLM-Driven RTL Generation
Xu, Qimin	MAESTRO: Memo-Augmented Multi-Agent Engine for Self-Testing RTL Code Generation with Resource Orchestration
Xu, Songlin	SPGLA-Net: A Slotline-Aware Port-Graph Linear Attention Residual Network for Sub-THz On-Chip Passive Modeling
Xu, Weihong	HAVEN: High-Bandwidth Flash Augmented Vector ENgine for Large-Scale Approximate Nearest-Neighbor Search Acceleration
Xu, Wenbo	Chain of SRAF Generation: A Large Reasoning Model for Sub-resolution Assist Features
Xu, Xiaoquan	RACE-FFN: Runtime-Adaptive Co-Execution in a Heterogeneous SA-CIM Architecture for Efficient MoE-FFN Acceleration
Xu, Yiming	An Efficient Layout Decomposition Framework via Unsatisfiable Core
Xu, Yinan	MinVNS: Minimal Virtual Network Separation for Deadlock Avoidance in Modular Network-on-Chip
Xu, Zhili	Chain of SRAF Generation: A Large Reasoning Model for Sub-resolution Assist Features
Xuan, Zihao	AutoIsing: An Automated Compiler for Programmable Ising Machine
Xue, Zhibiao	A XNOR-SRAM-Based Computing-in-Memory Macro for Memory-Augmented Neural Networks RACE-FFN: Runtime-Adaptive Co-Execution in a Heterogeneous SA-CIM Architecture for Efficient MoE-FFN Acceleration
Y
Yamashita, Shigeru	Scalable Quantum Circuits Partitioning via Shortest-Path Search and Circuit Transformation Reducing T-depth in quantum circuits through adaptive allocation of ancillae between T-par and H-gadgets
Yan, Hao	HINT: Toward an Executable Hardware-Intent Intermediate Representation Layer for LLM-Driven RTL Generation
Yan, Shoumeng	Investigation of Karatsuba Algorithm for Large-Bitwidth Modular Multiplication
Yan, Wenbo	FlowMapper: Detection-Guided Topology Reconstruction of Circuit Block Diagrams
Yan, Zheyu	UnO-NeSy: Optimizing Neuro-Symbolic Computing with Unified FeFET Based In-Memory System TACO: Topology-Aware Compression via Hardware–Software Co-Design for Robust CiM-Accelerated Edge RAG Retrieval
Yang, Chen	QoS Analysis for UCIe-based Cross-die Communication using Network Calculus
Yang, Fan	LU-Evolve: Agent-Based Algorithm Exploration for Sparse LU Solvers
Yang, Haoyu	SCALE: Self-Supervised Constraint-Aware Layout Generation for Local P&R DRV Fixing at Advanced Nodes OptiClear: Differentiable Curvilinear Design Rule Legalization for Inverse-Designed Photonic Device EvoDRC: A Self-Evolving Agentic Framework for Automated DRC Violation Repair
Yang, Hongying	HB-VGGT: Exploiting Head-Wise Complementary Redundancy for Efficient VGGT Inference on Hybrid-Bonded Architecture
Yang, Huazhong	SSR-VAR: Exploiting Spatial- and Scale-aware Redundancy for Lightweight Inference of Visual Autoregressive Models Cross-Bank ECC Strategy for LLM-Oriented Hybrid-Bonded 3D DRAM Architecture Security-Aware Runtime Control for Mitigating Token-Acceptance Side Channels in PIM/3D-Memory Speculative LLM Inference Architectures
Yang, Jun	Archive-Guided MOEA/D for Constrained Many-Objective Analog Circuit Sizing CktHVR: A Convergence-Aware GNN-VLM Hypothesize-Verify-Refine Framework for Analog Circuit Topology Rectification
Yang, Ning	MARCO: Markov Decision-based Adaptive Path Selection for Dynamic Layer Skipping
Yang, Sejeong	PaFeDSE: Pareto-Feedback-Guided Microarchitecture Design Space Exploration for Efficient Pareto Search
Yang, Sijing	TensorLUT: Exact Batched RTL Simulation via ANF-Lifted Tensor-Core GEMM Formally Verified Contract-Aware Replacement of Ready/Valid Microarchitectures
Yang, Yi	MATE: Model-Assisted Trade-off Exploration for Quality-Aware Approximate Matrix Computing
Yang, Yuxiao	CAS: A Ferroelectric Compute-in-Memory Annealer for Sparse Combinatorial Optimization Problems UnO-NeSy: Optimizing Neuro-Symbolic Computing with Unified FeFET Based In-Memory System
Yang, Zechen	Towards Leveraging the Software Ecosystem to Facilitate Hardware Verification
Yang, Zehao	3D-Syn: 3D-aware Synthesis Flow for Heterogeneous LogicFolding 3D ICs
Yang, Zongxiao	SPGLA-Net: A Slotline-Aware Port-Graph Linear Attention Residual Network for Sub-THz On-Chip Passive Modeling
Yangu, Yangu	Weight-Stationary Fault Recovery via Neuron Tuning in RRAM-Based CIM Neuromorphic Accelerators
Yao, Haidong	DFAC: Dataflow-Aided Intra-cluster Coalescer for AI Accelerators
Yao, Jiayu	HB-VGGT: Exploiting Head-Wise Complementary Redundancy for Efficient VGGT Inference on Hybrid-Bonded Architecture
Yao, Lei-Han	A Resource-Efficient Quantum Circuit for Fixed-Point Logarithm Operations with Analytical Error Bounds
Yao, Peng	LUMEN: A Compressed-LUT-based Processing-Near-Memory Architecture for Efficient LLM Inference at the Edge ACED: An Algorithm–Hardware Co-Designed VLA Accelerator Exploiting Dynamic Weight-Precision Switching ActRAM: A Hybrid Analog/Digital Action-Expert Accelerator Architecture for Vision-Language-Action Models
Yao, Shenshuo	MaxIM: A Plug-and-Play Maxwellian Engine via Interface Modification for Thick-Mask Lithography
Yao, Wenshuai	InfoCIM: An Information-Theoretic Framework for Modeling and Design of Noise-Limited Analog CIM STRIDE: Sparse Thermal Reconstruction-Informed Differential Encoding for Thermally Stable 3D-Integrated Analog CIM ABNAT: Attention-Based Noise-Aware Training for Robust Transformers on Analog Compute-in-Memory Systems NANQ: Noise-Aware Mixed-Precision Non-Uniform Quantization for Neural Networks on Analog Compute-in-Memory ASSERT: Adaptive Stochastic Sampling for Robust Diffusion Models on Analog Compute-in-Memory Hardware NOVA-CIM: Noise- and Correlation-Tolerant Stochastic Interfaces for Analog Compute-in-Memory
Yao, Yizhou	STRIDE: Sparse Thermal Reconstruction-Informed Differential Encoding for Thermally Stable 3D-Integrated Analog CIM
Yao, Zhicheng	Towards Leveraging the Software Ecosystem to Facilitate Hardware Verification
Ye, Le	HB-VGGT: Exploiting Head-Wise Complementary Redundancy for Efficient VGGT Inference on Hybrid-Bonded Architecture
Ye, Xiaoyi	Investigation of Karatsuba Algorithm for Large-Bitwidth Modular Multiplication
Ye, Xinyu	ChronosDSE: Stability-Aware Design Space Exploration for GPGPUs
Ye, Zijian	Weight-Stationary Fault Recovery via Neuron Tuning in RRAM-Based CIM Neuromorphic Accelerators
Yeh, Che-Wu	Efficient Concurrent Die-to-Die Routing with Teardrop and Offset-Via Awareness
Yen, Pei-Yun	Spec2Plan: An LLM-Powered Framework for Comprehensive Verification Plan Generation
Yeo, Hyeon-Yeong	CONTOUR: Continuous Topology Search for System-Level RFICs via Bi-Level Optimization and Neural-Analytical Co-Modeling
Yi, Xiang	SPGLA-Net: A Slotline-Aware Port-Graph Linear Attention Residual Network for Sub-THz On-Chip Passive Modeling
Yi, Yongxian	Sample-Efficient Neural Compact Modeling for Design-Technology Co-Optimization Based on Process-Aware Adaptation
Yi, Zhou	MfSpGEMM: Merger-Free Row-Wise SpGEMM with Bitmap Accumulation and HBM-Aware Mapping
Yin, Jun	ARES: Adaptive Reasoning-Effort Steering for PPA- and Cost-Aware RTL Optimization with LLM Agents
Yin, Miao	FLARE: A Dataflow-Aware and Scalable Hardware Architecture for Neural-Hybrid Scientific Lossy Compression
Yin, Shicheng	CRAFT: Constraint-Guided Region-Adaptive Search over Broad Design Spaces for High-Dimensional Analog Circuit Sizing
Yin, Shouyi	TreePIM: A Heterogeneous Processing-in-Memory Architecture for Tree-based Speculative Decoding
Yin, Xunzhao	CAS: A Ferroelectric Compute-in-Memory Annealer for Sparse Combinatorial Optimization Problems UnO-NeSy: Optimizing Neuro-Symbolic Computing with Unified FeFET Based In-Memory System
Yin, Zihan	A Time-Encoded Analog Photonic Interposer for Energy-Efficient Integration of Analog Vision Sensors and Analog Accelerators
Yoon, Jongho	Phase-Aware Monte Carlo Tree Search with LLM-Guided Proposal for Multi-Objective Physical Design Tuning
Yoon, Junghyun	Thermal-Aware Chiplet Placement and Shape Co-Optimization under D2D Interconnect Constraints for 2.5D Integration
Young, Evangeline F.Y.	GARDEN: GPU-Accelerated Rapid Divisor Extraction Fast Delay-oriented Logic Optimization with Parallel SOP Generation
Yu, Bei	Thermal-Aware Chiplet Placement Integrating Evolutionary Reinforcement Learning and Monte Carlo Tree Search HOIST: A High-Order Interaction Surrogate for Sample-Efficient High-Sigma Yield Estimation in High-Dimensional Circuits AgenticPD: A Stage-Aware Agentic Framework for Closed-Loop Physical Design Optimization Learning-Augmented Multilevel Hypergraph Partitioning with Net-Level Cut Priors Chain of SRAF Generation: A Large Reasoning Model for Sub-resolution Assist Features FormalPCell: Formal DRC Verification of Parameterized Layout Cells via Symbolic Interpretation and SMT Solving Logic Resynthesis for Cross-Die Dependencies in Hybrid Bonded 3D ICs VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts MoL-PAM: Joint P/G TSV Planning and Macro Refinement for Memory-on-Logic 3D ICs via a Benders-Type Decomposition Heuristic FADiff: Fusion-Aware Differentiable Optimization for DNN Scheduling on Tensor Accelerators Obstacle-Aware Timing-Driven Buffer Insertion via Feasible Shallow-Light Topology Reconstruction
Yu, Cunxi	SCALE: Self-Supervised Constraint-Aware Layout Generation for Local P&R DRV Fixing at Advanced Nodes
Yu, Dunshan	ATLAS: A Thermal-Aware 3D-Stacked Heterogeneous Architecture For LLM Multi-Turn Dialogue Serving
Yu, Hao	ScaleLUT: A Fully-Parallel Configurable LUT-Based Accelerator for Real-Time Multi-Scale Super-Resolution
Yu, Hao	CONTOUR: Continuous Topology Search for System-Level RFICs via Bi-Level Optimization and Neural-Analytical Co-Modeling
Yu, Jingyi	MaxIM: A Plug-and-Play Maxwellian Engine via Interface Modification for Thick-Mask Lithography MAGI-OPC: Manhattan Area–Edge Learning Guided by High-Quality ILT for Optical Proximity Correction
Yu, Jinnuo	Enabling Energy-Efficient TinyML Inference via Fused Tensor Architecture
Yu, Minsang	GD-PIM: A Low-Cost Gustavson Dataflow-Based Processing-in-Memory Architecture for SpGEMM
Yu, Qiaoyan	Multi-Feature Demographic Decoupling via LPC Cross-Synthesis for Privacy-Preserving Audio Anonymization
Yu, Shimeng	HAVEN: High-Bandwidth Flash Augmented Vector ENgine for Large-Scale Approximate Nearest-Neighbor Search Acceleration
Yu, Wenjian	VoxPMC: A Fast Voxel-Based Particle Monte Carlo Simulator for Feature-Scale Process Topography Simulation CCPart: Timing-Aware Multi-Level Partitioning for Multi-FPGA Systems with Incremental Timing Analysis Timing-Aware Routing and Heterogeneous TDM Assignment for Multi-Level FPGA-Based Emulation Systems
Yu, Xuerui	Cross-Bank ECC Strategy for LLM-Oriented Hybrid-Bonded 3D DRAM Architecture
Yu, Yanxuan	Less is More: KV Cache Scheduling for Bandwidth-Efficient LLM Inference on FPGA Speculate, Verify, Repeat: Faster Decoding via Speculative KV Access and Verification Feedback
Yu, Zhiping	LUMEN: A Compressed-LUT-based Processing-Near-Memory Architecture for Efficient LLM Inference at the Edge ACED: An Algorithm–Hardware Co-Designed VLA Accelerator Exploiting Dynamic Weight-Precision Switching
Yu, Zhiyi	Nexus: Activity-Aware Capacity-Constrained Neuron Partitioning for Multicore SNN Accelerators Q-COMPASS: A Circuit-Calibrated Simulation Framework for QDI NoC Architecture Exploration
Yu, Ziyang	MaxIM: A Plug-and-Play Maxwellian Engine via Interface Modification for Thick-Mask Lithography Chain of SRAF Generation: A Large Reasoning Model for Sub-resolution Assist Features
Yuan, Bo	NaCo3D: Native and Compact 3D Floorplanning via Reinforcement Learning
Yuan, Bo	AccTTS: Characterizing and Optimizing Workload Dynamics in Test-Time Scaling
Yuan, Mingxuan	DeepResub: Towards Learned Logic Optimization Operators PP2Tree: Learning-Guided Frontier Partitioning for Scalable Parallel Logic Synthesis
Yuan, Yue	HGRP: Heterogeneous Graph Neural Network for Routability Prediction
Yuan, Zhechen	Hit-SME: A High-throughput Hybrid SNN-based MLP Engine for Neural Volume Rendering
Yucel, Abdulkadir C.	CABAgent: A Cross-Stage Agentic Framework for Generating PDK-Compatible and Layout-Verified Analog Circuit Benchmarks
Yue, Zhiheng	TreePIM: A Heterogeneous Processing-in-Memory Architecture for Tree-based Speculative Decoding
Z
Zang, Yuqian	ResistONet: Cascade Operator Network for Photoresist Simulation
Zeng, Ming	AHEAD: A Fast and Efficient MoE Speculative Decoding System via Dynamic Draft–Verify Coordination
Zeng, Shulin	DeferKV: Long-Context LLM Attention Acceleration with Per-Token Scale Folding and Bank-Local Softmax on PIM CRISP: Paged Sparse Attention on DRAM-PIM with Row-Band-Aware KV Allocation and Frame-Derived Addressing PowerPilot: Preserving Verified Progress in LLM-Based Power-Intent ECO Repair
Zeng, Xiaoyang	Declared Event Semantics: Cross-Layer Memory-Hierarchy Co-Design for Latency-Critical Systems
Zeng, Xuan	From Communities to Coordinates: Hierarchical Clustering–Guided Placement for Large-Scale FPGAs
Zervakis, Georgios	FlexRF: Retention-Aware Compilation for Low-power and Area-Efficient Flexible Microprocessors using IGZO DRAM-style Register File
Zhai, Jianwang	PARFuzzer: Path-Aware RTL Fuzzing with Controlled BTB Conflict Injection for Branch-Predictor Security Validation Thermal-Aware Chiplet Placement Integrating Evolutionary Reinforcement Learning and Monte Carlo Tree Search Opening the Black Box: A Self-Correcting LLM Agent for EDA Toolchains Based on Source-Code Analysis Timing-Aware Routing and Heterogeneous TDM Assignment for Multi-Level FPGA-Based Emulation Systems FADiff: Fusion-Aware Differentiable Optimization for DNN Scheduling on Tensor Accelerators UACC: A Chiplet-Based Auxiliary Cache for Cost-Effective Performance Scaling in Multicore Processors
Zhan, Wang	From DRAM Architecture to Protocol State: A Resource-Grounded Executable Semantics for LPDDR5
Zhang, Bailiang	PI-Aware Co-Layer Signal Routing and Power Plane Synthesis for Chiplet Interposers
Zhang, Bo	Investigation of Karatsuba Algorithm for Large-Bitwidth Modular Multiplication
Zhang, Bowen	PDN-Aware Graph Transformer-based Dynamic IR Drop Prediction with Criticality-Guided Subgraph Construction
Zhang, Boyuan	FLARE: A Dataflow-Aware and Scalable Hardware Architecture for Neural-Hybrid Scientific Lossy Compression
Zhang, David Wei	LU-Evolve: Agent-Based Algorithm Exploration for Sparse LU Solvers
Zhang, Han	XCTS: Cross-Tier-Aware Differentiable Clock Tree Synthesis for 3D Integrated Circuits
Zhang, Haoyi	CRAFT: Constraint-Guided Region-Adaptive Search over Broad Design Spaces for High-Dimensional Analog Circuit Sizing PACT: A Runtime Contract for Sparse-Topology Updates in GPU-Accelerated Timing ECOs
Zhang, Hongce	Inverter Redistribution through Self-Dual and Self-Anti-Dual Function Transformation
Zhang, Hongji	HINT: Toward an Executable Hardware-Intent Intermediate Representation Layer for LLM-Driven RTL Generation
Zhang, Jiajun	PDG-CORDIC: A Posit-Decode-Guided Low-Latency CORDIC for Activation Function
Zhang, Jiaqi	UnO-NeSy: Optimizing Neuro-Symbolic Computing with Unified FeFET Based In-Memory System
Zhang, Junming	AHEAD: A Fast and Efficient MoE Speculative Decoding System via Dynamic Draft–Verify Coordination
Zhang, Kaiyuan	DRS: Unified Fully Homomorphic Encryption Hardware Accelerator with Scheme-Switching
Zhang, Li	A DTCO-Oriented Early Digital Bring-Up Framework under Incomplete PDK and Standard-Cell Assets
Zhang, Mengyun	LUMEN: A Compressed-LUT-based Processing-Near-Memory Architecture for Efficient LLM Inference at the Edge ACED: An Algorithm–Hardware Co-Designed VLA Accelerator Exploiting Dynamic Weight-Precision Switching ActRAM: A Hybrid Analog/Digital Action-Expert Accelerator Architecture for Vision-Language-Action Models
Zhang, Mingtao	Fine-Grained Compiler-Assisted Hardening via Tolerant-Output Analysis for SDC–Runtime Trade-offs
Zhang, Mingzhe	Investigation of Karatsuba Algorithm for Large-Bitwidth Modular Multiplication
Zhang, Pengju	Learning-Augmented Multilevel Hypergraph Partitioning with Net-Level Cut Priors From Communities to Coordinates: Hierarchical Clustering–Guided Placement for Large-Scale FPGAs
Zhang, Qi	TriM: Efficient MoE Inference on Edge CPU-GPU Systems via Fused Quantization and Sensitivity-Guided Scheduling
Zhang, Qijun	RAP: Resource‑Aware Scheduling for GPU Accelerated Hypergraph Partitioning UnifyPower: A Unified Framework of Architecture-Level Power Model for Processors
Zhang, Qinyan	AHEAD: A Fast and Efficient MoE Speculative Decoding System via Dynamic Draft–Verify Coordination
Zhang, Qizhi	DISSECT: Cross-Family RTL Trojan Localization by Auditing Structural–Functional Disagreement
Zhang, Shilong	Clock Distribution Network with Backside Clock Mesh in BSPDN Architecture
Zhang, Shun	APRQ: Adaptive Prediction-Driven Residual Quantization Accelerator for Diffusion Transformers
Zhang, Shuyuan	SSR-VAR: Exploiting Spatial- and Scale-aware Redundancy for Lightweight Inference of Visual Autoregressive Models
Zhang, Sihai	From DRAM Architecture to Protocol State: A Resource-Grounded Executable Semantics for LPDDR5
Zhang, Wei	DFAC: Dataflow-Aided Intra-cluster Coalescer for AI Accelerators GLARE: Generalizable Large-scale Analog Sizing via Reinforcement Learning with Covariance-Guided Exploration HLSClaw: Bringing Vibe Coding to High-Level Synthesis through Skill-Based Agentic Harness
Zhang, Xinyuan	Weight-Stationary Fault Recovery via Neuron Tuning in RRAM-Based CIM Neuromorphic Accelerators
Zhang, Xinyun	MaxIM: A Plug-and-Play Maxwellian Engine via Interface Modification for Thick-Mask Lithography MAGI-OPC: Manhattan Area–Edge Learning Guided by High-Quality ILT for Optical Proximity Correction
Zhang, Yali	EtchMO: A Differentiable Etch Model for Mask Optimization
Zhang, Yibin	VoxPMC: A Fast Voxel-Based Particle Monte Carlo Simulator for Feature-Scale Process Topography Simulation
Zhang, Yichen	OMNI-DC: One-shot Multi-input Neural-Inference-Based Data Converter for Analog Computation-in-Memory
Zhang, Yong	LMSACO: LLM-Guided Multi-Objective State-Adaptive Analog Circuit Sizing Optimization
Zhang, Yuanjie	TACO: Topology-Aware Compression via Hardware–Software Co-Design for Robust CiM-Accelerated Edge RAG Retrieval
Zhang, Yufeng	Chain of SRAF Generation: A Large Reasoning Model for Sub-resolution Assist Features
Zhang, Yushen	3D-VASE: Volumetric-Aware Scalable and Efficient Multi-Layer Design Synthesis for 3D-Printed Microfluidics
Zhang, Zaihe	Enabling Energy-Efficient TinyML Inference via Fused Tensor Architecture
Zhang, Zhengyi	TensorLUT: Exact Batched RTL Simulation via ANF-Lifted Tensor-Core GEMM Formally Verified Contract-Aware Replacement of Ready/Valid Microarchitectures
Zhang, Zhiyuan	S-cache Directory: Efficient Sharer Tracking for Entry-Constrained Coherence Directories
Zhang, Zuodong	Anonymous: A CPU-GPU Heterogeneous Engine for Glitch-Aware Time-Based Gate-Level Power Analysis Anonymous: Fast Clock-Aware Timing Propagation for Complex Clock Logic and Constraints with State Flow Graph Abstraction Obstacle-Aware Timing-Driven Buffer Insertion via Feasible Shallow-Light Topology Reconstruction
Zhang, Zuodong	RAPID: An Efficient and Accurate Ratio-Based Analytical Proxy for Interconnect Delay PACT: A Runtime Contract for Sparse-Topology Updates in GPU-Accelerated Timing ECOs
Zhao, Chen	Between The Cracks: Uncovering Illegal-Instruction Bugs in RISC-V Processors by Exploring the Unified Encoding Space WaveAce: Analyzing the Root Cause of SoC Test Failures via LLMs' Direct Waveform Inspection
Zhao, Chunyuan	PACT: A Runtime Contract for Sparse-Topology Updates in GPU-Accelerated Timing ECOs
Zhao, Dingyi	ChronosDSE: Stability-Aware Design Space Exploration for GPGPUs
Zhao, Fei	PARFuzzer: Path-Aware RTL Fuzzing with Controlled BTB Conflict Injection for Branch-Predictor Security Validation
Zhao, Jiahao	From Isolate to Co-Deployment Risk: Coupling-Aware Mapping for ACIM-Digital AI Accelerator Device-Circuit Co-Optimization of SOT-MRAM with Accurate PPA Evaluation for Edge AI Training
Zhao, Jiayu	VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts
Zhao, Kang	PARFuzzer: Path-Aware RTL Fuzzing with Controlled BTB Conflict Injection for Branch-Predictor Security Validation Thermal-Aware Chiplet Placement Integrating Evolutionary Reinforcement Learning and Monte Carlo Tree Search Opening the Black Box: A Self-Correcting LLM Agent for EDA Toolchains Based on Source-Code Analysis Timing-Aware Routing and Heterogeneous TDM Assignment for Multi-Level FPGA-Based Emulation Systems FADiff: Fusion-Aware Differentiable Optimization for DNN Scheduling on Tensor Accelerators UACC: A Chiplet-Based Auxiliary Cache for Cost-Effective Performance Scaling in Multicore Processors
Zhao, Liangcheng	An Area-Efficient CIM-Based Ising Annealer with Folded Mapping and Cooling-Scheduled Parallel Swaps Strategy for Large-Scale Traveling Salesman Problem
Zhao, Quanling	Online Open-World Wafer Defect Discovery using Hyperdimensional Computing
Zhao, Tianlang	DeferKV: Long-Context LLM Attention Acceleration with Per-Token Scale Folding and Bank-Local Softmax on PIM CRISP: Paged Sparse Attention on DRAM-PIM with Row-Band-Aware KV Allocation and Frame-Derived Addressing MTPMoE: Exploiting Activation Skewness in Single-GPU MoE Multi-Token Prediction via Parallel Dense-Sparse Computing PowerPilot: Preserving Verified Progress in LLM-Based Power-Intent ECO Repair
Zhao, Xinyuan	A Lightweight Microring-Resonator PUF Design for Silicon Photonics Transceivers
Zhao, Yushuo	DISSECT: Cross-Family RTL Trojan Localization by Auditing Structural–Functional Disagreement
Zhao, Yuxuan	MoL-PAM: Joint P/G TSV Planning and Macro Refinement for Memory-on-Logic 3D ICs via a Benders-Type Decomposition Heuristic
Zhao, Zijun	MX-like Tensor Core for LLM Inference with NPU Integration via Hardware-Software Co-Design Exploration
Zheng, Jingyang	S-cache Directory: Efficient Sharer Tracking for Entry-Constrained Coherence Directories
Zheng, Peng	APRQ: Adaptive Prediction-Driven Residual Quantization Accelerator for Diffusion Transformers
Zheng, Zhiyu	3D-Syn: 3D-aware Synthesis Flow for Heterogeneous LogicFolding 3D ICs From Communities to Coordinates: Hierarchical Clustering–Guided Placement for Large-Scale FPGAs
Zhong, Haochen	RACE-FFN: Runtime-Adaptive Co-Execution in a Heterogeneous SA-CIM Architecture for Efficient MoE-FFN Acceleration
Zhong, Yicheng	Between The Cracks: Uncovering Illegal-Instruction Bugs in RISC-V Processors by Exploring the Unified Encoding Space WaveAce: Analyzing the Root Cause of SoC Test Failures via LLMs' Direct Waveform Inspection
Zhou, Chengwei	A Time-Encoded Analog Photonic Interposer for Energy-Efficient Integration of Analog Vision Sensors and Analog Accelerators
Zhou, Guanglei	SCALE: Self-Supervised Constraint-Aware Layout Generation for Local P&R DRV Fixing at Advanced Nodes
Zhou, Hongjian	OptiClear: Differentiable Curvilinear Design Rule Legalization for Inverse-Designed Photonic Device
Zhou, Jiaqi	DREAM:3D-stacked Token-wise Caching Diffusion Accelerator with Resource-Aware Mapping
Zhou, Jindong	A Two Stage Learning-Based Thermal-Aware Framework for 3D Fixed-Outline Soft-Module Floorplanning across Chip Sizes
Zhou, Lingfeng	Q-COMPASS: A Circuit-Calibrated Simulation Framework for QDI NoC Architecture Exploration
Zhou, Liyi	An Efficient Layout Decomposition Framework via Unsatisfiable Core
Zhou, Pingqiang	Hit-SME: A High-throughput Hybrid SNN-based MLP Engine for Neural Volume Rendering A Two Stage Learning-Based Thermal-Aware Framework for 3D Fixed-Outline Soft-Module Floorplanning across Chip Sizes
Zhou, Ruping	AnchorGNN: Cross-PVT Corner Timing Prediction via Anchor-Guided Graph Learning and STA-Aware Propagation
Zhou, Tongxin	AX-AGENT: Contract-Driven Closed-Loop Framework for Error-Bounded PPA-Aware Approximate RTL Generation
Zhou, Wenyong	InfoCIM: An Information-Theoretic Framework for Modeling and Design of Noise-Limited Analog CIM STRIDE: Sparse Thermal Reconstruction-Informed Differential Encoding for Thermally Stable 3D-Integrated Analog CIM ScaleLUT: A Fully-Parallel Configurable LUT-Based Accelerator for Real-Time Multi-Scale Super-Resolution ABNAT: Attention-Based Noise-Aware Training for Robust Transformers on Analog Compute-in-Memory Systems NANQ: Noise-Aware Mixed-Precision Non-Uniform Quantization for Neural Networks on Analog Compute-in-Memory ASSERT: Adaptive Stochastic Sampling for Robust Diffusion Models on Analog Compute-in-Memory Hardware NOVA-CIM: Noise- and Correlation-Tolerant Stochastic Interfaces for Analog Compute-in-Memory
Zhou, Yifei	UnO-NeSy: Optimizing Neuro-Symbolic Computing with Unified FeFET Based In-Memory System
Zhou, Yongbin	TraceMorph: Real-Trace-Guided Execution-Level Obfuscation for RAPL-Based DNN Architecture Protection
Zhou, Yongkang	MTPMoE: Exploiting Activation Skewness in Single-GPU MoE Multi-Token Prediction via Parallel Dense-Sparse Computing
Zhou, Yu	MAESTRO: Memo-Augmented Multi-Agent Engine for Self-Testing RTL Code Generation with Resource Orchestration
Zhou, Zhiwei	PSD-CIM:A Computing-In-Memory Attention Accelerator with Predictor-Free Sparsity search and Distribution Shaping
Zhou, Zhongchun	DFAC: Dataflow-Aided Intra-cluster Coalescer for AI Accelerators
Zhu, Binwu	HOIST: A High-Order Interaction Surrogate for Sample-Efficient High-Sigma Yield Estimation in High-Dimensional Circuits Curvilinear OPC via Diffeomorphic Deformation
Zhu, Guanda	RobotCFU: A Tightly Coupled Multi-Operator CFU for Embedded RISC-V Robot Control
Zhu, Hang	MinVNS: Minimal Virtual Network Separation for Deadlock Avoidance in Modular Network-on-Chip
Zhu, Jiadong	A Unified Framework for Circuit-Aware Tapped-Inductor Inverse Design with Topology-Aware Sequence Representation
Zhu, Jiaying	Adaptive BTOR2 Reformulation via Solver-Aware Equality Saturation
Zhu, Jixiang	PI-Aware Co-Layer Signal Routing and Power Plane Synthesis for Chiplet Interposers
Zhu, Keren	From Communities to Coordinates: Hierarchical Clustering–Guided Placement for Large-Scale FPGAs
Zhu, Songlin	Low-Power Approximate MRAM CAM with Dynamic-Reference for HDC Associative Search
Zhu, Tianxiang	SPLIT-MOR: Fast and Accurate Model Order Reduction for Nonlinear Transient Thermal Simulation of 2.5D/3D ICs Anonymous: A CPU-GPU Heterogeneous Engine for Glitch-Aware Time-Based Gate-Level Power Analysis
Zhu, Xiaolei	Sample-Efficient Neural Compact Modeling for Design-Technology Co-Optimization Based on Process-Aware Adaptation
Zhu, Yinuo	MAGI-OPC: Manhattan Area–Edge Learning Guided by High-Quality ILT for Optical Proximity Correction
Zhu, Yu	Cross-Bank ECC Strategy for LLM-Oriented Hybrid-Bonded 3D DRAM Architecture
Zhu, Yueyao	RASP-LLM: Radiation-Aware Design-Space Exploration of Precision and Selective Protection for On-Orbit LLM Inference
Zhu, Yugao	RAP: Resource‑Aware Scheduling for GPU Accelerated Hypergraph Partitioning
Zhu, Zhen	LUMEN: A Compressed-LUT-based Processing-Near-Memory Architecture for Efficient LLM Inference at the Edge ACED: An Algorithm–Hardware Co-Designed VLA Accelerator Exploiting Dynamic Weight-Precision Switching ActRAM: A Hybrid Analog/Digital Action-Expert Accelerator Architecture for Vision-Language-Action Models
Zhu, Zhenhua	RASP-LLM: Radiation-Aware Design-Space Exploration of Precision and Selective Protection for On-Orbit LLM Inference Cross-Bank ECC Strategy for LLM-Oriented Hybrid-Bonded 3D DRAM Architecture
Zhu, Zhixin	T3R: Training-Free Two-Stage Token Refinement Towards Efficient and Robust VLA Models
Zhu, Zhiying	UnO-NeSy: Optimizing Neuro-Symbolic Computing with Unified FeFET Based In-Memory System
Zhuang, Zhen	MoL-PAM: Joint P/G TSV Planning and Macro Refinement for Memory-on-Logic 3D ICs via a Benders-Type Decomposition Heuristic
Zhuang, Zhen	A HeteroGNN-Based Hierarchical Co-Optimization Framework for Floorplanning and Routing in Advanced Packaging
Zhuo, Cheng	UnO-NeSy: Optimizing Neuro-Symbolic Computing with Unified FeFET Based In-Memory System
Zong, Zhirui	A Unified Framework for Circuit-Aware Tapped-Inductor Inverse Design with Topology-Aware Sequence Representation
Zou, Chenghong	AHEAD: A Fast and Efficient MoE Speculative Decoding System via Dynamic Draft–Verify Coordination
Zou, Lancheng	Logic Resynthesis for Cross-Die Dependencies in Hybrid Bonded 3D ICs
Zou, Ningmu	ResistONet: Cascade Operator Network for Photoresist Simulation Chain of SRAF Generation: A Large Reasoning Model for Sub-resolution Assist Features Curvilinear OPC via Diffeomorphic Deformation EtchMO: A Differentiable Etch Model for Mask Optimization
Zou, Peng	CertIR: Certified Static IR-Drop Estimation with Physics-Anchored Neural Correction
Zou, Xinhang	SSR-VAR: Exploiting Spatial- and Scale-aware Redundancy for Lightweight Inference of Visual Autoregressive Models
Zou, Yi	A XNOR-SRAM-Based Computing-in-Memory Macro for Memory-Augmented Neural Networks RACE-FFN: Runtime-Adaptive Co-Execution in a Heterogeneous SA-CIM Architecture for Efficient MoE-FFN Acceleration
Zou, Zihan	APRQ: Adaptive Prediction-Driven Residual Quantization Accelerator for Diffusion Transformers TriM: Efficient MoE Inference on Edge CPU-GPU Systems via Fused Quantization and Sensitivity-Guided Scheduling
Zscherpel, Lukas	Naviq: An Open-Source System-on-Chip Simulator for Rapid Prototyping, Verification, and Design Space Exploration
Zuo, Dongsheng	RT-DRC: Accelerating Design Rule Checking Using GPU Ray-Tracing Cores
Zuo, Dongsheng	HINT: Toward an Executable Hardware-Intent Intermediate Representation Layer for LLM-Driven RTL Generation
Zuo, Dongsheng	GA2-CT: GPU-Accelerated Genetic Algorithm for Low-Power Compression-Tree Rewiring