Program for Thursday, January 28th, 2027: Talk View

PROGRAM FOR THURSDAY, JANUARY 28TH, 2027: TALK VIEW

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View: with abstracts session overview

9:00

9:30

10:00

10:30

11:00

11:30

12:00

12:30

13:00

13:30

14:00

14:30

15:00

15:30

16:00

16:30

17:00

17:30

09:00-09:50 Session 3K

10:20-12:20 Session 07A

10:20-10:40

A XNOR-SRAM-Based Computing-in-Memory Macro for Memory-Augmented Neural Networks

Bo Liu, Yi Zou, Xu Chen, Zhibiao Xue

10:40-11:00

Topology as a Design Variable: Joint Architecture-Sizing Optimization for SRAM

Can Wang, Junhao Ma, Yikai Wang, Shan Shen, Wei Xing

11:00-11:20

From Isolate to Co-Deployment Risk: Coupling-Aware Mapping for ACIM-Digital AI Accelerator

J. Zhao, C. Xiao, F. Gao, T. Nan, J. Tang, B. Song, W. Jia

11:20-11:40

NVM-in-Cache: Repurposing Commodity 6T SRAM Cache into NVM Analog Processing-in-Memory Engine using a Novel Compute-on-Powerline

Subhradip Chakraborty, Ankur Singh, Xuming Chen, Gourav Datta, Akhilesh Jaiswal

11:40-12:00

Device-Circuit Co-Optimization of SOT-MRAM with Accurate PPA Evaluation for Edge AI Training

F. Gao, C. Xiao, K. Wang, T. Sui, Z. Han, B. Song, J. Zhao, J. Tang, T. Nan

12:00-12:20

Reducing Read Retries by Skipping Similar Adjacent Read Voltage Parameters in 3D TLC NAND Flash

Cheng-You Fang, Han-Yu Liao, Chien-Chung Ho

10:20-10:40

A Unified Framework for Circuit-Aware Tapped-Inductor Inverse Design with Topology-Aware Sequence

Jiadong Zhu, Junjia Ru, Zhirui Zong, Yuzhe Ma

10:40-11:00

CONTOUR: Continuous Topology Search for System-Level RFICs via Bi-Level Optimization and Neural-Analytical

Y. Fang, H. He, H.-Y. Yeo, Z. Fu, H. Yu, M. Chen, T. Chi, D. Pan, S. Li

11:00-11:20

Atomic and Hierarchy-Safe Cross-Module Undo/Redo for Analog IC Design

Xiaohan Liu, Shouming Xia

11:20-11:40

SPGLA-Net: A Slotline-Aware Port-Graph Linear Attention Residual Network for Sub-THz On-Chip Passive

Songlin Xu, Jintao Li, Zongxiao Yang, Xiang Yi, Yun Li

11:40-12:00

CABAgent: A Cross-Stage Agentic Framework for Generating PDK-Compatible and Layout-Verified Analog Circuit

Hu, Wang, Bao, Xie, Goh, Siek, Yucel, Li, Lin, Gao

12:00-12:20

OptiClear: Differentiable Curvilinear Design Rule Legalization for Inverse-Designed Photonic Device

Hongjian Zhou, Haoyu Yang, Nicholas Gangi, Rena Huang, Jiaqi Gu

10:20-10:40

DPSQ : Dynamic Partial Sum Quantization with Mixed Granularity

Joonseok Kim, Dowon Kwon, Seokhyeong Kang, Younghyun Kim

10:40-11:00

AlignQuant: Alignment First Two-Stage Integer Microscaling Format for Systolic Native LLM Inference

Dongyoung Lee, Sangdong Lee, Seungkyu Choi, Ik-Joon Chang

11:00-11:20

PDG-CORDIC: A Posit-Decode-Guided Low-Latency CORDIC for Activation Function

Yibo Rui, Jiajun Zhang

11:20-11:40

APRQ: Adaptive Prediction-Driven Residual Quantization Accelerator for Diffusion Transformers

Zheng, Zhang, Chen, Hu, Lin, Hu, An, Zou, Wang, Gong, Cai, Liu

11:40-12:00

Enabling Efficient Quantized LLM Inference on Floating-Point CGRAs via Lightweight Integer

Chenlin Shi, Yanchen Li, Boma Adhi, Jiaheng Liu, Kentaro Sano

12:00-12:20

MX-like Tensor Core for LLM Inference with NPU Integration via Hardware-Software Co-Design

Zijun Zhao, Ruichu Ao, Stef Cuyckens, Marian Verhelst, Chao Fang

10:20-10:40

SpectraPlace2.5D: Thermal-aware Chiplet Placement via Topology-guided MILP and Spectral Thermal

Joonyoung Seo, Hyunjung Cho, Hyeonjae Lee, Hyunwoo Kim, Seokhyeong Kang

10:40-11:00

Thermal-Aware Chiplet Placement and Shape Co-Optimization under D2D Interconnect Constraints for 2.5D

Gangmin Jeon, Ikkyum Kim, Junghyun Yoon, Heechun Park

11:00-11:20

Thermal-Aware Chiplet Placement Integrating Evolutionary Reinforcement Learning and Monte Carlo Tree

Cao Debin, Kanglin Tian, Ze Hao, Yi Huang, Bei Yu, Jianwang Zhai, Kang Zhao

11:20-11:40

A HeteroGNN-Based Hierarchical Co-Optimization Framework for Floorplanning and Routing in Advanced

Yiqi Huang, Zepeng Li, Zhen Zhuang, Kehao Chen, Genggeng Liu, Tsung-Yi Ho

11:40-12:00

PI-Aware Co-Layer Signal Routing and Power Plane Synthesis for Chiplet Interposers

J. Zhu, Y. Wang, X. Lin, L. Feng, B. Zhang, Y. Wang, Y. Han

12:00-12:20

Network Flow Guided Routing and Force Directed Offset Via Placement for Advanced Chiplet

Haoju Chang, Po-Chien Chiu, Hui-Jie Luo, Hung-Ming Chen, Chien-Nan Liu

10:20-10:40

TensorLUT: Exact Batched RTL Simulation via ANF-Lifted Tensor-Core GEMM

Zhengyi Zhang, Sijing Yang, Yuwei Qu, Zixuan Xiao, Lingli Wang

10:40-11:00

Encoding Symmetries into Operator Learning: Towards Accurate Multi-Physics Simulation in Advanced

Che-Ming Chang, Shao-Yu Lo, Yao-Wen Chang, Sung Kyu Lim

11:00-11:20

Memory-Aware Design-Space Exploration for Multi-Threaded HLS Accelerators

Firoz, Gozzi, Fiorito, Manzano, Bel, Ferrandi, Barker, Tumeo

11:20-11:40

VoxPMC: A Fast Voxel-Based Particle Monte Carlo Simulator for Feature-Scale Process Topography

Y.C. Ng, Y. Zhang, S. Tang, H. Pan, L. Hu, D. Gong, W. Yu

11:40-12:00

Cross-Family Graph Learning for Sparse Aging-Aware Timing Characterization of Standard-Cell

Zhibin Chen, Runsheng Liu, Songxuan He, Linlin Cai, Wangyong Chen

12:00-12:20

HOIST: A High-Order Interaction Surrogate for Sample-Efficient High-Sigma Yield Estimation in High-Dimensional

Zhongru Xiong, Mingjun Wang, Yanfang Liu, Tsung-Yi Ho, Bei Yu, Binwu Zhu

13:20-15:20 Session 08A

13:20-13:40

GD-PIM: A Low-Cost Gustavson Dataflow-Based Processing-in-Memory Architecture for SpGEMM

Minsang Yu, Seungsu Kim, Jongeun Lee

13:40-14:00

MfSpGEMM: Merger-Free Row-Wise SpGEMM with Bitmap Accumulation and HBM-Aware Mapping

Zhu Shulin, Yu Jiaqi, Zhou Yi, Zhao Liang

14:00-14:20

RACE-FFN: Runtime-Adaptive Co-Execution in a Heterogeneous SA-CIM Architecture for Efficient MoE-FFN

Xu Chen, Zhibiao Xue, Bo Liu, Xiaoquan Xu, Haochen Zhong, Yi Zou

14:20-14:40

GenMLIR: An MLIR Compiler for Dynamic Programming Workloads on Tier-Aware 3D-DRAM PIM

Mahbod Afarin, Tsung-Han Lu, Tajana Rosing

14:40-15:00

HAVEN: High-Bandwidth Flash Augmented Vector ENgine for Large-Scale Approximate Nearest-Neighbor Search

Po-Kai Hsu, Weihong Xu, Qunyou Liu, Tajana Rosing, Shimeng Yu

15:00-15:20

An Area-Efficient CIM-Based Ising Annealer with Folded Mapping and Cooling-Scheduled Parallel Swaps Strategy for Large-Scale Traveling Salesman

Ruihao He, Cong Wang, Liangcheng Zhao, Shaoxuan Li, Hongwu Jiang

13:20-13:40

TempoGS: Temporal Binning and Expiration-Aware Gaussian Loading for Memory-Efficient 4D Gaussian Splatting

Hyerin Lim, Seung-Eon Hwang, Jongsun Park

13:40-14:00

SSR-VAR: Exploiting Spatial- and Scale-aware Redundancy for Lightweight Inference of Visual Autoregressive

Y. Wang, L. He, X. Zou, S. Zhang, H. Yang, Y. Liu, H. Jia

14:00-14:20

DREAM:3D-stacked Token-wise Caching Diffusion Accelerator with Resource-Aware Mapping

Jiaqi Zhou, Han Liu, Qianxu Wang, Tianyu Jia

14:20-14:40

3DToMe: A Morton-Local and Interaction-Aware Token-Merging Accelerator for Efficient 3D Diffusion Policy

Le Qiu, Wenyu Sun, Yongpan Liu

14:40-15:00

ScaleLUT: A Fully-Parallel Configurable LUT-Based Accelerator for Real-Time Multi-Scale

Li, Ding, Ai, Shi, Jiang, Zhou, Huang, Ren, Yu, Wong

13:20-13:40

GARDEN: GPU-Accelerated Rapid Divisor Extraction

Zewen Li, Tianji Liu, Evangeline F.Y. Young

13:40-14:00

GA2-CT: GPU-Accelerated Genetic Algorithm for Low-Power Compression-Tree Rewiring

Dongsheng Zuo, Rui Qiu, Qiang Xu

14:00-14:20

Fast Delay-oriented Logic Optimization with Parallel SOP Generation

Ziang Ge, Tianji Liu, Evangeline F.Y. Young

14:20-14:40

3D-Syn: 3D-aware Synthesis Flow for Heterogeneous LogicFolding 3D ICs

Zehao Yang, Zhiyu Zheng, Chang Meng, Zhiang Wang, Weikang Qian

14:40-15:00

Multi-Output-Guided Transistor Network Synthesis and Layout for Sequential Cells

Kang, Kim, Lee, Kim, Kim, Baek, Kang, Sur-Kolay, Lin, Cheng

15:00-15:20

Logic Resynthesis for Cross-Die Dependencies in Hybrid Bonded 3D ICs

F. Liu, Y. Ji, L. Zou, J. Liu, M. Wang, G. Chen, G. Guo, B. Yu

13:20-13:40

AgenticPD: A Stage-Aware Agentic Framework for Closed-Loop Physical Design Optimization

Ren, Cheng, Han, Shen, Jin, Tian, Fu, Wang, Yu, Ho

13:40-14:00

Opening the Black Box: A Self-Correcting LLM Agent for EDA Toolchains Based on Source-Code Analysis

Hao Luo, Zhenghao Chen, Kanglin Tian, Kang Zhao, Jianwang Zhai

14:00-14:20

CoEvoP&R: Co-Evolving Placement Objectives with Routing Feedback via Large Language Models

Ruogu Chen, Weihua Xiao, Ramesh Karri, Jie Han

14:20-14:40

VPR-Evolve: Multi-Agent-Driven Algorithm Evolution for FPGA Place and Route

Qihang Wu, Taizun Jafri, Aman Arora, Vidya Chhabria

14:40-15:00

Phase-Aware Monte Carlo Tree Search with LLM-Guided Proposal for Multi-Objective Physical Design

Jongho Yoon, Jeonghyun Choi, Jaemin Seo, Seokhyeong Kang

15:00-15:20

EvoDRC: A Self-Evolving Agentic Framework for Automated DRC Violation Repair

Bing-Yue Wu, Chia-Tung Ho, Haoyu Yang, Brucek Khailany, Vidya Chhabria

13:20-13:40

MaxIM: A Plug-and-Play Maxwellian Engine via Interface Modification for Thick-Mask Lithography

L. Wang, S. Yao, W. Dong, Z. Yu, J. Liu, X. Zhang, J. Yu, H. Geng

13:40-14:00

ResistONet: Cascade Operator Network for Photoresist Simulation

Yiqing Wang, Silin Chen, Yuqian Zang, Jiale Li, Xiaodong Meng, Ningmu Zou

14:00-14:20

MAGI-OPC: Manhattan Area–Edge Learning Guided by High-Quality ILT for Optical Proximity Correction

Zhen Wang, Yinuo Zhu, Wenxuan Dong, Jiaqi Liu, Xinyun Zhang, Jingyi Yu, Hao Geng

14:20-14:40

Chain of SRAF Generation: A Large Reasoning Model for Sub-resolution Assist Features

J. Li, S. Chen, Y. Zhang, Z. Xu, Y. Wang, W. Xu, Z. Yu, B. Yu, N. Zou

14:40-15:00

Curvilinear OPC via Diffeomorphic Deformation

Silin Chen, Kangjian Di, Jiale Li, Binwu Zhu, Ningmu Zou

15:00-15:20

EtchMO: A Differentiable Etch Model for Mask Optimization

Jiale Li, Silin Chen, Yiqing Wang, Yali Zhang, Yang Xia, Ningmu Zou

15:40-17:40 Session 09A

15:40-16:00

ABNAT: Attention-Based Noise-Aware Training for Robust Transformers on Analog Compute-in-Memory

W. Yao, W. Zhou, H. Shao, Z. Ning, Y. Chen, Y. Feng, K. Tang, R. Huang

16:00-16:20

NANQ: Noise-Aware Mixed-Precision Non-Uniform Quantization for Neural Networks on Analog

Y. Chen, W. Yao, S. Wang, Y. Feng, G. Wang, K. Tang, W. Zhou, W. Kang

16:20-16:40

ASSERT: Adaptive Stochastic Sampling for Robust Diffusion Models on Analog Compute-in-Memory

Y. Feng, Y. Chen, W. Yao, Y. Xie, N. Wong, W. Zhou, W. Kang

16:40-17:00

NOVA-CIM: Noise- and Correlation-Tolerant Stochastic Interfaces for Analog Compute-in-Memory

J. Ren, W. Yao, H. Liu, X. Feng, C. Hu, Z. Liu, K. Tang, W. Zhou, N. Wong

17:00-17:20

ACCORD-IC: Contract-Checked Relation Transactions for Low-Bit Dynamic CNN–GNN Inference

Abdolvahab Khalili Sadaghiani, Jose Nunez-Yanez

17:20-17:40

SURE-AI: Single-pass Uncertainty Estimation for Reliable Edge AI Accelerators

Mangadahalli Siddaramu et.al

15:40-16:00

CRAFT: Constraint-Guided Region-Adaptive Search over Broad Design Spaces for High-Dimensional Analog Circuit

W. Fan, P. Guo, S. Yin, Z. Chen, H. Zhang, R. Wang, L. Shen, Y. Lin

16:00-16:20

Archive-Guided MOEA/D for Constrained Many-Objective Analog Circuit Sizing

Guyu Ma, Chengjie Liu, Weiyu Chen, Jun Yang

16:20-16:40

GLARE: Generalizable Large-scale Analog Sizing via Reinforcement Learning with Covariance-Guided

Jiang, Wang, Wu, Long, Liang, Wang, Wang, Ouyang, An, Jiang, Zhang

16:40-17:00

FUSE: Five-Block MVM Energy Comparison

Oceane Bel, Jesun Firoz, Prashansa Mukim, James Ang, Grzegorz Deptuch

17:00-17:20

MIBIFI: Differentiable Electronic–Photonic–Thermal Co-Simulation for Co-Packaged Optics Designs

Janie Lee, Wei-Ting Chen, Chien-Nan Jimmy Liu

17:20-17:40

A Time-Encoded Analog Photonic Interposer for Energy-Efficient Integration of Analog Vision Sensors and Analog

S. Chakraborty, Z. Yin, X. Chen, C. Zhou, G. Datta, A. Jaiswal

15:40-16:00

VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts

Jiayu Zhao, Zehua Pei, Zetao Guo, Bei Yu, Song Chen

16:00-16:20

SpecLens: LLM-Based Verilog Generation with Specification-Derived Constraints via Behavioral

Wen Bing, Bing Li

16:20-16:40

MAESTRO: Memo-Augmented Multi-Agent Engine for Self-Testing RTL Code Generation with Resource

Shukai Liu, Yu Zhou, Zirun Huang, Qimin Xu, Cailian Chen

16:40-17:00

HLSClaw: Bringing Vibe Coding to High-Level Synthesis through Skill-Based Agentic Harness

J. Ge, S. Liu, J. Liang, S. Li, A. Ahmad, J. Xu, L. Du, W. Zhang

17:00-17:20

ARES: Adaptive Reasoning-Effort Steering for PPA- and Cost-Aware RTL Optimization with LLM Agents

Stef Cuyckens, Mihaela Jivanescu, Jun Yin, Chao Fang, Marian Verhelst

17:20-17:40

HINT: Toward an Executable Hardware-Intent Intermediate Representation Layer for LLM-Driven RTL

T. Cheng, Y. Liu, D. Zuo, Z. Shi, H. Zhang, X. Hu, M. He, H. Yan, Q. Xu

15:40-16:00

RAPID: An Efficient and Accurate Ratio-Based Analytical Proxy for Interconnect Delay

H. Liu, Z. Guo, Z. Zhang, Y. Cheng, G. Guo, R. Wang, Y. Lin

16:00-16:20

PACT: A Runtime Contract for Sparse-Topology Updates in GPU-Accelerated Timing ECOs

H. Liu, Z. Guo, Z. Zhang, H. Zhang, C. Zhao, K. Guo, S. Hua, G. Guo, Y. Lin

16:20-16:40

Anonymous: Fast Clock-Aware Timing Propagation for Complex Clock Logic and Constraints with State Flow Graph

X. Shi, Z. Guo, Z. Zhang, G. Guo, Y. Liang, R. Wang, Y. Lin

16:40-17:00

AnchorGNN: Cross-PVT Corner Timing Prediction via Anchor-Guided Graph Learning and STA-Aware

Shengkai Guo, Ruping Zhou, Genggeng Liu

17:00-17:20

Obstacle-Aware Timing-Driven Buffer Insertion via Feasible Shallow-Light Topology Reconstruction

Jiahao Xu, Yuhao Ji, Yifan Shi, Zizheng Guo, Zuodong Zhang, Yibo Lin, Bei Yu

17:20-17:40

HGRP: Heterogeneous Graph Neural Network for Routability Prediction

Yule Sheng, Yue Yuan, Shan Shen, Daying Sun

15:40-16:00

When Fuzzing Meets Understanding: LLM-Driven Semantic Test Generation for RTL Verification

Kun Wang, Cangyuan Li, Kaiyan Chang, Siyang Cai, Yinhe Han, Ying Wang

16:00-16:20

CHAIDO: Open-Source Simulation-Based Fault Injection for the AMD Versal AI Engine

G. Sotiropoulos, F. Paraskevas, M. Neu, T. Harbaum, T. Ferber, J. Becker

16:20-16:40

Weight-Stationary Fault Recovery via Neuron Tuning in RRAM-Based CIM Neuromorphic Accelerators

Yangu, Zhang, Chen, Wong, Ye, Ding, Liu, Lin, Tan, Qi, Wang, Wang

16:40-17:00

TRAIT: Trajectory-based Robust Aging-aware Chip Identification for Traceability

Soga Hayakawa, Michihiro Shintani, Takashi Sato, Makoto Eiki, Yuta Mitake

17:00-17:20

WaveAce: Analyzing the Root Cause of SoC Test Failures via LLMs' Direct Waveform Inspection

Y. Zhong, J. Wu, X. Ling, H. Lyu, Z. Rui, T. Luo, C. Zhao

17:20-17:40

SRAM Bitcell-Peripheral Co-Optimization Under Array-Level Yield Constraints

Y. Wang, Y. Wu, J. Ma, C. Wang, K. Huang, Z. Liu, S. Shen, W.W. Xing

10:00-10:20 Coffee Break

12:20-13:20 Lunch Time

15:20-15:40 Coffee Break