Days: Monday, October 30th Tuesday, October 31st Wednesday, November 1st Thursday, November 2nd

Monday, October 30th

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16:30-18:00 Session P1: Monday Panel: Automotive Safety and Security: The Impending Challenges and Hopes on the Horizon

Panel Organizers: Mark Tehranipoor (University of Florida) and Yervant Zorian (Synopsys)
Panel Moderator: Mark Tehranipoor (University of Florida)

Safety and security assurance of future smart vehicles have become ever more important and a pressing need.  The complex ecosystem delivering components – both hardware and software – through a potentially untrusted supply chain and the sheer complexity of security design and validation of modern cars create host of new challenges with system security. Innovative features like driver assistance, infotainment via smartphone integration or over-the-air (OTA) updates keep increasing the potential attack surfaces and vulnerabilities for both remote and physical attacks. This panel will cover this important topic and point to the associated challenges as well as hopes in the horizon. 

Yervant Zorian, Synopsys
Riccardo Mariani, Intel
Ken Modeste, Underwriters Laboratories
Swarup Bhunia, University of Florida
Yousef Iskandar, Cisco

Mark Tehranipoor (University of Florida, United States)
Tuesday, October 31st

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09:30-10:30 Session K1: Plenary Keynote: Testing Beyond the Green Light

Presenter:  Bob Klosterboer, EVP of the Analog Solutions Group, ON Semiconductor

Abstract:  This presentation will highlight some of the challenges and opportunities that test developers and test operations managers face in a changing data climate. Measured data will drive decisions not only about the product under test but potentially on the entire design and manufacturing ecosystem. I will also explore some the value tradeoffs of increased data harvesting vs reduced test cost requirements of each component.

Bio:  Robert Klosterboer joined ON Semiconductor in March 2008 and currently serves as Executive Vice President and General Manager of the Analog Solutions Group for ON Semiconductor and SCI LLC. From March 2008 to September 2012 he was Senior Vice President and General Manager of the business unit then known as the Automotive, industrial, Medical, & Mil/Aero Group. He has more than two decades of experience in the electronics industry. During his career, Mr. Klosterboer has held various engineering, marketing and product line management positions. Prior to joining ON Semiconductor in 2008, Mr. Klosterboer was Senior Vice President, Automotive & Industrial Group for AMI Semiconductor, Inc. Mr. Klosterboer joined AMIS in 1982 as a test engineer and during his tenure there he also was a design engineer, field applications engineer, design section manager, program development manager, and product marketing manager. Mr. Klosterboer holds a bachelor's degree in electrical engineering technology from Montana State University.

14:00-16:00 Session 1: Analog/RF BIST & Calibration
Gordon Roberts (McGill University, Canada)
Haralampos-G. Stratigopoulos (Sorbonne Universités, UPMC Univ. Paris 6, CNRS, LIP6, France)
Nimit Jain (IIT Madras, India)
Nitin Agarwal (Texas Instruments (India) Pvt. Ltd, India)
Rajavelu Thinakaran (Texas Instruments (India) Pvt. Ltd, India)
Rubin Parekhji (Texas Instruments (India) Pvt. Ltd, India)
Low-Cost Dynamic Error Detection in Linearity Testing of SAR ADCs ( abstract )
Sabyasachi Deyati (Georgia Institute of Technology, United States)
Barry Muldrey (Georgia Institute of Technology, United States)
Abhijit Chatterjee (Georgia Institute of Technology, United States)
Byunghoo Jung (Purdue University, United States)
Concurrent Built-in Test and Tuning of Beamforming MIMO Systems Using Learning-assisted Performance Optimization ( abstract )
Xiankun Jin (NXP Semiconductor, United States)
Tao Chen (Iowa State University, United States)
Mayank Jain (NXP Semiconductors, India)
Arun Kumar Barman (NXP semiconductors, India)
David Kramer (NXP Semiconductors, United States)
Doug Garrity (NXP Semiconductors, United States)
Randal Geiger (Iowa State University, United States)
Degang Chen (Iowa State University, United States)
An On-Chip ADC BIST Solution and the BIST-enabled Calibration Scheme ( abstract )
Jae Woong Jeong (NXP Semiconductors, United States)
Ender Yilmaz (NXP Semiconductors, United States)
Leroy Winemberg (NXP Semiconductors, United States)
Sule Ozev (Arizona State University, United States)
Built-in Self-Test for Stability Measurement of Low-Dropout Regulator ( abstract )
14:00-16:00 Session 2: Diagnosis
Ken Butler (Texas Instruments, United States)
Phil Nigh (GLOBALFOUNDRIES, United States)
Subhadip Kundu (Synopsys, India)
Kuldip Kumar (Synopsys, India)
Rishi Kumar (Synopsys, India)
Rohit Kapur (Synopsys Inc., United States)
Diagnosing Multiple Faulty Chains with Low-Pin Convolution Compressor Using Compressed Production Test Set ( abstract )
Srikanth Venkataraman (Intel, United States)
Irith Pomeranz (Purdue University, United States)
Shraddha Bodhe (Purdue University, United States)
Enamul Amyeen (Intel, United States)
Test Reordering for Improved Scan Chain Diagnosis Using an Enhanced Defect Diagnosis Procedure ( abstract )
Chuanhe Shan (University of California Santa Barbara, United States)
Pietro Babighian (GLOBALFOUNDRIES, United States)
Yan Pan (GLOBALFOUNDRIES, United States)
John Carulli (GLOBALFOUNDRIES, United States)
Li-C. Wang (University of California Santa Barbara, United States)
Systematic Defect Detection Methodology for Volume Diagnosis: A Data Mining Perspective ( abstract )
Sameer Chillarige (Cadence Design Systems, India)
Anil Malik (Cadence Design Systems, India)
Sharjinder Singh (Cadence Design Systems, India)
Joe Swenton (Cadence Design Systems, India)
Krishna Chakravadhanula (Cadence Design Systems, India)
High-Throughput Multiple Device Diagnosis System ( abstract )
14:00-16:00 Session 3: Scan Architectures
Tm Mak (self, United States)
Mehdi Tahoori (Karlsruhe Institute of Technology, Germany)
Wilson Pradeep (Texas Instruments, India)
Prakash Narayanan (Texas Instruments, India)
Rajesh Mittal (Texas Instruments, India)
Naman Maheshwari (Texas Instruments, India)
Nikita Naresh (Texas Instruments, India)
Frequency-Scaled Segmented (FSS) Scan Architecture for Optimized Scan-Shift Power and Faster Test Application Time ( abstract )
Grady Giles (AMD, United States)
Jeff Rearick (AMD, United States)
Guoliang Li (AMD, China)
John Schulze (AMD, United States)
Yan Dong (AMD, United States)
James Wingfield (AMD, United States)
Tim Wood (AMD, United States)
Maximizing Scan Pin and Bandwidth Utilization with a Scan Routing Fabric ( abstract )
Xijiang Lin (Mentor Graphics Corp., United States)
On Applying Scan-based Structural Test for Designs with Dual-Edge Triggered Flip-Flops ( abstract )
Stefan Holst (Kyushu Institute of Technology, Japan)
Eric Schneider (University of Stuttgart, Germany)
Koshi Kawagoe (Kyushu Institute of Technology, Japan)
Michael A. Kochte (University of Stuttgart, Germany)
Kohei Miyase (Kyushu Institute of Technology, Japan)
Hans-Joachim Wunderlich (University of Stuttgart, Germany)
Seiji Kajihara (Kyushu Institute of Technology, Japan)
Xiaoqing Wen (Kyushu Institute of Technology, Japan)
Analysis and Mitigation of IR-Drop-Induced Scan Shift-Errors ( abstract )
14:00-16:00 Session PO: Poster Previews
Raghuraman Rajanarayanan (Achronix Semiconductor, India)
Adam Cron (Synopsys, United States)
Interstitial DFT in SpeedCore™ ( abstract )
Shravan K Chaganti (Iowa State University, United States)
Li Xu (Texas Instruments, United States)
Degang Chen (Iowa State University, United States)
A Low-Cost Jitter Separation and ADC Spectral Testing Method Without Requiring Coherent Sampling ( abstract )
Martin Keim (Mentor Graphics - A Siemens Business, United States)
Al Crouch (Amida, United States)
Michael Laisne (Dialog Semiconductor, United States)
Quo Vadis IJTAG.1? ( abstract )
Matthew Knowles (Mentor, a Siemens Business, United States)
Givargis Danialy (Mentor, a Siemens Business, United States)
Marc Hutner (Teradyne, Canada)
Scaling Interactive IJTAG Debug Beyond the Desktop to ATE ( abstract )
Kaitlyn Chen (Intel, United States)
Ramesh Sharma (Intel, United States)
Luc Romain (Mentor Graphics - A Siemens Business, Canada)
Reinhard Meier (Mentor Graphics Development (Deutschland) GmbH, Germany)
Jf Cote (Mentor Graphics - A Siemens Business, Canada)
Benoit Nadeau-Dostie (Mentor Graphics - A Siemens Business, Canada)
Albert Au (Mentor Graphics - A Siemens Business, Canada)
Martin Keim (Mentor Graphics - A Siemens Business, United States)
Reducing Memory BIST ATE Test Time Through a Data-ready Observation Port modeled in IJTAG ( abstract )
Anne Meixner (The Engineers' Daughter LLC, United States)
Keith Arnold (PDF Solutions, United States)
An Immodest Proposal to Bridge Test and Design Data for SoC and IP Yield ( abstract )
Wesley Smith (Mentor - A Siemens Business, United States)
Steven McDowall (Mentor - A Siemens Business, United States)
Marc Hutner (Teradyne Inc, Canada)
Taming of the Shmoo ( abstract )
Vidya Neerkundar (Mentor A Siemens Business, United States)
Henrik Bergendal (MicroSemi Corporation, Denmark)
Technique to Test Hierarchical Designs with Multiple Design Levels ( abstract )
Matthew Beckler (Carnegie Mellon University, United States)
Shawn Blanton (CMU, United States)
Evaluation of Transition-X Fault Model for On-Chip Diagnosis of Multiple Defects ( abstract )
Carl Wisnesky Ii (Cadence Design Systems, Inc., United States)
Patrick Gallagher (Cadence Design Systems, Inc., United States)
BIST On-demand Using Distributed On-Chip Programmable Data Streams ( abstract )
Daisuke Yabui (Tokushima University, Japan)
Masaki Hashizume (Tokushima University, Japan)
Hiroyuki Yotsuyanagi (Tokushima University, Japan)
Shyue-Kung Lu (National Taiwan Univ. of Science and Technology, Taiwan)
Online Electrical Interconnect Test Method Utilizing IEEE 1149.1 Architecture ( abstract )
Mike Lemanski (NXP Semiconductor, United States)
Kassem Hamze (NXP, United States)
Archana Jain (NXP, United States)
Development of a Production-worthy ATE Test Screen for a Unique Device Fail Signature ( abstract )
Procheta Chatterjee (IIEST, Shibpur, India)
Surajit Kumar Roy (IIEST Shibpur, India)
Hafizur Rahaman (IIEST, Shibpur, India)
Chandan Giri (IIEST, Shbpur, India)
Testing TSVs for Micro-void and Pinhole Defects Using OTA ( abstract )
David Keezer (Georgia Institute of Technology, United States)
Jingchi Yang (Georgia Institute of Technology, United States)
Self-Test and Self-Repair Method for FPGAs ( abstract )
Todd Jacobs (NXP Semiconductors, United States)
William Morris (NXP Semiconductors, United States)
Sharon Levy (NXP Semiconductors, United States)
A VMIN Temperature Shift Outlier Screen for Cold Test Elimination ( abstract )
Tal Kogan (Intel, Israel)
Amihay Rabenu (Inetl, Israel)
Tal Frucht (Intel, Israel)
Hierarchical Hybrid EDT-LBIST System ( abstract )
V.R. Devanathan (Texas Instruments Inc, United States)
Sumant Kale (Texas Instruments Inc, United States)
A Hierarchical, Power-safe, Parallel Memory Self-Test Architecture for In-Field Test ( abstract )
Hardik Bhagat (GlobalFoundries, India)
Greeshma Jayakumar (GlobalFoundries, India)
Automatic Solution to Frame-Clock-Domain Groupings for Efficient At-Speed Structural Testing ( abstract )
Mahroo Zandrahimi (Delft University of Technology, Netherlands)
Philippe Debaud (ST-Microelectronics, France)
Armand Castillejo (STMicroelectronics, France)
Zaid Al-Ars (Delft University, Netherlands)
Transition Fault Testing for Offline Adaptive Voltage Scaling ( abstract )
Yan Duan (Iowa State University, United States)
Hsinho Wu (Intel, United States)
Masashi Shimanouchi (Intel, United States)
Mike Peng Li (Intel, United States)
Degang Chen (Iowa State University, United States)
A Comparator-based Method for Decomposition of Random and Data-dependent Jitter in High-Speed Data Links ( abstract )
Vinay Kumar (STMicroelectronics Inc, United States)
Adam Cron (Synopsys, United States)
A Method to Debug LBIST-Mode SSA/TF Silicon Failure Accurately Using Scan-Through-TAP (STT) Mode ( abstract )
Ya-Syuan Wu (National Central University, Taiwan)
Ching-Ju Lin (National Central University, Taiwan)
Jwu E Chen (National Central University, Taiwan)
Hsing-Chung Liang (Hsing-Chung Liang Chung Yuan Christian University, Taiwan)
The Rainbow Transformed from a Set of Uniform-Defect Wafer Maps ( abstract )
Mallika Pokharel (Texas A&M University, United States)
Duncan Walker (Texas A&M University, United States)
Multicycle At-Speed Test ( abstract )
Jonathan Phelps (On Semiconductor, United States)
Vidya Neerkundar (Mentor A Siemens Business, United States)
Productivity Gains with Hierarchical DFT Methodology for Physically Flat Design – A Case Study ( abstract )
A.T Sivaram (Advantest, United States)
Oyama Yasuji (Advantest, United States)
Sam El Alam (Qualcomm, United States)
Arul Subbarayan (Qualcomm, United States)
Delay Fault Testing Using Cloud Testing Service ( abstract )
Kevin Fan (Advantest, Taiwan)
Multisite PMIC Fast Trimming with Pattern-based Search Function ( abstract )
16:30-18:00 Session S1: Special Session: Benchmarks

Organizer: Jeff Rearick, AMD

For evaluating the performance and effectiveness of new test methods and algorithms, and for comparing new approaches with those previously published, benchmark circuits have proven to be highly useful.  This session will explore two new sets of benchmarks, one for analog circuits and the other for 1687 networks.  Both of these topics are quite active in the industry and the standards development community, which makes the release of these benchmarks timely and pertinent.  To examine the importance of benchmarks in general, as well as to strike a cautionary note about the effects of over-reliance on the specific attributes of published benchmarks, the final presentation will review several other available test benchmarks and reflect on what we’ve learned in the past decades through using them.

Jeff Rearick (AMD, United States)
Stephen Sunter (Mentor Graphics, Canada)
Peter Sarson (ams, Austria)
A/MS Benchmark Circuits for Comparing Fault Simulation, DFT, and Test Generation Methods ( abstract )
Sergei Devadze (Testonica Lab, Estonia)
Artur Jutman (Testonica, Estonia)
Anton Tsertov (Testonica Lab, Estonia)
Jeff Rearick (AMD, United States)
Doing more with ITC'2016 IEEE 1687 Benchmarks: Ecosystem and PDLs ( abstract )
Scott Davidson (Retired, United States)
A Third of a Century of ATPG Benchmarks ( abstract )
16:30-18:00 Session S2: Special Session: Design to Specifications and Test for Defects in Analog

Description: Testing of analog circuits has been challenging since there is no uniformly accepted behavior of defects and no established relationship between defects and fault coverage therein. To ensure quality of the manufactured circuit, there is a tendency to test the circuit for all its operating performance parameters. However, this is becoming increasingly unaffordable and hence there is an increasing focus on testing for defects alone as against testing for specifications. This special session will have three experts present their views on what is required for designing to specifications and testing for defects alone in analog circuits, and what are the impediments to adopting this as a design and test methodology. These presentations will cover illustrations on where and how these methods have been successfully used on today’s circuits and what are the challenges preventing their wider adoption. Other aspects of evaluating these methods using silicon data from characterization and production, and how they scale for low DPPM requirements will also be covered. These will lead to a recipe for defect based testing for analog. 

Rubin Parekhji (Texas Instruments (Bangalore), India)
Wim Dobbelaere (ON Semiconductor, Belgium)
Testing for Latent Defects in the Analog: Does the Spec. Matter? ( abstract )
Mike Ales (Texas Instruments, United States)
Functional vs. Defect-based Testing in Context of Analog Mixed-Signal Blocks ( abstract )
Abhijit Chatterjee (Georgia Institute of Technology, United States)
Advanced Test Methods for Mixed-Signal Circuits: Specification vs. Defect-based Test ( abstract )
16:30-18:00 Session TC: IEEE TTTC E.J. McCluskey Best Doctoral Thesis Award 2017: Final Competition
Michele Portolan (IMAG, France)
Boyang Du (Politecnico di Torino, Italy)
Luca Sterpone (Politecnico di Torino, Italy)
Fault-tolerant Electronic System Design ( abstract )
Yuming Zhuang (Iowa State University, United States)
Degang Chen (Iowa State University, United States)
Accurate and Robust Spectral Testing with Relaxed Instrumentation Requirements ( abstract )
Surajit Kumar Roy (Indian Institute of Engineering Science and Technology, India)
Design-for-Test and Test Optimisation for 3D SOCs ( abstract )
16:30-18:00 Session TUT1: Advances in Diagnosis in Nano-scale Era

Post Silicon diagnosis drives the isolation of manufacturing defects and provides feedbacks for process improvement and is critical for enabling Moore’s law and semiconductor technology scaling. Due to the increasing complexity of nano-scale manufacturing fabrication, the need for faster root-cause of issues is essential for volume production ramp to meet the product time to market demand.  Over the last several years, many innovations have been made and novel solutions are emerging for better and faster defect isolation. With the advent of new transistor devices, lithography, and fabrication processes, the demand for improving the defect isolation and faster yield learning will continue to grow in coming years.


In this tutorial, we will review the basics of diagnosis approaches, and advancements in post silicon diagnosis field. In addition to diagnosis quality improvement, increased focus has been made to volume processing of diagnosis results for yield learning. This has resulted in introduction of new DFT technologies to obtain and process massive amount of fail data, and to provide better controllability and observability of failures to narrow down the defect suspects. Diagnosis algorithms are optimized to provide speed-ups in analysis time. Advancements are made in fault modeling to abstract the complex defect behavior and logical analysis of failures are being incorporated with layout analysis for finer pruning of diagnosis candidates.  We will review emerging techniques of learning based diagnosis approach which combining with process sensitivity, DFM constraints, and lithography simulation will be the key for driving the innovations for future technology generations.

Manish Sharma (Mentor Graphics, United States)
Shawn Blanton (CMU, United States)
Diagnosis Part 1 ( abstract )
Enamul Amyeen (Intel, United States)
Diagnosis Part 2 ( abstract )
Srikanth Venkataraman (Intel, United States)
Diagnosis Part 3 ( abstract )
Wednesday, November 1st

View this program: with abstractssession overviewtalk overview

08:30-10:00 Session 4: Dealing with Jitter and Leveraging Light
Bob Bartlet (Advantest Corporation, United States)
Sule Ozev (Arizona State University, United States)
Vahap Baris Esen (Katholieke Universiteit Leuven, Belgium)
Anthony Coyette (Katholieke Universiteit Leuven, Belgium)
Nektar Xama (Katholieke Universiteit Leuven, Belgium)
Wim Dobbelaere (On Semiconductor, Belgium)
Ronny Vanhooren (ON Semiconductor, Belgium)
Georges Gielen (Katholieke Universiteit Leuven, Belgium)
Nonintrusive Detection of Defects in Mixed-Signal Integrated Circuits Using Light Activation ( abstract )
Li Xu (Texas Instrumentation, United States)
Degang Chen (Iowa State University, United States)
Yuming Zhuang (Iowa State University, United States)
Kenneth Butler (Texas Instruments, United States)
Rajavelu Thinakaran (Texas Instruments, India)
Accurate ADC Testing with Significantly Relaxed Instrumentation Including Large Cumulative Jitter ( abstract )
Masahiro Ishida (ADVANTEST Corporation, Japan)
Kiyotaka Ichiyama (ADVANTEST Corporation, Japan)
A Jitter Separation and BER Estimation Method for Asymmetric Total Jitter Distributions ( abstract )
08:30-10:00 Session 5: Cell and Bridging ATPG
Andreas Glowatz (Mentor Graphics, Germany)
Vivek Chickermane (Cadence Design Sstems, United States)
Arani Sinha (Intel, United States)
Sujay Pandey (Georgia Institute of Technology, United States)
Ayush Singhal (Intel, United States)
Alodeep Sanyal (Intel, United States)
Alan Schmaltz (Intel, United States)
DFM-aware Fault Model and ATPG for Intra-Cell and Inter-Cell Defects ( abstract )
Masayuki Arai (Nihon University, Japan)
Shingo Inuyama (Tokyo Metropolitan University, Japan)
Kazuhiko Iwasaki (Tokyo Metropolitan University, Japan)
Layout-aware 2-Step Window-based Pattern Reordering for Fast Bridge/Open Test Generation ( abstract )
Irith Pomeranz (Purdue University, United States)
Selecting Target Bridging Faults for Uniform Circuit Coverage ( abstract )
08:30-10:00 Session 6: Security
Jennifer Dworak (Southern Methodist University, United States)
Adib Nahiyan (University of Florida, United States)
Mehdi Sadi (University of Florida, United States)
Rahul Vittal (Univesity of Floroda, United States)
Gustavo Contreras (University of Florida, United States)
Domenic Forte (University of Florida, United States)
Mark Tehranipoor (University of Florida, United States)
Hardware Trojan Detection Through Information Flow Security Verification ( abstract )
Rana Elnaggar (Duke University, United States)
Krishnendu Chakrabarty (Duke University, United States)
Mehdi Tahoori (Karlsruhe Institute of Technology, Germany)
Run-Time Hardware Trojan Detection Using Performance Counters ( abstract )
Jiafan Wang (Texas A&M University ECE Department, United States)
Congyin Shi (Texas A&M University ECE Department, United States)
Adriana Sanabria-Borbon (Texas A&M University ECE Department, United States)
Edgar Sanchez-Sinencio (Texas A&M University ECE Department, United States)
Jiang Hu (Texas A&M University ECE Department, United States)
Thwarting Analog IC Piracy via Combinational Locking ( abstract )
08:30-10:00 Session 7: Memory and 3D Test
Anne Gattiker (IBM, United States)
Rob Aitken (ARM Ltd., United States)
Xiaoan Ding (University of Chicago, United States)
Xi Liang (University of Chicago, United States)
Yanjing Li (University of Chicago, United States)
Cross-Layer Refresh Mitigation for Efficient and Reliable DRAM Systems: A Comparative Study ( abstract )
Gherman Valentin (CEA, France)
Farjallah Emna (CEA, France)
Armani Jean-Marc (CEA, France)
Seif Marcelino (CEA, France)
Dilillo Luigi (LIRMM, France)
Improvement of the Tolerated Raw Bit-Error Rate in NAND Flash-based SSDs with the Help of Embedded Statistics ( abstract )
Raphael Robertazzi (IBM, United States)
Micheal Scheurman (IBM, United States)
Matt Wordeman (IBM, United States)
Shurong Tian (IBM, United States)
Christy Tyberg (IBM, United States)
Analytical Test of 3D Integrated Circuits ( abstract )
10:30-12:00 Session 8: Interfaces, iJTAG and DDR testing
Dave Armstrong (Advantest, United States)
Anita Pratti (Texas Instruments, United States)
Peter Sarson (ams AG, Austria)
Jeff Rearick (AMD, United States)
Use Models for Extending IEEE 1687 to Analog Test ( abstract )
Michael Laisne (Dialog Semiconductor, United States)
Hans Martin von Staudt (Dialog Semiconductor, United States)
Sourabh Bhalerao (Dialog Semiconductor, United States)
Mark Eason (Dialog Semiconductor, United States)
Single-Pin Test Control for Big A, little d Devices ( abstract )
Sergei Odintsov (Tallinn University of Technology, Estonia)
Artur Jutman (Testonica Lab, Estonia)
Sergei Devadze (Testonica Lab, Estonia)
Marginal PCB Assembly Defect Detection on DDR3/4 Memory Bus ( abstract )
10:30-12:00 Session 9: Delay Test and Quality
Mike Vachon (Cadence Design Systems, United States)
Janusz Rajski (Mentor Graphics, United States)
Nik Sumikawa (NXP, United States)
Matthew Nero (University of California, Santa Barbara, United States)
Li-C. Wang (University of California, Santa Barbara, United States)
Kernel-based Clustering for Quality Improvement and Excursion Detection ( abstract )
Ankush Srivastava (NXP Semiconductor India Pvt Ltd, India)
Adit Singh (Auburn University, United States)
Virendra Singh (Indian Institute of Technology (IIT) Bombay, India)
Kewal Saluja (University of Wisconsin, United States)
Exploiting Path Delay Test Generation to Develop Better TDF Tests for Small Delay Defects ( abstract )
Irith Pomeranz (Purdue University, United States)
POSTT: Path-oriented Static Test Compaction for Transition Faults in Scan Circuits ( abstract )
10:30-12:00 Session S3: Special Session: Emerging Topics in Security and Trust I
Jennifer Dworak (Southern Methodist University, United States)
Brian Dupaix (Air Force Research Lab, United States)
Test Opportunities to Reduce Time and Expertise Required to Assess (TERA) for Trust ( abstract )
Patrick Schaumont (Virginia Tech, United States)
Fault Injection Attacks and their Mitigation in Embedded Processors ( abstract )
An Chen (Semiconductor Research Corporation, United States)
Opportunities in Emerging Technologies for Hardware Security ( abstract )
10:30-12:00 Session S4: Special Session: Machine Learning in Testing Applications

Organizer: Peilin Song, IBM Research

Xiaowei Li (Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China, China)
Peilin Song (IBM, United States)
Xinli Gu (Huawei Technologies, Inc., United States)
Yu Huang (Mentor, A Siemens Business, United States)
The Emerging Applications of Machine Learning in Testing ( abstract )
Yiorgos Makris (UT Dallas, United States)
Enhanced Lithographic Hotspot Detection Through Design of Experiments ( abstract )
Rob Aitken (ARM, United States)
Opportunities in Machine Learning and Test ( abstract )
14:00-15:30 Session 10: DFT Architectures and Compression
Peter Wohl (Synopsys, United States)
Hardik Bhagat (Globalfoundries, India)
Saurabh Gupta (Southern Methodist University, Dallas, Texas, USA, United States)
Al Crouch (Amida Technology Solutions, Inc, Austin, Texas, USA, United States)
Jennifer Dworak (Southern Methodist University, Dallas, Texas, USA, United States)
Daniel Engels (Southern Methodist University, Dallas, Texas, USA, United States)
Increasing IJTAG Bandwidth and Managing Security through Parallel Locking-SIBs ( abstract )
Vivek Chickermane (Cadence Design Sstems, United States)
Krishna Chakravadhanula (Cadence Design Systems, United States)
Paul Cunningham (Cadence Design Systems, United States)
Brian Foutz (Cadence Design Systems, United States)
Dale Meehl (Cadence Design Systems, United States)
Louis Milano (Cadence Design Systems, United States)
Christos Papameletis (Cadence Design Systems, United States)
David Scott (Cadence Design Systems, United States)
Steev Wilcox (Cadence Design Systems, United States)
Advancing Test Compression to the Physical Dimension ( abstract )
Jerzy Tyszer (Poznan University of Technology, Poland)
Sylwester Milewski (Poznan University of Technology, Poland)
Nilanjan Mukherjee (Mentor Graphics, United States)
Janusz Rajski (Mentor Graphics, United States)
Jedrzej Solecki (Mentor Graphics, United States)
Justyna Zawada (Poznan University of Technology, Poland)
Full-Scan LBIST with Capture-per-Cycle Hybrid Test Points ( abstract )
14:00-15:30 Session ITC-A: ITC Asia Best Papers
Shi-Yu Huang (National Tsing Hua University, Taiwan, Taiwan)
Yu Huang (Mentor Graphics, United States)
Bing-Yang Lin (Mediatek, Taiwan)
Hsin-Wei Hung (NTHU, Taiwan)
Shu-Mei Tseng (NTHU, Taiwan)
Chi Chen (NTHU, Taiwan)
Cheng-Wen Wu (NTHU, Taiwan)
Highly Reliable and Low-Cost Symbiotic IOT Devices and Systems ( abstract )
Shuo-Lian Hong (National Cheng Kung University, Taiwan)
Kuen-Jong Lee (National Cheng Kung University, Taiwan)
A Run-Pause-Resume Silicon Debug Technique with Cycle Granularity for Multiple Clock Domain Systems ( abstract )
Matthew Beckler (Carnegie Melon University, United States)
Shawn Blanton (CMU, United States)
GPU-Accelerated Fault Dictionary Generation for the TRAX Fault Model ( abstract )
14:00-15:30 Session S5: Special Session:Emerging Topics in Security and Trust II
Ujjwal Guin (Auburn University, United States)
Naghmeh Karimi (University of Maryland Baltimore County (UMBC), United States)
Domenic Forte (University of Florida, United States)
Upgrade/Downgrade: A Perspective on Challenges and Opportunities in Overcoming the Legacy System Issue ( abstract )
Jeyavijayan Rajendran (Texas A&M University, United States)
Supply-Chain Risks in Additive Manufacturing ( abstract )
Krishnendu Chakrabarty (Duke University, United States)
Securing Chip-Scale Microbiology and Biochemistry: Attacks and Countermeasures for Microfluidic Biochips ( abstract )
14:00-15:30 Session TUT2: Automotive Embedded Tutorial
Leroy Winemberg (NXP, United States)
Christophe Eychenne (Bosch, France)
V Prasanth (Texas Instruments, India)
David Foley (Texas Instruments, United States)
Srivaths Ravi (Texas Instruments, India)
Part 1: Demystifying Automotive Safety and Security for Semiconductor Developer ( abstract )
Grigor Tshagharyan (Synopsys, Armenia)
Gurgen Harutyunyan (Synopsys, Armenia)
Yervant Zorian (Synopsys, United States)
Part 2: An Effective Functional Safety Solution for Automotive Systems-on-Chip ( abstract )
16:30-17:30 Session K2: Security Keynote: Ultra-low Energy Security Circuit Primitives for IoT Platforms, Sanu Mathew, Intel

Low-area energy-efficient security primitives are key building blocks for enabling end-to-end content protection, user authentication and data security in IoT platforms. This talk describes the design of security circuit primitives that employ energy-efficient circuit techniques with optimal hardware-friendly arithmetic for seamless integration into area/battery constrained IoT systems: 1) A 2040-gate AES accelerator achieving 289Gbps/W efficiency in 22nm CMOS, 2) Hardened hybrid Physically Unclonable Function (PUF) circuit to generate a 100% stable encryption key. 3) All-digital TRNG to achieve >0.99 min-entropy with 3pJ/bit energy-efficiency. The talk will also discuss design issues related to side-channel leakage of key information, and how they may be addressed during design of encryption circuits. Finally, the talk will touch upon existing challenges of maintaining the integrity of security circuits, while still enabling testability and post-silicon validation.



Sanu Mathew is a Senior Principal Engineer with the Circuits Research Labs at Intel Corporation, Hillsboro, Oregon, where he leads research & development of energy-efficient hardware accelerators for encryption & security. Sanu obtained his Ph.D. degree in Electrical and Computer Engineering from State University of New York at Buffalo in 1999. He holds 41 issued patents, with another 63 patents pending and has published over 77 conference/journal papers. He has been with Intel for the past 18 years.

Thursday, November 2nd

View this program: with abstractssession overviewtalk overview

09:00-10:30 Session 11: Functional and Software-based Test
Sounil Biswas (Altera, United States)
Prab Varma (Veritable, United States)
Ying Zhang (The School of Software Engineering, Tongji University, China)
Krishnendu Chakrabarty (Duke University, United States)
Huawei Li (Institute of Computing Technology, Chinese Academy of Sciences, China)
Jianhui Jiang (The School of Software Engineering, Tongji University, China)
Software-based Online Self-Testing of Network-on-Chip using Bounded Model Checking ( abstract )
Sonal Pinto (Virginia Tech, United States)
Michael S. Hsiao (Virginia Tech, United States)
RTL Functional Test Generation Using Factored Concolic Execution ( abstract )
Christopher Lukas (University of Virginia, United States)
Farah Yahya (University of Virginia, United States)
Ben Calhoun (University of Virginia, United States)
Modeling Trans-Threshold Correlations for Reducing Functional Test Time in Ultra-Low-Power Systems ( abstract )
09:00-10:30 Session 12: Die Inking, Test Chips and Aging
Glenn Colon-Bonet (Intel, United States)
John Carulli (GLOBALFOUNDRIES, United States)
Constantinos Xanthopoulos (The University of Texas at Dallas, United States)
Peter Sarson (ams AG, Austria)
Heinz Reiter (ams AG, Austria)
Yiorgos Makris (The University of Texas at Dallas, United States)
Automated Die Inking: A Pattern Recognition-based Approach ( abstract )
Zeye Liu (Carnegie Mellon University, United States)
Phillip Fynan (Carnegie Mellon University, United States)
Ronald Blanton (Carnegie Mellon University, United States)
Front-End Layout Reflection for Test Chip Design ( abstract )
Souhir Mhira (ST Microelectronics, France)
Vincent Huard (STMicroelectronics, France)
Ahmed Benhassain (STMicroelectronics, France)
Florian Cacho (STMicroelectronics, France)
David Meyer (STMicroelectronics, France)
Sylvie Naudet (STMicroelectronics, France)
Abhishek Jain (STMicroelectronics, India)
Chittoor Parthasarathy (STMicroelectronics, India)
Alain Bravaix (REER-ISEN, France)
ITC-India Best Paper: Cognitive Approach to Support Dynamic Aging Compensation ( abstract )
09:00-10:30 Session 13: Status Monitoring
Samy Makar (Stanford, United States)
Yanjing Li (University of Chicago, United States)
Shi-Yu Huang (National Tsing Hua University, Taiwan)
A Cloud-based Methodology for Online PVTA Monitoring ( abstract )
Shi Jin (Duke University, United States)
Zhaobo Zhang (Huawei Technologies Co. Ltd., United States)
Krishnendu Chakrabarty (Duke University, United States)
Xinli Gu (Huawei Technologies Co. Ltd., United States)
Changepoint-based Anomaly Detection in a Core Router System ( abstract )
Shi Jin (Duke University, United States)
Zhaobo Zhang (Huawei Technologies Co. Ltd., United States)
Krishnendu Chakrabarty (Duke University, United States)
Xinli Gu (Huawei Technologies Co. Ltd., United States)
Symbol-based Health-Status Analysis in a Core Router System ( abstract )
09:00-10:30 Session 14: Safety and Test for Automotive ICs
Oscan Ballan (Xilinx, United States)
Paolo Bernardi (Politecnico di Torino, Italy)
V Prasanth (Texas Instruments, India)
Rubin Parekhji (Texas Instruments (Bangalore), India)
Bharadwaj Amrutur (Indian Institute of Science, India)
Safety Analysis for Integrated Circuits in the Context of Hybrid Systems ( abstract )
Tal Kogan (Intel, Israel)
Yehonatan Abotbol (Inomize, Israel)
Gabriele Boschi (Intel, Italy)
Gurgen Harutyunyan (Synopsys, Armenia)
Itay Kroul (Intel, Israel)
Hanna Shaheen (Intel, Israel)
Yervant Zorian (Synopsys, United States)
Advanced Functional Safety Mechanisms for Embedded Memories and IPs in Automotive SoCs ( abstract )
Li-C. Wang (UCSB, United States)
Sebastian Siatkowski (UCSB, United States)
Chuanhe Shan (UCSB, United States)
Matthew Nero (UCSB, United States)
Nikolas Sumikawa (NXP, United States)
Leroy Winemberg (NXP, United States)
Some Considerations on Choosing an Outlier Method for Automotive Product Lines ( abstract )
11:00-12:00 Session K3: Keynote - Automotive

Presenter: Joachim Kunkel, General Manager, Synopsys, Inc., Corporate Staff

Title: Look mom! No hands!

Abstract: After many years of relying on established processes technology geometries, advanced automotive semiconductors, driven by assisted and autonomous driving systems, have recently joined the race to ever smaller semiconductor process technologies. If the massive functionality enabled by 16-nm and below FinFET semiconductor processes, combined with the new fault mechanisms they bring along, weren’t enough of a test and repair challenge, the automotive functional safety requirements add a whole other dimension to the problem. This talk discusses automotive test and repair requirements and solutions in the context of automotive functional safety from the perspective of a test automation tool and IP provider.

Bio:  Joachim joined Synopsys in 1994 and serves as general manager of the Solutions Group. In this capacity, he oversees the business unit responsible for Synopsys DesignWare intellectual property (IP). Before joining Synopsys, Joachim was co-founder of CADIS GmbH in Aachen, Germany. There, he served as managing director and performed myriad duties in engineering, sales, and marketing. Before co-founding CADIS he was a research assistant at the Aachen University of Technology, where he conducted research in system-level simulation techniques for digital signal processing, with special emphasis on parallel computing. Joachim holds an M.S.E.E. degree, the Dipl.-Ing. der Nachrichtentechnik, from the Aachen University of Technology.

14:00-15:30 Session P2: Hot Topic Virtual Panel - What does the Test Community really think about System-Level Test?

System Level Test is becoming a bit of a hot button topic at times.  The general sentiment with some is, "hate to have to implement System-Leve Test, but cannot live without it". In this "virtual panel" everyone can weigh in during this interactive session and share their opinion through the audience poll.  We will see what the Test community sees as the issues and challenges going forward.   We will raise the questions one by one providing some time for the everyone to answer in an online poll and then show the results real-time.

Paul Berndt (Test Consultant, United States)
14:00-15:30 Session P3: Yield Learning at the Crossroads – Test Chips to the Rescue?

Organizers: Enamul Amyeen, Shawn Blanton

Moderator: Enamul Amyeen


                   Rob Aitken, ARM

                   Shawn Blanton. CMU

                   Rao Desineni, Global Foundries

                   Doug Gerwitz, Intel

                   Bruce Cory, NViDIA

                   Mike Bourland, Qualcomm

Current approaches for test chip design does not fully reflect all the complexities of actual customer product ICs, therefore yield learning is becoming more dependent on product fails as opposed to test chips.  The capability of a test chip to capture real product issues may be diminishing as we move further and further into advanced process nodes.  Are test chips missing the mark, or is the fabrication process simply different when customer ICs are manufactured?

Enamul Amyeen (Intel, United States)
14:00-15:30 Session P4: Automotive Panel

Panel: Automotive Test & Reliability: Challenges or Opportunities 

Moderator: LeRoy Winemberg, NXP (US)

Organizer: Yervant Zorian, Synopsys (US)

While ensuring automotive test quality needs (DPPB) and meeting reliability levels and functional safety standards are major challenges today, could our embedded test & repair infrastructure become the new opportunity to address the multipurpose needs of automotive SoCs?  


O. Ballan, Xilinx (USA)

Gabriele Boschi, Intel (Italy)

Marco Casarsa, ST (Italy)

Christophe Eyschenne, Bosch (France)

Rubin Parekhji, Texas Instruments (India)

Leroy Winemberg, NXP Semiconductors (USA)

Yervant Zorian (Synopsys, United States)
14:00-15:30 Session S6: Special Session: Emerging IEEE Test Standards

Organizer: Jeff Rearick, AMD

The IEEE Test Technology Standards Committee oversees the entire lifecycle of the development of new standards in our field.  This session features three standards in three different stages of that lifecycle: one just completed and published, one in active development by a working group, and one just starting as a study group.  Respectively, the freshly-minted IEEE 1149.10 standard addresses the use of high-speed serial I/O interfaces to access scan and JTAG registers, the IEEE P1687.1 working group is defining how to connect 1687 networks to non-TAP device interfaces, and the study group is tackling analog test access and coverage issues.  The audience will receive an overview of the first standard and learn about the in-flight development details for the other two efforts.

Mike Ricchetti (Synopsys, United States)
Cj Clark (Intellitech, United States)
IEEE 1149.10-2017: Mapping JTAG and Scan onto Serial I/O Such As SERDES and SPI ( abstract )
Al Crouch (SiliconAid, United States)
IEEE P1687.1: Accessing 1687 Networks via Non-TAP Interfaces ( abstract )
Steve Sunter (Mentor Graphics, Canada)
IEEE Analog Test Coverage and Access: A New Study Group for Longstanding Problems ( abstract )