ABSTRACT. Methods increasing controllability to solve the problem of low fault coverage are in practice limited due to the excessive area overhead and being intrusive. This paper presents a non-intrusive controllability method based on external activation.

ABSTRACT. A new algorithm is proposed in this paper to accurately estimate the ADC performance with sampling clock jitter. This method does not require precise sampling clock and thus reduce the test cost.

ABSTRACT. This paper proposes an FFT-based jitter separation and a model-based BER-curve estimation technique for asymmetric total jitter distributions. Experimental results show that the proposed method can analyze jitter and BER-curves more accurately than existing methods.

ABSTRACT. This paper motivates a new test paradigm – a design-for-manufacturability hotspot-aware fault model to target intra-cell and inter-cell defects, and introduces a cell characterization flow that can be used to create patterns for DFM-aware faults.

ABSTRACT. We propose fast test pattern generation scheme for bridge and open faults, considering critical area. The proposed scheme applies commercial ATPG tools and takes 2-step window-based reordering.

ABSTRACT. This paper develops a procedure for bridging fault selection that addresses the need to provide a uniform coverage of the circuit in order to prevent areas with low coverage from resulting in test escapes.

ABSTRACT. We propose a novel framework to detect hardware Trojan inserted by untrusted 3PIP vendors. Our proposed framework is based on information flow security (IFS) verification which can detect any violation of IFS policies by Trojans.

ABSTRACT. We introduce a run-time hardware Trojan detection method that is applied to microprocessor cores. This approach detects Trojan activation by applying run-time anomaly detection to the streaming data from the performance counters of microprocessor core

ABSTRACT. A combinational locking technique is introduced to enhance analog IC security against piracy. The key idea is reconfigurable current mirror design using Satisfiability Modulo Theories. Its effectiveness is confirmed by simulations on analog IC designs.

ABSTRACT. We present a new cross-layer approach to efficiently mitigate DRAM refresh overheads, which enables reliable, energy-efficient, and scalable DRAM systems.

ABSTRACT. The tolerated bit error rate in Flash memories is improved with a statistical approach that estimates the remaining safe retention time of a page based on the number of retention errors and the retention age.

ABSTRACT. We will review results from a test site designed expressly to investigate 3D IC design, integration and test issues and discuss test methods used to support diagnostic test of 3D chips in a research environment.

ABSTRACT. Through four use cases, we describe how IEEE 1687 can be extended to handle Analog chips, including enhancements to ICL and PDL to facilitate the description of the components and actions involved in analog tests.

ABSTRACT. The paper presents a unique single wire P1687.1 like input developed by the authors for purposes of test. The paper will show how the wire was implemented in silicon and show actual test results.

ABSTRACT. DDR3/4 memory interface calibration mechanisms may mask PCBA delay faults. Bus operating margin analysis can still reveal their presence. We propose a method to check the operating margin discrepancies reusing the existing in-system memory controller.

ABSTRACT. This paper will introduce Kernel Based Clustering, a method for removing die in close proximity to fail clusters and detecting common clusters in terms of shape, region on the wafer and failure mode.

ABSTRACT. This paper shows that Path Delay Fault (PDF) test generation can be exploited to not only generate TDF tests more efficiently, but the resulting TDF test sets are also more compact with better SDD coverage.

ABSTRACT. This paper describes a static test compaction procedure for transition faults that preserves the lengths of the paths through which transition faults are detected in order to preserve the ability to detect small delay defects.

ABSTRACT. This talk describes how some of the artifacts from the component creation process can potentially be applied to produce quantifiable assessment results for trustworthiness of electronic components while simultaneously reducing the time required for evaluation.

ABSTRACT. In the Internet of Things, the cyber-world will use a huge number of small embedded computing elements to control and sense the real world. The integrity and trustworthiness of these embedded systems are crucial; their manipulation has direct consequences to the safety of the applications they support. We discuss the threat vector of fault injection attacks on these embedded systems. A fault injection attack is the deliberate insertion of a computation error or memory error. We highlight the use of fault injection as a versatile hacking tool to obtain device control and to extract secret data. The traditional technique, differential fault analysis, dates back almost two decades, and many effective variants have since been proposed. We show that fault attacks apply equally well to hardware as to software. We then discuss a generic countermeasure against fault injection attacks, based on micro-architecture enhancements and software support. The FAME (Fault Aware Microprocessor Extension) architecture uses sensors to capture fault injection and uses software to provide a user-defined fault response. We present a prototype ASIC design and preliminary testing data for fault attacks. We demonstrate that, compared to traditional redundancy based techniques, FAME has a lower overhead in area as well as in performance.

ABSTRACT. As the conventional CMOS scaling approaches fundamental limits, semiconductor research has focused on beyond-CMOS materials, devices, and architectures. For 35 years, the Semiconductor Research Corporation (SRC) has played a critical role in industry collaboration, research funding, and education. In the last decade, the Nanoelectronics Research Initiative (NRI) under SRC has explored numerous beyond-CMOS technologies and developed comprehensive methodologies to assess them. Although the research of emerging materials and devices has focused on their applications in the computing and memory space, some unique characteristics of these materials and devices may be utilized for hardware security primitives and solutions. These characteristics include switching polarity, hysteresis, or I-V curves that are tunable, randomness that is programmable and intrinsic to device mechanisms, logic switches that have built-in and variable retention, etc. These characteristics may be utilized effectively in logic encryption, camouflaging, true random number generator, physical unclonable functions, etc. Some promising emerging devices may provide a technology platform for energy-efficient, intelligent, and secure systems. Although emerging technologies have demonstrated feasibility for security applications and may enable more efficient solutions with enhanced functionalities, their reliability and robustness need to be carefully evaluated. It is important that these physical characteristics and implementations of security primitives are connected to system designs to be verified, assessed, and optimized. This presentation will discuss the opportunities and challenges of emerging technologies for hardware security and review relevant SRC programs, e.g., Trustworthy and Secure Semiconductors and Systems (T3S).

ABSTRACT. Machine learning has already been applied in different fields of EDA. In the testing area, it has been applied in data mining for yield learning, root cause analysis for years. Some recent research has applied it to test scheduling and DFT planning. In the near future, we will see more research and development of its applications in diagnosis or even ATPG. In this talk, we will discuss the machine learning applications in testing and predict its trending.

ABSTRACT. Continuous technology scaling and the introduction of advanced technology nodes in Integrated Circuit (IC) fabrication has exposed new manufacturability issues. Lithographic hotspots are one of such problems which are a result of complex process interactions. These hotspots are known to vary from design to design and foundries expect such hotspots to be predicted early and corrected in the design stage itself, as opposed to a process fix for every hotspot, which would be intractable. Various efforts have been made in the past to address this issue by using a known database of hotspots as a source of information. Most of these works use either Machine Learning (ML) or pattern matching techniques to identify and predict hotspots in new incoming designs. Often these methods suffer from high false-alarm rates and some of the main reasons for this are: (a) these methods are oblivious to the root cause of hotspots, and (b) non-availability of a large hotspot database to learn from. In this work, we try to address these issues by using a novel Design Of Experiments (DOE) approach. We analyze the effectiveness of proposed methods against the state-of-the-art on a 45nm process, using industry standard tools and designs.

ABSTRACT. Machine learning (ML) has enjoyed a great resurgence in the last few years as algorithms have improved and compute technology has advanced to the point where complex neural nets can be processed quickly enough to be useful aids to applications as diverse as image recognition, preventative maintenance, and design verification. With such success, it seems reasonable to expect that ML can be applied to test as well. This talk looks at lessons from nearby domains and gives suggestions on potential benefits and pitfalls.

ABSTRACT. A parallel IJTAG network provides high bandwidth access to the embedded instruments. A successful implementation requires designing parallel SIBs along with addressing new security challenges that arise with parallel Locking-SIBs.

ABSTRACT. Test Compression ratios are currently stalled at 100-200X. A new 2-dimensional physically-aware sequential CoDec design addresses the severe wiring congestion as well as the test coverage droop and pattern spike at the highest compression ratios.

ABSTRACT. The paper presents a novel LBIST scheme addressing test requirements of automotive electronics. It uses pseudorandom test patterns delivered in a test-per-clock fashion in conjunction with per-cycle-driven hybrid test points.

ABSTRACT. IOT has seen countless potential applications that can improve our lives dramatically, but after years of efforts by numerous companies and organizations, the beautiful dreams are yet to be realized. The main obstacles are cost and energy consumption constraints of the devices and systems, which still cannot be contained. As a step forward in improving the reliability and reducing the cost and energy consumption of IOT devices and systems, at ITC-Asia17 we proposed a high-level model for efficient design-space exploration, which is called the symbiotic system (SS) model. Based on that, we also proposed a quorum-sensing model for SS to improve the reliability of IOT systems that contain subsystems. Preliminary experimental result shows that it is possible for an IOT system to achieve low cost, low energy consumption, and high reliability. In this extended work we discuss more evaluation results, and show that by using quorum-sensing-based peer-repair, up to 97% of the faulty devices can be repaired even when the raw yield is only 30%. It shows that by adopting the proposed approach, there is hope in eliminating production test of symbiotic IOT devices in the future.

ABSTRACT. A novel run-pause-resume (RPR) debug methodology that can achieve complete cycle-level granularity of debug resolution for multiple clock domain systems is proposed. With this methodology one can pause the normal operation of a system at any cycle of any clock domain and resume the system without causing any data invalidation problem. Bidirectional transactions among different clock domains are analyzed and supported with this methodology. A debug platform with both breakpointsetup software and clock-gating hardware is developed. The former allows the user to setup the breakpoint and calculate the exact time to transmit the pause control signal. The latter converts the pause signal to appropriate gating signals for the circuits under debug and the clock domain crossing interface. Experimental results show that the hardware area overhead is very small and 100% debug resolution is achieved. The experimented circuits include an industrial JPEG decoder system, several open-source cores and a system containing three clock domains.

ABSTRACT. Legacy electronic systems are vital to commercial and government infrastructures, with many that were built in 1960’s and 1970’s still in use today. However, their long lifetimes cause a major problem for the organizations assigned to maintain them – obsolescence. Legacy electronic chips/software are typically no longer being fabricated/supported by the original component manufacturer/developer. In the case of hardware (HW), purchasing the original component from the market is time consuming and costly; a problem only exacerbated by the need to ensure that it isn’t fake or counterfeit. Although newer chips are likely to have better performance and less security issues/bugs, they are difficult to employ due to forward and backward compatibility issues between hardware, software (SW), and firmware (FW). Finally, reproducing the entire system is also nontrivial. As a result of company merges, migration of engineers between companies, and so forth, original hardware design files and/or software codes are often lost or unavailable. This presentation will provide a perspective on the challenges and opportunities that lay in overcoming the obsolescence issue through emerging technologies and advances in automation. It will also highlight the crucial roles that test, verification, validation, and hardware security communities can play in two different paths: (i) Upgrade where a legacy system’s HW and FW is automatically reverse engineered and re-produced from new elements with the goals of faithfully matching the functionality and parametric behavior of the original as well as improving security; and (ii) Downgrade where new chips are adapted to match the specification of previous generations and integrate them into legacy systems.

ABSTRACT. As 3D printing becomes even more pervasive and manufacturing times and costs continue to shrink, more businesses and consumers invest in this revolutionary technology. One of the countless benefits of this technology is the ability to localize production and reduce logistic costs for parts and materials. Despite its countless benefits, this new manufacturing paradigm also raises concerns about the trustworthiness of the process, especially since contemporary business models have switched to the globalization of the manufacturing process and supply chain over multiple (potentially untrusted) parties. In this work, we assess the risks of 3D printing, present multiple attacks on the process and provide a comprehensive taxonomy of different applicable threats. We further evaluate different detection methods over two attack scenarios using finite element analysis and physical testing with an ultrasonic and tensile test. 

ABSTRACT. Since microfluidics was introduced in the 1990s, there has been a considerable amount of work on biochip design and chip-scale adaptation of biomolecular protocols. However, security assessment and secure biochip design have not received much attention. Microfluidic biochips can be tampered with to modify the outcome of bioassays and to steal proprietary biomolecular protocols, thereby undermining the quality of and trust in laboratory analysis, healthcare, and the landscape of innovation in biotechnology. This presentation will identify threats, vulnerabilities, attacks, actors, and countermeasures for various microfluidic platforms. The speaker will also describe some recent proposals to secure microfluidic biochips from specific attacks.

ABSTRACT. Increasing electronics, software and connectivity drive two consumer concerns – “functional safety” and “security” in the advanced automotive systems today. This embedded tutorial dissects these concerns and translates them into semiconductor development requirements.

ABSTRACT. A functional safety solution based on multi-purpose built-in self-test and repair infrastructure for automotive SoCs is presented. This solution allows building a hierarchical network and managing it in multiple in-field test and repair modes.