ABSTRACT. High resolution ADCs employing full linearity sweep suffer from high test cost. Alternate fast test methods published do not check dynamic linearity errors accurately. This paper analyzes these errors and provides a solution.

ABSTRACT. We have developed a concurrent characterizing procedure to characterize all the channels simultaneously. Leveraging characterized data of sampled devices a locally gradient based optimization technique is developed to optimize the MIMO array performance is demonstrated.

ABSTRACT. This paper presents an on-chip ADC BIST solution based on an algorithm known as USER-SMILE. Adapted for efficient hardware implementation, the solution correlates well with traditional histogram test and gains the ADC additional 10dB THD/SFDR.

ABSTRACT. This paper presents built-in self-test (BIST) for Low Dropout Regulator (LDO). On-chip BIST system measures impulse response of closed-loop LDO and then calculates phase margin and closed-loop bandwidth of LDO.

ABSTRACT. High-resolution patterns are generally used to diagnose multiple chain failures. We have developed a new algorithm which can be used to diagnose multiple chains using compressed production test set only.

ABSTRACT. A test reordering algorithm is presented to improve scan chain diagnosis. Tests are reordered based on information derived from limited fail data for faulty units by an enhanced defect diagnosis procedure.

ABSTRACT. This work introduces a data-driven methodology for detecting systematic defects using layout-aware scan diagnosis data. The methodology focuses on ranking the most systematic defective signatures. It was applied on three 14nm products for evaluation.

ABSTRACT. This paper presents a new Multiple Device Diagnosis (MDD) system to significantly improve the throughput of volume diagnosis by performing diagnosis on groups of failing devices.

ABSTRACT. We present a novel frequency scaled segmented scan architecture to alleviate the impact of both peak and average scan shift power in low power industrial designs without any impact to overall test-application time.

ABSTRACT. We describe a configurable switching network called the Scan Routing Fabric which connects a subset of a large number of scan channels to a small number of SOC pins and facilitates optimal pattern scheduling.

ABSTRACT. We address several challenges to achieve highest structural test quality for the designs with dual-edge triggered flip-flops. The experimental results on modified ISCAS-89 and ITC-99 circuits demonstrate the effectiveness of the proposed strategies.

ABSTRACT. Excessive IR-drop around clock buffers can corrupt test data during scan-shift. We assess this corruption risk and show that a few targeted pattern changes and maskings improve shift safety and test time significantly.

ABSTRACT. DFT methodologies have moved to closer integration with Physical Design to reduce total cycle time in chip design. The geometry of the ASIC could play a pivotal role in DFT strategy and architecture.

ABSTRACT. A low-cost method is presented for separating and estimating noise and aperture jitter of the ADC, and random clock jitter, while eliminating the need for coherent sampling. This enables accurate estimation of ADC specifications.

ABSTRACT. Since its inception as a working group in December 2016, IEEE P1687.1 made progress on multiple fronts. This poster discusses this progress in detail.

ABSTRACT. As IJTAG adoption increases across advanced semiconductor devices, there is need for a standard approach to debugging and interacting with IJTAG instruments. A new approach is demonstrated, which interfaces standard DFT tools with standard ATE.

ABSTRACT. During much of the ATE time for memory diagnosis, the MBIST controllers are idle, waiting for the ATE. A new hardware component allows the ATE to take action asap, reducing ATE test time.

ABSTRACT. Successful IP yield learning requires IP design data. Barriers exist to connect knowledge found Design, Fab and Test. We suggest setting up a data exchange that guarantees security and payment thus facilitating sharing IP knowledge.

ABSTRACT. We will discuss a newly developed approach and its impact on a test and product engineer’s ability to isolate faults early in the product lifecycle.

ABSTRACT. Hierarchical designs having > 2 levels of physical design hierarchies introduces its own complexities. This poster will show how to avoid adding redundant wrapper cells when signals go straight through multiple levels of physical hierarchies.

ABSTRACT. In this paper, we evaluate the effectiveness of the TRAX fault model to diagnose multiple early-life and wear-out failures, through a series of on-chip diagnosis experiments.

ABSTRACT. This poster describes a distributed mechanism for storing programmable data streams on-chip and providing repeatable on-demand data streams for Power-On Self-Test (POST) and Mission-Mode Self-Test (MMST) applications, critical for emerging markets and automotive standards.

ABSTRACT. An online electrical interconnect test method is proposed for assembled PCB circuits. Interconnects between ICs and a PCB are tested by an electrical test after shipping by adding a mode to the IEEE114.9 standard.

ABSTRACT. A unique test strategy for a particularly unusual and difficult to detect fail signature is presented. Statistical analysis techniques/results of extensive characterization across temperature, voltage, process, and the various IP on the device is summarized.

ABSTRACT. This work proposes a pre-bond TSV test technique based on operational transducer amplifier (OTA) to detect both the micro-void and pinhole defects in TSV at the same time.

ABSTRACT. This paper outlines a strategy, based on enhancement of TMR, for designing self-testing and self-repairing FPGAs and demonstrates the approach as applied to arrays of benchmark MSI and LSI logic blocks.

ABSTRACT. An inverse temperature dependence VMIN outlier screen is developed as a key enabler of cold test elimination. This outlier screen dynamically sets voltage of test to account for natural process variation.

ABSTRACT. New structural testing challenges include huge design performing In-System-Testing continuously, identifying silicon failures during operation. Addressing these challenges is done through Hierarchical DFT combined with Hybrid EDT-LBIST system containing configurable chain length.

ABSTRACT. We present a novel, area-efficient parallel memory self-test architecture to reduce the test time and thereby reducing the overall system boot-time while honoring the functional power constraints that results in >5X test time reduction.

ABSTRACT. An algorithm for getting efficient first time right clock domain groups for at-speed test for complicated designs. Automating algorithm has saved days of manual grouping efforts and ATPG re-spins due to human errors.

ABSTRACT. Using a 28nm FD-SOI device, this paper shows that voltage scaling using PMB can only account for 85% of the variability in the measurements, while transition fault testing can account for 99% of that variability.

ABSTRACT. The proposed method simultaneously decomposes periodic, ISI, and random jitters, using Boolean outputs from small, low-cost comparators instead of TIE data. Simulation and measurements demonstrate accuracy and cost-efficiency using significantly fewer samples than conventional methods.

ABSTRACT. As we know, the LBIST mode pass/fail MISR signature is very complex to debug. To debug LBIST mode failures for Single stuck-at {SSA} or Transition fault {TF} failures, the Scan-Through-Tap {STT mode} is a very accurate methodology. In STT mode, all scan chains are hooked up in a single san chain and access via JTAG TDI/TDO pins. The good values of the scan cells in LBIST Capture mode are extract for the ATPG tool. The good value are compared with the scan unloaded values during the scan load-unload of long scan chain formed in STT mode.

ABSTRACT. In wafer map analysis, in order to detect systemic defects, we first need to describe the characteristics of uniform-defect pattern. A method is proposed that only two normalized parameters are used and transformed into a point in a new scatter plane. A bend in the scatter plane like the rainbow in the sky is found which is constituted from a set of wafer maps with various numbers of uniform defects generated from the Monte-Carlo Simulation. Given a wafer map, these two parameters are the total number of bad dice and the total number of contiguous lines covering the bad dice. Comparing to the results with pattern recognition, it is shown that the bend can be used to classify some parts of local clustering on the classified real wafer maps. Especially, in additional to the pattern of over-clustering, anti-clustering defects could be found in the real-world wafer maps.

ABSTRACT. We develop an algorithm that is used to generate minimal number of patterns for path delay test of integrated circuits using multi-cycle at-speed test. Existing algorithm generates a new pattern if the necessary assignments of the path conflict with the patterns in the pattern pool. In this work, we test the circuits in functional mode, where multiple functional cycles follow after the test pattern scan-in operation. Experiments show that K longest paths for a target gate which were not compacted in the first time frame were observed to be compacted in different time frames leading to the increase in paths per pattern.

ABSTRACT. Design for Test (DFT) plays an important and increasing role in testing large SOCs during manufacturing. Most designs aim for high test quality standards, but allow limited time for test insertion. This poster shows how we were able to achieve over 6x productivity improvement gains (turn-around time to insert DFT) by using hierarchical DFT implementation methods on a large SOC design even when layout was performed flat.

ABSTRACT. Nanometer technology has led to a drastic increase in operational frequency of semiconductor circuits. Consequently the performance of circuit becomes more vulnerable to delay variation. Ordinarily testing delay defects requires that the test vectors be applied to the circuit at its intended operating speed. However since high speed testers require capital investments testing for delay defects on a low cost/low speed tester requires special test application if existing test generation strategies are to be used. In this paper we describe how a new innovative service oriented test solution whose main goal is to reduce test development, debug and new silicon verification costs, is used by Qualcomm for testing delay faults in a design verification environment.

ABSTRACT. This paper Illustration how to perform trimming approach by multi-site execution, and demonstrate Pattern Based Binary Search to speed up trimming search methodology, the performance evaluation by V93000 ATE tester shows 80% test time improvement.

ABSTRACT. Twenty years after the first published A/MS benchmark circuits, this paper describes the first, publicly-available A/MS benchmark circuits that include realistic process models with corners, netlists for common A/MS and digital cells, specifications, and testbenches.

ABSTRACT. We present a software library and API for parsing the IJTAG benchmarks (ICL) and building/exporting network models to target formats enabling easy integration into arbitrary SW packages. We also provide simple PDLs for retargeting experiments.

ABSTRACT. Ever since ISCAS’85, benchmarks have driven research into ATPG and other aspects of testing. We will give a brief history, show how results were presented before 1985, and give my experience in being on the ISCAS’89 panel and putting together the ITC’99 benchmarks. We will also give some of the advantages and problems of using benchmarks to drive research.

ABSTRACT. Latent defects are an important source of analog field failures. Novel defect-oriented methods are investigated to replace the traditional performance-based analog testing and “defect activation coverage” is introduced as an effective figure of merit.

ABSTRACT. Functional based Testing involve long test times and development times. Efforts have been associated with reducing test times or improving accuracy. We will discuss a few avenues for further investigation to enhance screening for defects.

ABSTRACT. In this talk, the pros and cons of specification vs. defect driven testing of AMS circuits will be discussed. Possible cost-effective test scenarios for a range of future products will be discussed.

ABSTRACT. In this thesis, new soft error detection solutions have been proposed exploiting existing debug infrastructures in processor-based systems. Meanwhile, Single Event Effects analysis and mitigation solutions have been proposed for SRAM- and Flash-based FPGA devices.

ABSTRACT. This paper proposes several accurate and robust algorithms to relax the stringent test requirements of high precision data converters, and to reduce the test cost while maintaining the test efficiency, accuracy without precision test instrumentation.

ABSTRACT. 3D integration based on through-Silicon-Via (TSV) is an emerging area in semiconductor industry. Effective test architecture optimization techniques are essential to minimize the manufacturing test cost. This paper addresses test architecture optimization and DfT for 3D ICs.