Program for Tuesday, October 31st: Talk View

PROGRAM FOR TUESDAY, OCTOBER 31ST: TALK VIEW

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9:00

9:30

10:00

10:30

11:00

11:30

12:00

12:30

13:00

13:30

14:00

14:30

15:00

15:30

16:00

16:30

17:00

17:30

18:00

09:00-09:30 Plenary - opening session

09:30-10:30 Plenary Keynote: Testing Beyond the Green Light

14:00-14:30

Low-Cost Dynamic Error Detection in Linearity Testing of SAR ADCs

Nimit Jain, Nitin Agarwal, Rajavelu Thinakaran, Rubin Parekhji

14:30-15:00

Concurrent Built-in Test and Tuning of Beamforming MIMO Systems Using Learning-assisted Performance

Sabyasachi Deyati, Barry Muldrey, Abhijit Chatterjee, Byunghoo Jung

15:00-15:30

An On-Chip ADC BIST Solution and the BIST-enabled Calibration Scheme

X. Jin, T. Chen, M. Jain, A.K. Barman, D. Kramer, D. Garrity, R. Geiger, D. Chen

15:30-16:00

Built-in Self-Test for Stability Measurement of Low-Dropout Regulator

Jae Woong Jeong, Ender Yilmaz, Leroy Winemberg, Sule Ozev

14:00-14:30

Diagnosing Multiple Faulty Chains with Low-Pin Convolution Compressor Using Compressed Production Test

Subhadip Kundu, Kuldip Kumar, Rishi Kumar, Rohit Kapur

14:30-15:00

Test Reordering for Improved Scan Chain Diagnosis Using an Enhanced Defect Diagnosis Procedure

Srikanth Venkataraman, Irith Pomeranz, Shraddha Bodhe, Enamul Amyeen

15:00-15:30

Systematic Defect Detection Methodology for Volume Diagnosis: A Data Mining Perspective

Chuanhe Shan, Pietro Babighian, Yan Pan, John Carulli, Li-C. Wang

15:30-16:00

High-Throughput Multiple Device Diagnosis System

S. Chillarige, A. Malik, S. Singh, J. Swenton, K. Chakravadhanula

14:00-14:30

Frequency-Scaled Segmented (FSS) Scan Architecture for Optimized Scan-Shift Power and Faster Test Application

W. Pradeep, P. Narayanan, R. Mittal, N. Maheshwari, N. Naresh

14:30-15:00

Maximizing Scan Pin and Bandwidth Utilization with a Scan Routing Fabric

G. Giles, J. Rearick, G. Li, J. Schulze, Y. Dong, J. Wingfield, T. Wood

15:00-15:30

On Applying Scan-based Structural Test for Designs with Dual-Edge Triggered Flip-Flops

Xijiang Lin

15:30-16:00

Analysis and Mitigation of IR-Drop-Induced Scan Shift-Errors

Holst, Schneider, Kawagoe, Kochte, Miyase, Wunderlich, Kajihara, Wen

14:00-14:04

Interstitial DFT in SpeedCore™

Raghuraman Rajanarayanan, Adam Cron

14:04-14:08

A Low-Cost Jitter Separation and ADC Spectral Testing Method Without Requiring Coherent Sampling

Shravan K Chaganti, Li Xu, Degang Chen

14:08-14:12

Quo Vadis IJTAG.1?

Martin Keim, Al Crouch, Michael Laisne

14:12-14:16

Scaling Interactive IJTAG Debug Beyond the Desktop to ATE

Matthew Knowles, Givargis Danialy, Marc Hutner

14:16-14:20

Reducing Memory BIST ATE Test Time Through a Data-ready Observation Port modeled in IJTAG

Chen, Sharma, Romain, Meier, Cote, Nadeau-Dostie, Au, Keim

14:20-14:24

An Immodest Proposal to Bridge Test and Design Data for SoC and IP Yield

Anne Meixner, Keith Arnold

14:24-14:28

Taming of the Shmoo

Wesley Smith, Steven McDowall, Marc Hutner

14:28-14:32

Technique to Test Hierarchical Designs with Multiple Design Levels

Vidya Neerkundar, Henrik Bergendal

14:32-14:36

Evaluation of Transition-X Fault Model for On-Chip Diagnosis of Multiple Defects

Matthew Beckler, Shawn Blanton

14:36-14:40

BIST On-demand Using Distributed On-Chip Programmable Data Streams

Carl Wisnesky Ii, Patrick Gallagher

14:40-14:44

Online Electrical Interconnect Test Method Utilizing IEEE 1149.1 Architecture

Daisuke Yabui, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu

14:44-14:48

Development of a Production-worthy ATE Test Screen for a Unique Device Fail Signature

Mike Lemanski, Kassem Hamze, Archana Jain

14:48-14:52

Testing TSVs for Micro-void and Pinhole Defects Using OTA

Procheta Chatterjee, Surajit Kumar Roy, Hafizur Rahaman, Chandan Giri

14:52-14:56

Self-Test and Self-Repair Method for FPGAs

David Keezer, Jingchi Yang

14:56-15:00

A VMIN Temperature Shift Outlier Screen for Cold Test Elimination

Todd Jacobs, William Morris, Sharon Levy

15:00-15:04

Hierarchical Hybrid EDT-LBIST System

Tal Kogan, Amihay Rabenu, Tal Frucht

15:04-15:08

A Hierarchical, Power-safe, Parallel Memory Self-Test Architecture for In-Field Test

V.R. Devanathan, Sumant Kale

15:08-15:12

Automatic Solution to Frame-Clock-Domain Groupings for Efficient At-Speed Structural Testing

Hardik Bhagat, Greeshma Jayakumar

15:12-15:16

Transition Fault Testing for Offline Adaptive Voltage Scaling

Mahroo Zandrahimi, Philippe Debaud, Armand Castillejo, Zaid Al-Ars

15:16-15:20

A Comparator-based Method for Decomposition of Random and Data-dependent Jitter in High-Speed Data

Yan Duan, Hsinho Wu, Masashi Shimanouchi, Mike Peng Li, Degang Chen

15:20-15:24

A Method to Debug LBIST-Mode SSA/TF Silicon Failure Accurately Using Scan-Through-TAP (STT) Mode

Vinay Kumar, Adam Cron

15:24-15:28

The Rainbow Transformed from a Set of Uniform-Defect Wafer Maps

Ya-Syuan Wu, Ching-Ju Lin, Jwu E Chen, Hsing-Chung Liang

15:28-15:32

Multicycle At-Speed Test

Mallika Pokharel, Duncan Walker

15:32-15:36

Productivity Gains with Hierarchical DFT Methodology for Physically Flat Design – A Case Study

Jonathan Phelps, Vidya Neerkundar

15:36-15:40

Delay Fault Testing Using Cloud Testing Service

A.T Sivaram, Oyama Yasuji, Sam El Alam, Arul Subbarayan

15:40-15:44

Multisite PMIC Fast Trimming with Pattern-based Search Function

Kevin Fan

16:30-17:00

A/MS Benchmark Circuits for Comparing Fault Simulation, DFT, and Test Generation Methods

Stephen Sunter, Peter Sarson

17:00-17:30

Doing more with ITC'2016 IEEE 1687 Benchmarks: Ecosystem and PDLs

Sergei Devadze, Artur Jutman, Anton Tsertov, Jeff Rearick

17:30-18:00

A Third of a Century of ATPG Benchmarks

Scott Davidson

16:30-17:00

Testing for Latent Defects in the Analog: Does the Spec. Matter?

Wim Dobbelaere

17:00-17:30

Functional vs. Defect-based Testing in Context of Analog Mixed-Signal Blocks

Mike Ales

17:30-18:00

Advanced Test Methods for Mixed-Signal Circuits: Specification vs. Defect-based Test

Abhijit Chatterjee

16:30-17:00

Fault-tolerant Electronic System Design

Boyang Du, Luca Sterpone

17:00-17:30

Accurate and Robust Spectral Testing with Relaxed Instrumentation Requirements

Yuming Zhuang, Degang Chen

17:30-18:00

Design-for-Test and Test Optimisation for 3D SOCs

Surajit Kumar Roy

16:30-17:00

Diagnosis Part 1

Shawn Blanton

17:00-17:30

Diagnosis Part 2

Enamul Amyeen

17:30-18:00

Diagnosis Part 3

Srikanth Venkataraman