PROGRAM
Days: Sunday, November 3rd Monday, November 4th Tuesday, November 5th Wednesday, November 6th Thursday, November 7th
Sunday, November 3rd
View this program: with abstractssession overviewtalk overview
08:30-12:00 Session Tutorial T1: RANDOM PROCESS VARIATIONS, CIRCUIT TIMING MARGINALITIES AND SILENT DATA ERRORS
TTEP Tutorial by
Adit SINGH (Auburn University)
More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial1
Location: Sapphire 400
08:30-12:00 Session Tutorial T2: ENHANCING TRUSTWORTHINESS IN THE GLOBAL IC SUPPLY CHAIN
TTEP Tutorial by
Giorgio DI NATALE (TIMA - CNRS / Université Grenoble-Alpes / Grenoble INP)
More information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial2
Location: Sapphire 410
08:30-12:00 Session Tutorial T3: HIERARCHICAL AND TILE BASED DFT TECHNIQUES FOR AI AND LARGE SOC
TTEP Tutorial by
Lee HARRISON (Siemens EDA)
More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial3
Location: Sapphire 411
10:00-10:30 Session CB1: Tutorial Coffee Break
Tell your presenter to take a break
Location: Sapphire West Foyer
12:00-13:00Tutorial Lunch Break (Sapphire Terrace)
13:00-16:30 Session Tutorial T4: LLM-ASSISTED ANALYTICS IN SEMICONDUCTOR TEST
TTEP Tutorial by
Li-C. WANG (UC Santa Barbara)
More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial4
Location: Sapphire 400
13:00-16:30 Session Tutorial T5: AUTOMOTIVE FUNCTIONAL SAFETY USING PREDICTIVE MAINTENANCE
TTEP Tutorial by
Yervant ZORIAN, Jyotika ATHAVALE (Synopsys)
More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial5
Location: Sapphire 410
13:00-16:30 Session Tutorial T6: MIXED-SIGNAL DFT CHALLENGES AND SOLUTIONS
TTEP Tutorial by
Stephen SUNTER (Siemens EDA)
More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial6
Location: Sapphire 411
14:30-15:00 Session CB2: Tutorial Coffee Break
Tell your presenter to take a break
Location: Sapphire West Foyer
Monday, November 4th
View this program: with abstractssession overviewtalk overview
08:30-12:00 Session Tutorial T7: 3DIC ADVANCED PACKAGING, TEST & SLM
TTEP Tutorial by
Sandeep GOEL (TSMC), Yervant ZORIAN (Synopsys)
More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial7
Location: Sapphire 400
08:30-12:00 Session Tutorial T8: ARTIFICIAL INTELLIGENCE SAFETY
TTEP Tutorial by
Annachiara RUOSPO (Politecnico di Torino), Riccardo MARIANI (NVIDIA)
More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial8
Location: Sapphire 410
08:30-12:00 Session Tutorial T9: FUNCTIONAL TESTING TECHNIQUES
TTEP Tutorial by
Paolo BERNARDI (Politecnico di Torino)
More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial9
Location: Sapphire 411
10:00-10:30 Session CB3: Tutorial Coffee Break
Tell your presenter to take a break
Location: Sapphire West Foyer
12:00-13:00Tutorial Lunch Break (Sapphire Terrace)
13:00-16:30 Session Tutorial T10: UCIE 2.0 BASED MULTI-CHIPLETS DESIGN & TEST
TTEP Tutorial by
Debendra DAS SHARMA (Intel), Yervant ZORIAN (Synopsys)
More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial10
Location: Sapphire 400
13:00-16:30 Session Tutorial T11: COMPUTATION IN MEMORY: TECHNOLOGIES, DESIGN, TEST AND RELIABILITY
TTEP Tutorial by
Mehdi TAHOORI (Karlsruhe Institute of Technology)
More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial1
Location: Sapphire 410
13:00-16:30 Session Tutorial T12: IN-FIELD SYSTEM TEST & DEBUG
TTEP Tutorial by
Amit PANDEY (Amazon), Karthik NATARJAN (Synopsys), Sankaran MENON (Intel)
More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial12
Location: Sapphire 411
14:30-15:00 Session CB4: Tutorial Coffee Break
Tell your presenter to take a break
Location: Sapphire West Foyer
Tuesday, November 5th
View this program: with abstractssession overviewtalk overview
09:00-09:40 Session Plenary-Opening: Opening Ceremony and Award Presentations
Location: Sapphire-CDGH
11:45-13:30Lunch Break
14:30-15:30Coffee Break
15:30-17:30 Session A1: Short Papers - Industrial Practices
Location: Sapphire OP
| 15:30 | Handling Die-to-Die I/O Pads for 3DIC Interconnect Tests (abstract) |
| 15:50 | Probe Card Ground Noise Canceling Circuit (abstract) |
| 16:10 | Finding Faulty Components In a Live Fleet Environment – Short Paper (abstract) PRESENTER: Benson Inkley |
| 16:30 | Short Paper: Bus-based Packetized Scan Architecure Trade-offs for Hetrogeneous Multi-Die SoCs (abstract) PRESENTER: Hiroyuki Iwata |
| 16:50 | Scalable BIST for Linearity Testing of Sigma-Delta Modulators (abstract) PRESENTER: Krishna Pramod Madabhushi |
| 17:10 | Evaluating Vulnerability of Chiplet-Based Systems to Contactless Probing Techniques (abstract) |
15:30-17:30 Session B1: Short Papers - Pre/Post Silicon
Location: Sapphire KL
| 15:30 | From Hybrid to Integrated: The Evolution of DFT Integration in SoC Design at Intel (abstract) |
| 15:50 | Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing (abstract) |
| 16:10 | Functionally-Possible Gate-Exhaustive Bridging Faults (abstract) |
| 16:30 | Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States (abstract) |
| 16:50 | A Cell-aware Transistor State Stress Model and its Application for Quality Measurement (abstract) PRESENTER: Stephan Eggersglüß |
| 17:10 | Testing for aging in advanced SRAM : From front end of the line transistors to back end of the line interconnects (abstract) |
15:30-17:30 Session C1: Short Papers - ML Related
Location: Aqua Salon AB
| 15:30 | A Robust On-Chip Sensor for Online Monitoring of BTI-Induced Aging in Integrated Circuits (abstract) |
| 15:50 | Identifying Undetectable Defects Using Equivalence Checking (abstract) |
| 16:10 | Unsupervised Learning Provides Intelligence for Testing Hard to Detect Faults (abstract) |
| 16:30 | Wafer-View Defect-Pattern-Prominent GDBN Method Using Image-in-Image-out MetaFormer Variant (abstract) |
| 16:50 | Wafer2Spike: Spiking Neural Network for Wafer Map Pattern Classification (abstract) |
| 17:10 | FAT-RABBIT: Fault-Aware Training towards Robustness Against Bit-flip Based Attacks in Deep Neural Networks (abstract) |
15:30-17:30 Session D1: Short Papers - Emerging Technologies
Location: Aqua C
| 15:30 | Cross-Layer Reliability Evaluation of In-memory Similarity Computation (abstract) |
| 15:50 | Design-for-Test for Silicon Photonic Circuits (abstract) |
| 16:10 | Defects, Fault Modeling, and Test Development Framework for FeFETs (abstract) |
| 16:30 | Locked by Design: Enhancing White-box Logic Obfuscation with Effective Key Mutation (abstract) |
| 16:50 | Defect Analysis for FeFETs using a Compact Model (abstract) |
18:30-21:00 Welcome Reception
Location: Promenade
Wednesday, November 6th
View this program: with abstractssession overviewtalk overview
10:00-10:30Coffee Break
10:30-12:00 Session A2: Explainable AI
Location: Sapphire OP
| 10:30 | WM-Graph: Graph-Based Approach for Wafermap Analytics (abstract) |
| 11:00 | Boost CPU Turbo Yield Utilizing Explainable Artificial Intelligence (abstract) |
| 11:30 | A Fast, Statistical, Machine-learning Approach for Automotive Semiconductor Test Reduction (abstract) |
10:30-12:00 Session B2: ML Applications
Location: Sapphire KL
| 10:30 | Generation and Quality Evaluation of Synthetic Process Control Monitoring Data (abstract) |
| 11:00 | Safety-Guided Test Generation for Structural Faults (abstract) |
| 11:30 | E-SCOUT: Efficient-Spatial Clustering-based OUtlier detection through Telemetry (abstract) |
10:30-12:00 Session C2: Emerging Technologies
Location: Aqua Salon AB
| 10:30 | High-Bandwidth IJTAG over SSN (abstract) |
| 11:00 | SEC-CiM: Selective Error Compensation for ReRAM-based Compute-in-Memory (abstract) |
| 11:30 | qFD: Coherent and Depolarizing Fault Diagnosis for Quantum Processors (abstract) |
10:30-12:00 Session E2
Location: Cobalt 502
12:00-14:00Lunch Break (Poster Show on Exhibit Floor)
12:00-14:00 Session Poster: Poster Show
Location: Exhibit Hall-Sapphire ABEFIJMN
Memory BIST for Automotive Non-destructive Memory Testing (abstract) |
Shift-left approach for SSN Oriented design: Enabling Robust RTL-Based SOC Automated Validation flow for ATPG and Power-Up Sequence (abstract) |
Method for Diagnosing Clock Jitter Using FPGA (abstract) |
(Short Paper) Efficient Noise Injection Methodology for Sample and Hold Circuits in AMS Behavioral Models (abstract) |
Minimizing Probe Touchdown Route After First EDS Steps for Test Cost Reduction (abstract) |
Improved Silent Data Error Detection through Test Optimization using Reinforcement Learning (abstract) |
High-Performance ATPG with Loadable Nonscan Cells (abstract) |
Test Time Optimization: A Novel Staggered-capture Architecture Using A Token-passing Architecture (abstract) |
JTAG Protocol Aware Debug Tool for efficient debugging on V93K (abstract) |
Inline Full Test Flow Scoping Capability on V93K Smart Scale (abstract) |
Automation of PMU module using POP for TTR (abstract) |
Evolution of PXI(e) Test for Digital Solutions (abstract) |
UID Way Of End-To-End Specification Compliance And Data Analysis (abstract) |
Internally generated scan resets using OCC (abstract) |
Industrial application of IEEE P1687.2 for post-Si verification of a smart power device (abstract) |
Efficiency and Reliability Enhancement in Pre-Silicon Validation Lessons from ASIC Networking product (abstract) |
Bridging the EDA to ATE gap for mixed-signal with IEEE P1687.2 and P1450.1-2024 (abstract) |
Synergetic Pre- and Post-Silicon SLM Analytics for Reliable and Safe Automotive (abstract) |
Optimizing Mobile & Automotive GPUs with Streaming Fabric, SEQ/XLBIST, IEEE1687 and TSO.ai (abstract) |
Intel HDMT ATE Capabilities Poster (abstract) |
Solving Verification Challenges for Modern DRAM based Systems requiring Refresh and Refresh Management Compliance (abstract) |
Executable Tables, ‘Key’ Concepts Demonstrated Using DDR5 Speed Bin Example (abstract) |
Enhancing test quality for abutted designs with Logic BIST (abstract) |
Flexible Scan test Architecture with Scalable Bus in 2.5D/3D Packaged Chips (abstract) |
Optimizing ATE Resources for WLAN Rx PER Testing: A Cost-Effective Approach (abstract) |
A Novel Solution for Efficient Signal Pattern Debug of Complex Devices Interconnect (abstract) |
Accelerated 3D IC DFT Development using commercial multi-die solution (abstract) |
Improving WLAN Rx PER Test Efficiency for Increased ATE Yield (abstract) |
Solving Memory Subsystem Verification Challenges for Multi-Instance Designs. (abstract) |
Experimental Evaluation of Multi-Stage Jitter-Reduction Circuits for 54 GHz ATE Clocks (abstract) |
Automation to Speed up the process of Timing Closure of the IJTAG Network (abstract) |
Cell-aware Chain Diagnosis for Backside Power (abstract) |
Layout-aware Chain Diagnosis for Backside Power (abstract) |
AI Chip Testing: Transforming Challenges into Opportunities with AI/ML/LLM Technology (abstract) |
Driving deterministic In-System Test using Advanced Peripheral Bus (APB) (abstract) |
Enhanced Security Mechanism for 1687 Network (abstract) |
1687 Solution for Tiled Based Design with Feedthroughs (abstract) |
TDR-Based S-Parameter Estimation of Signal Transmission Line on ATE Utilizing Built-In Driver and Comparator (abstract) |
Improved area overhead with advanced memory dump and memory test automation for AI chips (abstract) |
Efficient Test port access to address test time (abstract) |
Effective detection of uncommon faults by SMarchCHKBvcd algorithm (abstract) |
Embedded Trace: A Key Enabler for Silicon Debug and Continuous Monitoring (abstract) |
Scalable Multi-Chiplet Test Solution Using IEEE 1838 (abstract) |
Test Chip Design for Small Delay Defect Diagnosis Based on C-testable Arrays and Mutually Orthogonal Latin Squares (abstract) |
14:00-15:30 Session A3: Advances in Pre-Silicon
Location: Sapphire OP
| 14:00 | Adaptive Diagnosis Points for 100% Chain Diagnosis Coverage (abstract) |
| 14:30 | Efficient Built-In Self-Test Scheme for Inter-Die Interconnects of Chiplet-Based Chips (abstract) |
| 15:00 | Delay Monitoring Under Different PVT Corners for Test and Functional Operation (abstract) |
14:00-15:30 Session B3: Advances in Post-Silicon
Location: Sapphire KL
| 14:00 | Effectiveness of Timing-Aware Scan Tests in Targeting Marginal Failures and Silent Data Errors in a Data Center Processor (abstract) |
| 14:30 | Small-Bridging-Fault-Aware Built-In-Self-Repair for Cycle-Based Interconnects in a Chiplet Design Using Adjusted Pulse-Vanishing Test (abstract) |
| 15:00 | A Fast and Efficient Graph-Based Methodology for Cell-Aware Model Generation (abstract) |
14:00-15:30 Session C3: Diagnosis and Prediction
Location: Aqua Salon AB
| 14:00 | Diagnosis of intermittent faults and corresponding algorithm development beyond 5nm technologies (abstract) |
| 14:30 | Diagnosis of Defects on Global Signals (abstract) |
| 15:00 | Predictive Testing for Aging in SRAMs and Mitigation (abstract) |
14:00-15:30 Session E3
Location: Cobalt 502
15:30-16:30Coffee Break
16:30-18:00 Session A4: RAM
Location: Sapphire OP
| 16:30 | MBIST-based MRAM defect screening for safety-critical applications (abstract) |
| 17:00 | Testing STT-MRAMs: Do We Need Magnets in our Automated Test Equipment? (abstract) |
| 17:30 | Robust Design-for-Testability Scheme for Conventional and Unique Defects in RRAMs (abstract) |
16:30-18:00 Session B4: HW Security
Location: Sapphire KL
| 16:30 | SECT-HI: Enabling Secure Testing for Heterogeneous Integration to Prevent SiP Counterfeits (abstract) |
| 17:00 | Test Data Encryption with a New Stream Cipher (abstract) |
| 17:30 | Towards Machine-Learning-based Oracle-Guided Analog Circuit Deobfuscation (abstract) |
16:30-18:00 Session C4: Scan
Location: Aqua Salon AB
| 16:30 | Scan SerDes for Multi-die Packages (abstract) |
| 17:00 | Digital Scan and ATPG for Analog Circuits (abstract) |
| 17:30 | Functional State Extraction Using Scan DFT (abstract) |
16:30-18:00 Session D4
Location: Aqua C
16:30-18:00 Session E4
Location: Cobalt 502
Thursday, November 7th
View this program: with abstractssession overviewtalk overview
09:30-14:00 Session JF: Job Fair
Job fair on the exhibit floor. Visit recruitment booths.
Chair:
Location: Exhibit Hall-Sapphire ABEFIJMN
10:00-10:30Coffee Break
10:30-12:00 Session A5: Industrial Case Studies
Location: Sapphire OP
| 10:30 | Power-Aware Test Scheduling for Memory BIST (abstract) PRESENTER: Michal Kepinski |
| 11:00 | Deterministic In-Fleet Scan Test for a Cloud Computing Platform (abstract) |
| 11:30 | A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS (abstract) |
10:30-12:00 Session B5: Industrial Case Studies
Location: Sapphire KL
| 10:30 | AI-Enabled Board Level Vibration Testing: Unveiling the Physics of Degradation (abstract) |
| 11:00 | Virtual Test Development Using Pre-Silicon Verification Environment (abstract) |
| 11:30 | Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard (abstract) |
10:30-12:00 Session C5: Automotive
Location: Aqua Salon AB
| 10:30 | LESER-2: Detailed Consideration in Latch Design under Process Migration for Prevention of Single-Event Double-Node Upsets (abstract) |
| 11:00 | A graph-based algorithm for RRAM address decoders testing (abstract) |
| 11:30 | TEACH: Outlier Oriented Testing of Analog/Mixed-Signal Circuits Using One-class Clustering in Hyperdimensional Spaces (abstract) |
10:30-12:00 Session D5
Location: Aqua C
12:00-13:30Lunch Break
13:30-15:00 Session A6
Location: Sapphire OP
13:30-15:00 Session B6
Location: Sapphire KL
13:30-15:00 Session C6
Location: Aqua Salon AB
13:30-15:00 Session D6
Location: Aqua C
15:00-15:30Main Conference Ends and Workshops Start