TTEP Tutorial by

Adit SINGH (Auburn University) 

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial1

TTEP Tutorial by

Giorgio DI NATALE (TIMA - CNRS / Université Grenoble-Alpes / Grenoble INP) 

More information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial2

TTEP Tutorial by

Lee HARRISON (Siemens EDA) 

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial3

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TTEP Tutorial by

Li-C. WANG (UC Santa Barbara) 

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial4

TTEP Tutorial by

Yervant ZORIAN, Jyotika ATHAVALE (Synopsys)

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial5

TTEP Tutorial by

Stephen SUNTER (Siemens EDA) 

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial6

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TTEP Tutorial by

Sandeep GOEL (TSMC), Yervant ZORIAN (Synopsys)

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial7

TTEP Tutorial by

Annachiara RUOSPO (Politecnico di Torino), Riccardo MARIANI (NVIDIA)  

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial8

TTEP Tutorial by

Paolo BERNARDI (Politecnico di Torino) 

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial9

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TTEP Tutorial by

Debendra DAS SHARMA (Intel), Yervant ZORIAN (Synopsys) 

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial10

TTEP Tutorial by

Mehdi TAHOORI (Karlsruhe Institute of Technology) 

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial1

TTEP Tutorial by

Amit PANDEY (Amazon), Karthik NATARJAN (Synopsys), Sankaran MENON (Intel)

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial12

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Moderators: Seoyeon Kim & Yu Su (UCSB) 

Panelists 

Teresa McLaurin - ARM

Jeff Rearick - AMD

Adam Cron - Synopsys

Steve Sunter - Siemens

Savita Banerjee - Meta

The test community has a long history of embracing diversity and joining forces to further the state of art in test technology. With full-lifecycle product engagement, the test ecosystem plays a pivotal role in a product's success. Hear from industry veterans who have built their careers fighting defects to ensure quality and reliability using tools they have shaped. Learn from their failures and derive inspiration from their resilience and commitment to develop the next generation of innovators. 

Shankar Krishnamoorthy

General Manager, EDA Group & Corporate Staff at Synopsys Inc

Title:  Test and Telemetry in the Age of Pervasive AI

See: https://www.itctestweek.org/2024-keynote-visionary-talks/

Transformative technologies from advanced DFT industry leader Siemens EDA

Ankur Gupta, Sr. Vice President and General Manager of Digital Design Creation Platform with Siemens EDA discusses Tessent as the foundation for a sustainable future plus introduces an important new product for in-system test.

Anurag Jindal, Head of DFX group at Ericsson, presents productivity gains using Tessent products.

Vishal Agarwal, Sr. Director, H/W Engineering with NVIDIA, explains how Tessent Streaming Scan Network is being used in their challenging designs.

Dan Trock, Principal Engineer with Amazon Web Services, Annapurna Labs, presents results on using in-system test technology on their silicon.

See: https://www.itctestweek.org/2024-keynote-visionary-talks/

Sriram Sankar

Director, Infrastructure at Meta

Title:  Herding Llamas:  Testing for AI at Hyperscale

See: https://www.itctestweek.org/2024-keynote-visionary-talks/

Platinum -1: Mastering Test: Strategies for the Semiconductor “Era of Complexity”

Presenter: Rich Lathrop, Sr. Director of Business Development, Advantest America

Advantest, a leading manufacturer of automatic test and measurement equipment, has been enabling leading-edge technology since 1954. Over the years, the company has seen various technology trends emerge in our industry, but none have grown as quickly as AI has in the last year. The high-performance devices that power AI are deeply complex, with dense circuitry and intricate designs that require specialized testing equipment. This presentation will detail how Advantest’s broad product portfolio and experienced global network of engineers provide a carefully cultivated test ecosystem to help our customers thrive in this new "age of complexity."

Platinum -2: Test & Silicon Health in the Age of AI & Multi-die Design

Presenter: Sri Ganta, Synopsys

Abstract:  The proliferation of silicon content in the age of pervasive AI means that design-for-test and silicon lifecycle management is more important than ever in the development of software-defined systems. This silicon to systems approach is also driving multi-die innovation to solve the challenges around scaling and complexity. In this presentation Synopsys will share thoughts on the future of semiconductor test and discuss how AI will continue to shape and streamline Synopsys’ innovative solutions.

Platinum -3: “Four Out of Five Machine Learning Projects will Fail. Here’s How to Improve Your Odds of Success.”

Presenter: Dan King, Customer Success Manager, Galaxy Semiconductor

 Much attention is given to Artificial Intelligence and Machine Learning in Manufacturing & Test.  However, recent studies have shown that approximately four out of five machine learning projects will fail to deliver meaningful results.   This is due in large part to a naïve misunderstanding of the amount of time and energy required to gather, clean, blend, filter, and otherwise prepare the raw data for analysis.  While Data Science is cool, the underappreciated but vital task of Data Engineering is a key component of the Data Analysis Value proposition.  In this presentation, we will provide examples from several industrial use cases in which we will share four fundamental Data Engineering tasks that are prerequisites for delivering meaningful results in a Machine Learning project.

Platinum-4: Paradigm Shift in Testing of the AI Super Chips

Presenter: Eugene Lin, Chroma

We have seen a paradigm change in making AI chips, from driving semiconductor process node to 18A and lower and the combination of chiplets using advanced packaging. Lots of new technologies have been brought to the world to make the new AI world possible. How about the paradigm shift in testing of those super chips? Traditional wafer test and final package test followed by system level test and burn-in, and in conjunction with chained chiplet-to-chiplet tests. We will talk about how Chroma provides tools to help customers maximize test coverage and improve product quality

Steve Hesley

Corporate Vice President at AMD

Title:  The Future of Computing Depends on You

See: https://www.itctestweek.org/2024-keynote-visionary-talks/

1. “UCIe-based Open Chiplet Ecosystem: Architecture of Test, Debug and Silicon Lifecycle Management” Gerald Pasdast, Intel, Debendra Das Sharma, Intel, Yervant Zorian, Synopsys

2. “Leveraging UCIe Interface for High-Speed Stack Testing of Chiplets in a 3D Stack”, Sandeep Goel, Ankita Patidar, Stanley John, Frank Lee, Min-Jer Wang, Daniel F.J. Yang (TSMC), Yervant Zorian, Manish Arora, Abhijeet Samudra^, Shaan Awasthi, Stelios Balalis, Velmurugan Pathervellaichamy^, Bharath Shankaranarayanan, Vidya Charan Chitti, Gurgen Harutyunian, Grigor Tshagharyan (Synopsys)

3. UCIe Testing challenges, Steve Ledford, Davide Appello, (TechnoProbe)

This panel will discuss different aspects of the challenges and complexities of 3DIC. Where are we today? When and how will this become mainstream and what will it take to be successful?

Panelists:

• DFT: Teresa McLaurin
• 3D Test/Packaging: Pamela Fulton
• FA: Lesly Endrinal

Talk 1: Lessons from Applied ML in Semiconductors, given by Sergio Mier, Senior Director of Qualcomm.

Talk 2: Can AI transform test?

Abstract: AI has been transformative in various fields such as computer vision, text translation, chatbots, protein structure prediction, etc. However, we have barely scratched the surface in the area of semiconductor test. In this talk, I will describe why AI has been extremely effective in some fields and what are the challenges that have prevented it from being transformative in the area of test so far. I will give an example from yield learning where we have been able to successfully apply AI and another example where we haven’t had much success.

Bio: Gaurav Veda is a ML Research Engineer at Siemens EDA for the past 7 years. He earned a BTech in Computer Science from IIT Kanpur, India. He did research in Machine Learning as a PhD candidate in the CS Department at Carnegie Mellon University. He left after 5 years with a Masters and joined an algorithmic trading firm in New York, applying techniques from statistics and ML to high frequency trading. After 6 years in HFT, he joined the Tessent group at Siemens to apply statistics and ML to problems in semiconductor test.

Talk 3: LLMs in Semiconductor Test, given by Li-C. Wang, UCSB

Title: How Important Is DPPM? But the Number Is Negligibly Small.

Coordinator: Rubin Parekhji (Texas Instruments, Bangalore).

Abstract: We are aware that chip DPPM (value in defective parts per million) affects Time 0 quality as well as eventually contributes to life-time FIT (failure in time). We are also aware that chip DPPM in 1s – 10s is now the baseline, as compared to 100s – 1000s a decade ago. Chips go into different applications, and applications are built on systems which integrate a large number of chips, often upto 100s – 1000s. This results in the individual chip being an important contributor to the system’s DPPM, with each chip DPPM now being forced to be only a small fraction, forcing chip targets like 1 DDPB (value in defective parts per billion), so that end system DPPM is still very small (sub-1 or sub-10 DPPM).

Title: Experiences Estimating Test Quality and Test Escape Rates by Kenneth Butler, Advantest.

Title: Balancing Quality and Cost Trade-offs to Meet DPPM Targets in Mixed-signal Microcontrollers by Shravan Chaganti, Jamal Sheikh and Santosh Kavalur, Texas Instruments.

Title: DPM in the High-Performance, Advanced Technology AI Processor World, By Phil Nigh, Broadcom.

Organizers : Saman Adham – TSMC (USA) and Erik Jan Marinissen – imec (Belgium)

Panelsts:

Phil Byrd – Micron (Idaho, USA)

Omer Dossani – Amkor Technology (Arizona, USA)

Darshan Kobla – Microsoft (Texas, USA)

Shu-Liang Nin – TSMC (Taiwan)

Mike Slessor – FormFactor (California, USA)

Lawrence van der Vegt – MPI Corporation (California, USA)

In recent years, chiplet-based design has emerged as a promising approach to overcome the limitations of traditional monolithic integrated circuits. This paradigm shift involves the partitioning of a complex system into smaller, individual chiplets that are placed side-by-side, to stacked on top of each other and interconnected to achieve the desired functionality as a single product. While chiplet-based design offers numerous advantages such as improved performance, scalability, and cost-effectiveness, it also presents unique challenges in testing and manufacturing.

However, the test community does not have their name for this type of chips. Is that because test engineers are not engaged yet with this technology or because the associated challenges are insurmountable? Can such chips be tested with conventional DfT and/or BIST infrastructure or do we need more? Furthermore, there are a lot of potential test stages: pre-bond, mid-bond, post-bond, and packaged test. Do we really need to test at all these moments or are there possibilities to optimize the test flow? To what extent is the DfT reusable at subsequent integration steps?

In this “special panel session”, a combination of a special session and a panel session, the speakers are selected to cover a wide range of roles in this industry-wide phenomenon. They each will present their insights into current and future challenges in a 10-minute talk, followed by a plenary panel session in which all speakers (and also you, the audience) have the opportunity to iron out any doubt there might still exist.

Mike Slessor

Chief Executive Officer at FormFactor Inc.

Title:  From the Shadows to the Spotlight – Probe’s Role in Enabling Electronics Industry Innovation

See: https://www.itctestweek.org/2024-keynote-visionary-talks/

Job fair on the exhibit floor. Visit recruitment booths.

JTAG IEEE 1687 – Upping the Game for the Next Decade

The IJTAG standard IEEE1687 has had wide adoption within the industry and is the most influential DfT standard since IEEE 1149.1. After 10 years the next generation is around the corner. It will do much more than just making incremental improvements based on feedback from users. So, the base standard is undergoing a major revision after its first decade. The P1687.1 extension got a refocus and P1687.2 is nearing its completion. The prime driver behind the revision and the extensions is to widen the application of the IJTAG standard principles to real-world challenges. The major developments of the past two years range from basic things like bidirectional signals and switches (relays) to the concept of transfer procedures that describe behavioural blocks (arbitrary low pin count test interfaces, A/D converters, etc.), supporting both the analog and the digital aspects of test. This is also the case for PDL, which got a major update to better match real-world test program behaviour. Stay tuned!

• IJTAG Family Update – Learn from the Children, Martin Keim, Siemens
• IJTAG Goes Real-World, Hans Martin von Staudt, Renesas
• ITJAG PDL2 Describes Real Test Programs, Jeff Rearick, AMD
• IJTAG.1 There and Back Again, a Databit’s “EHPIC” Journey, Michael Laisne, Renesas

1. “In-Field Test under PVT-Variations”, Hans-Joachim Wunderlich, University of Stuttgart
2. “Addressing SDC challenges with Silicon Lifecycle Management”, Yervant Zorian, Jyotika Athavale, Synopsys
3. "Silent Data Corruptions in AI Workloads - A Deep Dive", Harish Dattatraya Dixit, Meta

IEEE Standards – Keeping Up with the Moore’s

As the old panel title alluded to, IEEE Std 1149.1 is not dead. And neither is Moore’s Law. But clearly, industry is in the midst of turning a corner. Chiplets are modernizing Moore’s Law, and literally up-leveling it. What test methodologies need to change with it as chiplets come to the fore of the electronics design industry? The new buzzword in multi-die design is “interface.” Each chiplet will need to interface with another chiplet or the outside world. This session will educate you on what IEEE Std P1149.1 is (and is not) doing to keep up. Interfaced perfectly with 1149.1, IEEE Std P1838a is also adding and clarifying facilities to help access and test certain categories of 2.5D and 3D multi-die package content. That leaves a lot of interfaces to address. So, IEEE Std P3405 is defining a set of constructs to help test and repair all the interface connections between chiplets. Come to this session to get updated and educated about how these IEEE standards are keeping pace with industry’s new direction.

P1149.1: Alive and Kicking, Jason Doege, Siemens

P1838a: Asked and Answered, Adam Cron, Synopsys

P3405: Make it So, Sreejit Chakravarty, Ampere Computing

Moderator: Savita Banerjee, Sr. Manager, Meta

Panelists:

Rob Aitken, Program Manager, NAPMP CHIPS R&D Office

Yervant Zorian, Fellow & Chief Architect, Synposys

Jennifer Dworak, Texoma Semi Tech Hub Professor, ECE, SMU

Krishnendu Chakrabarty, CTO, SWAP Hub, DoD Professor, EECE, ASU

The CHIPS Act provided over $280 billion for advanced chip manufacturing, packaging, and workforce development. The latest NOFO is out, and the ideas are flowing. This special session assembles experts who are actively leading critical CHIPS workstreams. They will discuss the importance of this national initiative, the ecosystem that needs to be developed to ensure its goals are achieved as well as the challenges that need the broader tech community to support. See how you can contribute to this historic effort and join the conversation. 

1. Best Paper: Optimized Timing Aware ATPG for At-Speed Test of Cell Internal Faults, 

Authors: Aneri Jain (Google), Wilson Pradeep* (Google) and Andreas Glowatz (Siemens)

2. 1st Honorable Mention:   An FPGA based Emulation of Source Synchronous Protocol-Aware Timing Stress Test, 

Authors: Prrk Tirumalesu Manda*, Vinodh J Rakesh, Vasavi Ghanta and Jagadish Raju Krishna Raju

Affiliation: Infineon Technologies India Pvt. Ltd.