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15:30 | Handling Die-to-Die I/O Pads for 3DIC Interconnect Tests ABSTRACT. In a multi-die 3DIC system Dies are connected to each other & to external I/O at stack level though I/O pads, to handle signal load and give electrical protection. Number of D2D interconnects is growing fast to several hundred thousands, hence, it is critical to test I/O pads & interconnects at die & stack level for low DPM. In this paper, we present test challenges, DFT methods & EDA tool support for handling different types of I/O pads in IEEE 1838 compliant DFT implementation. |
15:50 | Probe Card Ground Noise Canceling Circuit ABSTRACT. During wafer testing with probe cards in Automatic Test Equipment (ATE), it is challenging to maintain a stable VDD-GND voltage supplied to the Device Under Test (DUT) due to fluctuations in GND voltage caused by the return current from the DUT. Typically, due to a lack of channels, the test equipment reads and corrects the VDD voltage based on the representative GND voltage at an intermediate point where power is supplied, rather than the ground of each individual DUT. As a result, if there is a change in the GND voltage of an individual DUT, the test equipment is unable to detect and adjust for it. To overcome these limitations, this study proposes a method of configuring a circuit within the probe card that allows for the use of existing equipment functions such as current measurement and open-short testing while correcting changes in the individual DUT GND voltage of sensitive power sources. |
16:10 | Finding Faulty Components In a Live Fleet Environment – Short Paper PRESENTER: Benson Inkley ABSTRACT. Over time, computing systems experience component failures. System administrators schedule regular maintenance sessions where diagnostics are run to find these failures. How often and how extensive of a test to run is a complex question involving many variables. Intel developed Intel® In-Field Scan, a feature that enables fast testing of processing cores without taking the node off-line. This paper discusses Intel In-Field Scan and key considerations regarding how often to test the processors. |
16:30 | Short Paper: Bus-based Packetized Scan Architecure Trade-offs for Hetrogeneous Multi-Die SoCs PRESENTER: Hiroyuki Iwata ABSTRACT. Choosing a DfT architecture for heterogeneous multi-core SoCs is constrained by various requirements. SSN is a bus-based packetized data distribution scan architecture designed to address these requirements. A comparison between SSN and previous hierarchical DfT approaches is shown. A specific project SoC requirements is reviewed with packetized scan delivery architecture trade-offs. Results show 2X scan data transfer rate while adhering to pinning, area and physical design constraints. |
16:50 | Scalable BIST for Linearity Testing of Sigma-Delta Modulators PRESENTER: Krishna Pramod Madabhushi ABSTRACT. Sigma Delta Modulators (SDMs) are widely used in implantable devices to process biological signals captured by the on-board sensors. The latest semiconductor trends have grown the sensor capacity and reduced test points on these devices which creates burden on test and rises a need for an in-field monitor. A scalable BIST scheme that uses a small circular buffer is implemented to test linearity of three SDMs in parallel and the performance has been compared to the traditional test methodology. |
17:10 | Evaluating Vulnerability of Chiplet-Based Systems to Contactless Probing Techniques ABSTRACT. Chiplets play an increasingly prominent role in large semiconductor designs. This paper evaluates the unique security vulnerabilities of their die-to-die communication circuits to contactless probing, and discusses the challenges of effective sensor-based mitigation. |
15:30 | From Hybrid to Integrated: The Evolution of DFT Integration in SoC Design at Intel ABSTRACT. This paper presents a case study on Intel’s SoC design, highlighting unique test and debug challenges not met by commercial software. SoC design growth has increased the cost of maintaining proprietary software, prompting a reevaluation of Intel’s DFT IP integration approach. With EDA software trending towards TCL shell-based, Intel has leveraged commercial software to integrate both proprietary and vendor-provided DFT IP. This paper introduces a new DFT integration solution as a resolution. |
15:50 | Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing ABSTRACT. Testing delay faults under PVT-variations is challenging due to self-heating in FinFET and technologies beyond. Temperature effect inversion is exploited in test generation and application to increase fault coverage with reduced test volume and time. |
16:10 | Functionally-Possible Gate-Exhaustive Bridging Faults ABSTRACT. The article defines a bridging fault model for hard-to-detect bridge defects, and focuses on faults that can affect the correct functional operation of the circuit. Such faults are important to detect since they can escape detection if not targeted, and cause silent data corruption. |
16:30 | Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States ABSTRACT. We propose DIG, a novel Dynamic Instruction Generator that leverages processor runtime states through an instruction set simulator to produce high-quality test instructions with valid semantics. DIG successfully uncovers previously unknown bugs in VeeR EH2. Our experimental results show that the number of instructions is reduced by as much as 62.50% and 86.11% compared to famous instruction generators, RISC-V DV and RISC-V Torture, respectively, while achieving superior functional coverage. |
16:50 | A Cell-aware Transistor State Stress Model and its Application for Quality Measurement PRESENTER: Stephan Eggersglüß ABSTRACT. Stress testing becomes more and more important with shrinking technology nodes to excite latent defects and reduce the infant mortality of ICs. This paper introduces a Cell-aware Transistor State Stress Model and a methodology to create a stress view for cell libraries as well as a flow to assess the quality of the stress test. This flow uses this cell-aware stress view during simulation to provide a stress coverage of the test set. Experiments show the quality of different test sets. |
17:10 | Testing for aging in advanced SRAM : From front end of the line transistors to back end of the line interconnects ABSTRACT. The long-term reliability of the SRAM is crucial for safety-critical applications. The transistor elements are vulnerable to negative bias temperature instability, and the interconnect is prone to electromigration. To comply with the safety-critical standards, understanding the combined transistor and interconnect aging mechanisms in the SRAM array and effective testing methods are required. Therefore, we perform a full aging analysis including FinFET and FDSOI. |