ABSTRACT. In a multi-die 3DIC system Dies are connected to each other & to external I/O at stack level though I/O pads, to handle signal load and give electrical protection. Number of D2D interconnects is growing fast to several hundred thousands, hence, it is critical to test I/O pads & interconnects at die & stack level for low DPM. In this paper, we present test challenges, DFT methods & EDA tool support for handling different types of I/O pads in IEEE 1838 compliant DFT implementation.

ABSTRACT. During wafer testing with probe cards in Automatic Test Equipment (ATE), it is challenging to maintain a stable VDD-GND voltage supplied to the Device Under Test (DUT) due to fluctuations in GND voltage caused by the return current from the DUT. Typically, due to a lack of channels, the test equipment reads and corrects the VDD voltage based on the representative GND voltage at an intermediate point where power is supplied, rather than the ground of each individual DUT. As a result, if there is a change in the GND voltage of an individual DUT, the test equipment is unable to detect and adjust for it. To overcome these limitations, this study proposes a method of configuring a circuit within the probe card that allows for the use of existing equipment functions such as current measurement and open-short testing while correcting changes in the individual DUT GND voltage of sensitive power sources.

ABSTRACT. Over time, computing systems experience component failures. System administrators schedule regular maintenance sessions where diagnostics are run to find these failures. How often and how extensive of a test to run is a complex question involving many variables. Intel developed Intel® In-Field Scan, a feature that enables fast testing of processing cores without taking the node off-line. This paper discusses Intel In-Field Scan and key considerations regarding how often to test the processors.

ABSTRACT. Choosing a DfT architecture for heterogeneous multi-core SoCs is constrained by various requirements. SSN is a bus-based packetized data distribution scan architecture designed to address these requirements. A comparison between SSN and previous hierarchical DfT approaches is shown. A specific project SoC requirements is reviewed with packetized scan delivery architecture trade-offs. Results show 2X scan data transfer rate while adhering to pinning, area and physical design constraints.

ABSTRACT. Sigma Delta Modulators (SDMs) are widely used in implantable devices to process biological signals captured by the on-board sensors. The latest semiconductor trends have grown the sensor capacity and reduced test points on these devices which creates burden on test and rises a need for an in-field monitor. A scalable BIST scheme that uses a small circular buffer is implemented to test linearity of three SDMs in parallel and the performance has been compared to the traditional test methodology.

ABSTRACT. Chiplets play an increasingly prominent role in large semiconductor designs. This paper evaluates the unique security vulnerabilities of their die-to-die communication circuits to contactless probing, and discusses the challenges of effective sensor-based mitigation.

ABSTRACT. This paper presents a case study on Intel’s SoC design, highlighting unique test and debug challenges not met by commercial software. SoC design growth has increased the cost of maintaining proprietary software, prompting a reevaluation of Intel’s DFT IP integration approach. With EDA software trending towards TCL shell-based, Intel has leveraged commercial software to integrate both proprietary and vendor-provided DFT IP. This paper introduces a new DFT integration solution as a resolution.

ABSTRACT. Testing delay faults under PVT-variations is challenging due to self-heating in FinFET and technologies beyond. Temperature effect inversion is exploited in test generation and application to increase fault coverage with reduced test volume and time.

ABSTRACT. The article defines a bridging fault model for hard-to-detect bridge defects, and focuses on faults that can affect the correct functional operation of the circuit. Such faults are important to detect since they can escape detection if not targeted, and cause silent data corruption.

ABSTRACT. We propose DIG, a novel Dynamic Instruction Generator that leverages processor runtime states through an instruction set simulator to produce high-quality test instructions with valid semantics. DIG successfully uncovers previously unknown bugs in VeeR EH2. Our experimental results show that the number of instructions is reduced by as much as 62.50% and 86.11% compared to famous instruction generators, RISC-V DV and RISC-V Torture, respectively, while achieving superior functional coverage.

ABSTRACT. Stress testing becomes more and more important with shrinking technology nodes to excite latent defects and reduce the infant mortality of ICs. This paper introduces a Cell-aware Transistor State Stress Model and a methodology to create a stress view for cell libraries as well as a flow to assess the quality of the stress test. This flow uses this cell-aware stress view during simulation to provide a stress coverage of the test set. Experiments show the quality of different test sets.

ABSTRACT. The long-term reliability of the SRAM is crucial for safety-critical applications. The transistor elements are vulnerable to negative bias temperature instability, and the interconnect is prone to electromigration. To comply with the safety-critical standards, understanding the combined transistor and interconnect aging mechanisms in the SRAM array and effective testing methods are required. Therefore, we perform a full aging analysis including FinFET and FDSOI.

ABSTRACT. Bias Temperature Instability(BTI) is an aging phenomenon in MOS transistors which is a critical concern for reliability of integrated circuits. This paper presents a robust sensor that allows for the direct monitoring of the BTI-induced threshold voltage change of MOS transistors. This sensor allows for a direct physical-to-digital conversion of the threshold voltage change. We also discuss a potential use case of proposed sensor for the online monitoring of an analog circuit.

ABSTRACT. The paper proposes a method for identifying undetectable defects to exclude them from further consideration in defect campaigns. The method uses an equivalence checker to generate counterexamples or prove the undetectability of a defect.

ABSTRACT. Combined signal data on input-output cone widths, reconvergences, and multiple testability measures with principal component analysis (PCA), an unsupervised learning technique, guides ATPG for unprecedented performance gain on hard to detect and redundant faults.

ABSTRACT. We utilized a denoising technique, a flexible input-size model, and a new training strategy to detect latent defects based on neighboring information. This approach reduced DPPM (defective parts per million) by 24%

ABSTRACT. In integrated circuit design, the analysis of wafer map patterns is critical to improve yield and detect manufacturing issues. Traditional deep neural networks, while effective, consume significant energy. We develop Wafer2Spike, an spiking neural network architecture that mimics biological neurons for energy-efficient classification. Tested on the WM-811k benchmark, it achieved a remarkable 98% accuracy, surpassing conventional methods and demonstrating the potential of SNNs.

ABSTRACT. Machine learning is increasingly used in crucial applications, often implemented in hardware. However, they are vulnerable to fault injection attacks, particularly bit-flipping. We introduce a low-cost defensive method, designed to prevent such adversarial threats. This method minimizes the impact of individual weights on the overall model output, reducing its sensitivity to the attack. The results confirm the high resilience of our method against bit-flipping in both software and hardware.

ABSTRACT. Similarity computation, widely used in various applications, can significantly benefit from emerging Compute-in-Memory (CiM) approaches utilizing non-volatile memory (NVM) technologies. However, the reliability of these technologies is often challenged by device non-idealities and characteristics. This study compares Current-based and Scouting-based Content-Addressable Memory for various NVM technologies and tests their error rates and robustness using various benchmarks.

ABSTRACT. This paper proposes a design-for-test (DFT) methodology and architecture for testing and validation of silicon photonic integrated circuits. We describe the design of silicon photonic circuits and components that comprise the proposed DFT architecture. The designs are extensively simulated and validated as test-access and fault-detection circuitry. We demonstrate how the DFT approach can be deployed on photonic integrated circuits and how they can be tested for correct operation, in terms of signal power and phase. The application is demonstrated on two distinct types of designs -- an optical neural network comprising optical devices in a feed-forward topology, and on a optical logic circuit with feedback loops.

ABSTRACT. This paper introduces a comprehensive framework for defect and fault modeling, enabling testing solutions to be developed. Firstly, an overview and classification of FeFET manufacturing defects are provided. Defects in contacts and interconnects, considered conventional defects, are modeled as resistors. However, unique defects are introduced in the FeFET fabrication. Therefore, the device-aware test (DAT) method is used to effectively model and analyze unique defects.

ABSTRACT. We propose an obfuscation technique designed to thwart behavioral reverse engineering of finite state machines, even when attackers possess the details of a functional netlist. The solution employs self-generated and mutating keys in a locking framework to hinder an attacker's ability to learn functionality beyond what sequential queries provide.

ABSTRACT. Ferroelectric (Fe) field-effect transistors (FeFETs) are promising emerging devices, but the impact of manufacturing imperfections on FeFETs has yet to be studied comprehensively. We extend a previous FeFET compact model to combine the Preisach Fe capacitor with the BSIM-SOI MOSFET model. We analyze polarization defects in the Fe layer using this compact model. We also present an analysis of device-level opens, shorts, coupling faults and process variations in a 1T-1FeFET cell.