ITC 2024: IEEE INTERNATIONAL TEST CONFERENCE

A
Abdalwahab, Mahmoud	Short Paper: Bus-based Packetized Scan Architecure Trade-offs for Hetrogeneous Multi-Die SoCs
Abel, Inga	Identifying Undetectable Defects Using Equivalence Checking
Addepalli, Hari	Delay Monitoring Under Different PVT Corners for Test and Functional Operation
Aderholz, Ernst	Virtual Test Development Using Pre-Silicon Verification Environment
Adjei, Daniel	A Robust On-Chip Sensor for Online Monitoring of BTI-Induced Aging in Integrated Circuits
Agarwal, Khushboo	Test Time Optimization: A Novel Staggered-capture Architecture Using A Token-passing Architecture
Agarwal, Vishal	A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS
Agnihotri, Pratishtha	Design-for-Test for Silicon Photonic Circuits
Agrawal, Vishwani	Unsupervised Learning Provides Intelligence for Testing Hard to Detect Faults
Alexandrescu, Dan	Synergetic Pre- and Post-Silicon SLM Analytics for Reliable and Safe Automotive
Allen, Ramsay	Synergetic Pre- and Post-Silicon SLM Analytics for Reliable and Safe Automotive
Amrouch, Hussam	Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing
Armstrong, David	Intel HDMT ATE Capabilities Poster
Arora, Manish	Handling Die-to-Die I/O Pads for 3DIC Interconnect Tests
Arora, Manish	Scalable Multi-Chiplet Test Solution Using IEEE 1838 1687 Solution for Tiled Based Design with Feedthroughs Enhanced Security Mechanism for 1687 Network Automation to Speed up the process of Timing Closure of the IJTAG Network
Asami, Koji	TDR-Based S-Parameter Estimation of Signal Transmission Line on ATE Utilizing Built-In Driver and Comparator
Atol, Quint	Virtual Test Development Using Pre-Silicon Verification Environment
Au, Albert	Memory BIST for Automotive Non-destructive Memory Testing Power-Aware Test Scheduling for Memory BIST
Aziza, Hassen	Robust Design-for-Testability Scheme for Conventional and Unique Defects in RRAMs
B
B. Tahoori, Mehdi	Cross-Layer Reliability Evaluation of In-memory Similarity Computation MBIST-based MRAM defect screening for safety-critical applications Testing for aging in advanced SRAM : From front end of the line transistors to back end of the line interconnects
Bahrami, Javad	FAT-RABBIT: Fault-Aware Training towards Robustness Against Bit-flip Based Attacks in Deep Neural Networks
Bakhtavari Mamaghani, Sina	MBIST-based MRAM defect screening for safety-critical applications
Balajiram, Vishnu	Improving WLAN Rx PER Test Efficiency for Increased ATE Yield Optimizing ATE Resources for WLAN Rx PER Testing: A Cost-Effective Approach
Banerjee, Sanmitra	Safety-Guided Test Generation for Structural Faults
Baptist, Bernhard	Virtual Test Development Using Pre-Silicon Verification Environment
Barondeau, Olivier	Industrial application of IEEE P1687.2 for post-Si verification of a smart power device
Bauer, Joseph	Executable Tables, ‘Key’ Concepts Demonstrated Using DDR5 Speed Bin Example
Bauwens, Peter	Bridging the EDA to ATE gap for mixed-signal with IEEE P1687.2 and P1450.1-2024
Bhatt, Suketu	Efficient Test port access to address test time
Biyani, Gourav	Accelerated 3D IC DFT Development using commercial multi-die solution
Blair, Steve	Design-for-Test for Silicon Photonic Circuits
Bommana, Ashish Reddy	SEC-CiM: Selective Error Compensation for ReRAM-based Compute-in-Memory
Brenroth, Ofri	Shift-left approach for SSN Oriented design: Enabling Robust RTL-Based SOC Automated Validation flow for ATPG and Power-Up Sequence
Bucksch, Thorsten	Industrial application of IEEE P1687.2 for post-Si verification of a smart power device
Burchard, Jan	High-Bandwidth IJTAG over SSN
C
Callahan, Tim	High-Bandwidth IJTAG over SSN
Cantoro, Riccardo	Defects, Fault Modeling, and Test Development Framework for FeFETs
Carulli, John	Generation and Quality Evaluation of Synthetic Process Control Monitoring Data
Cauwels, Heleen	Bridging the EDA to ATE gap for mixed-signal with IEEE P1687.2 and P1450.1-2024
Chai, Hung Ho	High-Bandwidth IJTAG over SSN
Chakrabarty, Krishnendu	SEC-CiM: Selective Error Compensation for ReRAM-based Compute-in-Memory Safety-Guided Test Generation for Structural Faults E-SCOUT: Efficient-Spatial Clustering-based OUtlier detection through Telemetry Defect Analysis for FeFETs using a Compact Model
Chand, Manish	Solving Memory Subsystem Verification Challenges for Multi-Instance Designs.
Chandra, Anshuman	Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard
Chang, Daehyun	Minimizing Probe Touchdown Route After First EDS Steps for Test Cost Reduction
Chang, Shuo-Wen	Wafer-View Defect-Pattern-Prominent GDBN Method Using Image-in-Image-out MetaFormer Variant
Chao, Chia-Tso	Wafer-View Defect-Pattern-Prominent GDBN Method Using Image-in-Image-out MetaFormer Variant
Chaplot, Nipun	Effectiveness of Timing-Aware Scan Tests in Targeting Marginal Failures and Silent Data Errors in a Data Center Processor
Chatterjee, Abhijit	TEACH: Outlier Oriented Testing of Analog/Mixed-Signal Circuits Using One-class Clustering in Hyperdimensional Spaces
Chattopadhyay, Rita	E-SCOUT: Efficient-Spatial Clustering-based OUtlier detection through Telemetry
Chaudhuri, Arjun	Safety-Guided Test Generation for Structural Faults Defect Analysis for FeFETs using a Compact Model
Chen, Danyang	Defects, Fault Modeling, and Test Development Framework for FeFETs
Chen, Degang	A Robust On-Chip Sensor for Online Monitoring of BTI-Induced Aging in Integrated Circuits
Chen, Ping-Wen	Test Chip Design for Small Delay Defect Diagnosis Based on C-testable Arrays and Mutually Orthogonal Latin Squares
Chen, Rebecca	AI-Enabled Board Level Vibration Testing: Unveiling the Physics of Degradation
Cheng, Wu-Tung	Adaptive Diagnosis Points for 100% Chain Diagnosis Coverage
Cherukur, Omar Sharif	Accelerated 3D IC DFT Development using commercial multi-die solution
Chickermane, Vivek	Embedded Trace: A Key Enabler for Silicon Debug and Continuous Monitoring
Chiueh, Herming	LESER-2: Detailed Consideration in Latch Design under Process Migration for Prevention of Single-Event Double-Node Upsets
Choi, Jaemoo	Method for Diagnosing Clock Jitter Using FPGA Probe Card Ground Noise Canceling Circuit
Chu, Ying-Hua	Wafer-View Defect-Pattern-Prominent GDBN Method Using Image-in-Image-out MetaFormer Variant
Colburn, Jonathon	High-Performance ATPG with Loadable Nonscan Cells
Coppetta, Matteo	A graph-based algorithm for RRAM address decoders testing
Corso, Jorge	Optimizing Mobile & Automotive GPUs with Streaming Fabric, SEQ/XLBIST, IEEE1687 and TSO.ai
Couet, Sebastien	Testing STT-MRAMs: Do We Need Magnets in our Automated Test Equipment?
Coyette, Anthony	Bridging the EDA to ATE gap for mixed-signal with IEEE P1687.2 and P1450.1-2024
Côté, Jean-François	High-Bandwidth IJTAG over SSN
D
D'Souza, Jayant	Layout-aware Chain Diagnosis for Backside Power Cell-aware Chain Diagnosis for Backside Power
Dandnaik, Sudip	Scalable BIST for Linearity Testing of Sigma-Delta Modulators
Das, Anup	Wafer2Spike: Spiking Neural Network for Wafer Map Pattern Classification
Datta, Rajesh	Towards Machine-Learning-based Oracle-Guided Analog Circuit Deobfuscation
Deric, Aleksa	Evaluating Vulnerability of Chiplet-Based Systems to Contactless Probing Techniques
Detofsky, Abram	Intel HDMT ATE Capabilities Poster
Ding, Xiaotian	Diagnosis of Defects on Global Signals
Dobbelaere, Wim	Bridging the EDA to ATE gap for mixed-signal with IEEE P1687.2 and P1450.1-2024
Dokken, Ric	Bridging the EDA to ATE gap for mixed-signal with IEEE P1687.2 and P1450.1-2024
Doppa, Janardhan Rao	SEC-CiM: Selective Error Compensation for ReRAM-based Compute-in-Memory
E
Edmondson, Rob	Intel HDMT ATE Capabilities Poster
Eggersglüß, Stephan	A Cell-aware Transistor State Stress Model and its Application for Quality Measurement
Engelke, Piet	Bridging the EDA to ATE gap for mixed-signal with IEEE P1687.2 and P1450.1-2024
F
Faehn, Eric	A Fast and Efficient Graph-Based Methodology for Cell-Aware Model Generation
Farahmandi, Farimah	SECT-HI: Enabling Secure Testing for Heterogeneous Integration to Prevent SiP Counterfeits
Fieback, Moritz	Defects, Fault Modeling, and Test Development Framework for FeFETs Testing STT-MRAMs: Do We Need Magnets in our Automated Test Equipment? Robust Design-for-Testability Scheme for Conventional and Unique Defects in RRAMs
Firouzi, Farshad	SEC-CiM: Selective Error Compensation for ReRAM-based Compute-in-Memory
Fledell, Evan	Intel HDMT ATE Capabilities Poster
Fu, Hong-Siang	Efficient Built-In Self-Test Scheme for Inter-Die Interconnects of Chiplet-Based Chips
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Gangwar, Anand	Optimizing Mobile & Automotive GPUs with Streaming Fabric, SEQ/XLBIST, IEEE1687 and TSO.ai
Gaudet, Jonathan	High-Bandwidth IJTAG over SSN Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard
Getz, Matthew	Evolution of PXI(e) Test for Digital Solutions
Gielen, Georges	Bridging the EDA to ATE gap for mixed-signal with IEEE P1687.2 and P1450.1-2024
Girard, Patrick	A Fast and Efficient Graph-Based Methodology for Cell-Aware Model Generation
Glowatz, Andreas	A Cell-aware Transistor State Stress Model and its Application for Quality Measurement
Godbole, Kaustubh	Accelerated 3D IC DFT Development using commercial multi-die solution
Godinez, Ricardo	Optimizing Mobile & Automotive GPUs with Streaming Fabric, SEQ/XLBIST, IEEE1687 and TSO.ai
Goel, Sandeep Kumar	Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard Handling Die-to-Die I/O Pads for 3DIC Interconnect Tests
Goteti, Prashant	TEACH: Outlier Oriented Testing of Analog/Mixed-Signal Circuits Using One-class Clustering in Hyperdimensional Spaces
Grossi, Alessandro	A graph-based algorithm for RRAM address decoders testing
Gupta, Sandeep	Predictive Testing for Aging in SRAMs and Mitigation
H
Hag, Eslam	Scalable BIST for Linearity Testing of Sigma-Delta Modulators
Haidar, Galib Ibne	SECT-HI: Enabling Secure Testing for Heterogeneous Integration to Prevent SiP Counterfeits
Hamdioui, Said	Defects, Fault Modeling, and Test Development Framework for FeFETs Testing STT-MRAMs: Do We Need Magnets in our Automated Test Equipment? Robust Design-for-Testability Scheme for Conventional and Unique Defects in RRAMs
Han, Dongkwan	Diagnosis of intermittent faults and corresponding algorithm development beyond 5nm technologies
Hansen, Ethan	Improved Silent Data Error Detection through Test Optimization using Reinforcement Learning
Harith, Ashrith	Driving deterministic In-System Test using Advanced Peripheral Bus (APB) Enhancing test quality for abutted designs with Logic BIST
Harrant, Manuel	Industrial application of IEEE P1687.2 for post-Si verification of a smart power device
Harrison, Lee	Deterministic In-Fleet Scan Test for a Cloud Computing Platform
Harutyunyan, Gurgen	Testing for aging in advanced SRAM : From front end of the line transistors to back end of the line interconnects
He, Chen	AI-Enabled Board Level Vibration Testing: Unveiling the Physics of Degradation
Hedrich, Lars	Identifying Undetectable Defects Using Equivalence Checking
Hellebrand, Sybille	Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing
Higo, Akio	TDR-Based S-Parameter Estimation of Signal Transmission Line on ATE Utilizing Built-In Driver and Comparator
Holcomb, Daniel	Evaluating Vulnerability of Chiplet-Based Systems to Contactless Probing Techniques
Holzner, Rainer	Virtual Test Development Using Pre-Silicon Verification Environment
Hsiao, Jennifer	Boost CPU Turbo Yield Utilizing Explainable Artificial Intelligence
Hsieh, Cheng-Yun	qFD: Coherent and Depolarizing Fault Diagnosis for Quantum Processors
Hua, Erbing	Robust Design-for-Testability Scheme for Conventional and Unique Defects in RRAMs
Huang, Shi-Yu	Small-Bridging-Fault-Aware Built-In-Self-Repair for Cycle-Based Interconnects in a Chiplet Design Using Adjusted Pulse-Vanishing Test
Huang, Yi-Chun	Efficient Built-In Self-Test Scheme for Inter-Die Interconnects of Chiplet-Based Chips
Huang, Yu	Diagnosis of Defects on Global Signals
I
Ignacio, Ryan	Virtual Test Development Using Pre-Silicon Verification Environment
Iizuka, Tetsuya	TDR-Based S-Parameter Estimation of Signal Transmission Line on ATE Utilizing Built-In Driver and Comparator
Inkley, Benson	Finding Faulty Components In a Live Fleet Environment – Short Paper
Inman, Brad	Intel HDMT ATE Capabilities Poster
Ishida, Masahiro	TDR-Based S-Parameter Estimation of Signal Transmission Line on ATE Utilizing Built-In Driver and Comparator
Iwata, Hiroyuki	Short Paper: Bus-based Packetized Scan Architecure Trade-offs for Hetrogeneous Multi-Die SoCs
J
Jacobs, Dan	Internally generated scan resets using OCC
Jafarzadeh, Hanieh	Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing
Jain, Dipali	Towards Machine-Learning-based Oracle-Guided Analog Circuit Deobfuscation
Janicki, Jakub	Adaptive Diagnosis Points for 100% Chain Diagnosis Coverage
Jeong, Hyuntae	Method for Diagnosing Clock Jitter Using FPGA
Jha, Rahil	A Novel Solution for Efficient Signal Pattern Debug of Complex Devices Interconnect Executable Tables, ‘Key’ Concepts Demonstrated Using DDR5 Speed Bin Example
Joardar, Biresh Kumar	SEC-CiM: Selective Error Compensation for ReRAM-based Compute-in-Memory
Jurga, Krzysztof	Diagnosis of intermittent faults and corresponding algorithm development beyond 5nm technologies Digital Scan and ATPG for Analog Circuits
K
Kagale, Sonia Ramachandra	Automation of PMU module using POP for TTR
Kakollu, Vijay	Effectiveness of Timing-Aware Scan Tests in Targeting Marginal Failures and Silent Data Errors in a Data Center Processor
Kalla, Priyank	Design-for-Test for Silicon Photonic Circuits
Kamanuri, Vinayak	Virtual Test Development Using Pre-Silicon Verification Environment
Kampmann, Matthias	High-Bandwidth IJTAG over SSN
Kandasamy, Nagarajan	Wafer2Spike: Spiking Neural Network for Wafer Map Pattern Classification
Kang, Dahyun	Diagnosis of intermittent faults and corresponding algorithm development beyond 5nm technologies
Kang, Hong Seong	Inline Full Test Flow Scoping Capability on V93K Smart Scale
Kang, Minho	Method for Diagnosing Clock Jitter Using FPGA Probe Card Ground Noise Canceling Circuit
Kang, Seohyun	Diagnosis of intermittent faults and corresponding algorithm development beyond 5nm technologies
Kanzawa, Yasunari	High-Performance ATPG with Loadable Nonscan Cells
Kapadiya, Krunal	A Novel Solution for Efficient Signal Pattern Debug of Complex Devices Interconnect
Karimi, Naghmeh	FAT-RABBIT: Fault-Aware Training towards Robustness Against Bit-flip Based Attacks in Deep Neural Networks
Karoonlatifi, Khaled	(Short Paper) Efficient Noise Injection Methodology for Sample and Hold Circuits in AMS Behavioral Models
Keezer, David	Experimental Evaluation of Multi-Stage Jitter-Reduction Circuits for 54 GHz ATE Clocks
Keim, Martin	High-Bandwidth IJTAG over SSN Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard Diagnosis of intermittent faults and corresponding algorithm development beyond 5nm technologies MBIST-based MRAM defect screening for safety-critical applications
Kelly, Brad	Improved Silent Data Error Detection through Test Optimization using Reinforcement Learning
Kennedy, Lorin	Synergetic Pre- and Post-Silicon SLM Analytics for Reliable and Safe Automotive
Kepinski, Michal	Power-Aware Test Scheduling for Memory BIST
Kern, Thomas	A graph-based algorithm for RRAM address decoders testing
Khan, Mohammed Moiz	Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard Handling Die-to-Die I/O Pads for 3DIC Interconnect Tests
Khandre, Dipika	Enhanced Security Mechanism for 1687 Network
Kichenamourty, Christina	Automation of PMU module using POP for TTR
Kim, Doo	Handling Die-to-Die I/O Pads for 3DIC Interconnect Tests
Kim, Doo	1687 Solution for Tiled Based Design with Feedthroughs
Kim, Siwoong	Minimizing Probe Touchdown Route After First EDS Steps for Test Cost Reduction
Kim, Woojin	Testing STT-MRAMs: Do We Need Magnets in our Automated Test Equipment?
Klemme, Florian	Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing
Koh, Khim	Boost CPU Turbo Yield Utilizing Explainable Artificial Intelligence
Komarraju, Suhasini	TEACH: Outlier Oriented Testing of Analog/Mixed-Signal Circuits Using One-class Clustering in Hyperdimensional Spaces
Koneru, Venkata Raja Ramchandar	Optimizing Mobile & Automotive GPUs with Streaming Fabric, SEQ/XLBIST, IEEE1687 and TSO.ai
Kruppa, David	Intel HDMT ATE Capabilities Poster
Kulkarni, Prashant	Driving deterministic In-System Test using Advanced Peripheral Bus (APB)
Kulkarni, Vinod	Virtual Test Development Using Pre-Silicon Verification Environment
Kulshreshtha, Kshitij	Automation to Speed up the process of Timing Closure of the IJTAG Network
Kulshreshtha, Kshitij	1687 Solution for Tiled Based Design with Feedthroughs Enhanced Security Mechanism for 1687 Network
Kumar, Suman	Wafer2Spike: Spiking Neural Network for Wafer Map Pattern Classification
Kun, Andras	Virtual Test Development Using Pre-Silicon Verification Environment
L
LaBanz, Trevor	Scalable BIST for Linearity Testing of Sigma-Delta Modulators
Lai, Chi	Small-Bridging-Fault-Aware Built-In-Self-Repair for Cycle-Based Interconnects in a Chiplet Design Using Adjusted Pulse-Vanishing Test
Lai, Citi	Boost CPU Turbo Yield Utilizing Explainable Artificial Intelligence
Lal, Suhana	Improved area overhead with advanced memory dump and memory test automation for AI chips
Lee, Frank	Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard
Lee, Frank	Handling Die-to-Die I/O Pads for 3DIC Interconnect Tests
Lee, Jaehoon	Diagnosis of intermittent faults and corresponding algorithm development beyond 5nm technologies
Lee, Kim Huat	Inline Full Test Flow Scoping Capability on V93K Smart Scale JTAG Protocol Aware Debug Tool for efficient debugging on V93K
Lee, Kuen-Jong	Test Chip Design for Small Delay Defect Diagnosis Based on C-testable Arrays and Mutually Orthogonal Latin Squares
Lee, Ross	Boost CPU Turbo Yield Utilizing Explainable Artificial Intelligence
Lee, Seongkwan	Method for Diagnosing Clock Jitter Using FPGA Probe Card Ground Noise Canceling Circuit
Lee, Th	Boost CPU Turbo Yield Utilizing Explainable Artificial Intelligence
Lee, Yung-Pin	Efficient Built-In Self-Test Scheme for Inter-Die Interconnects of Chiplet-Based Chips
Lemar, Naim	Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard
Lerner, David	Improved Silent Data Error Detection through Test Optimization using Reinforcement Learning
Leventhal, Ira	AI Chip Testing: Transforming Challenges into Opportunities with AI/ML/LLM Technology
Li, Chaobo	Defects, Fault Modeling, and Test Development Framework for FeFETs
Li, Chien-Mo	qFD: Coherent and Depolarizing Fault Diagnosis for Quantum Processors
Li, Jin-Fu	Efficient Built-In Self-Test Scheme for Inter-Die Interconnects of Chiplet-Based Chips
Li, Leon	Locked by Design: Enhancing White-box Logic Obfuscation with Effective Key Mutation
Li, Mingye	Predictive Testing for Aging in SRAMs and Mitigation
Li, Shu-Wen	Wafer-View Defect-Pattern-Prominent GDBN Method Using Image-in-Image-out MetaFormer Variant
Li, Xiuyan	Defects, Fault Modeling, and Test Development Framework for FeFETs
Li, Yen-Wei	qFD: Coherent and Depolarizing Fault Diagnosis for Quantum Processors
Lim, Ivy Ee Hsia	High-Bandwidth IJTAG over SSN
Lin, Chin Wei	Boost CPU Turbo Yield Utilizing Explainable Artificial Intelligence
Lin, Pei-Yun	Efficient Built-In Self-Test Scheme for Inter-Die Interconnects of Chiplet-Based Chips
Lin, Yunkun	Predictive Testing for Aging in SRAMs and Mitigation
Lingamoorthy, Anush Niranjan	Wafer2Spike: Spiking Neural Network for Wafer Map Pattern Classification
Lingappan, Loganathan	Improved Silent Data Error Detection through Test Optimization using Reinforcement Learning
Liu, Alan S.-M.	LESER-2: Detailed Consideration in Latch Design under Process Migration for Prevention of Single-Event Double-Node Upsets
Liu, Anlin	Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States
Liu, Peng	Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States
Liu, Yangfan	Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States
Lonkar, Apurva	Effectiveness of Timing-Aware Scan Tests in Targeting Marginal Failures and Silent Data Errors in a Data Center Processor
Lu, Tianyao	Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States
M
Ma, Keyue	Virtual Test Development Using Pre-Silicon Verification Environment
Macieira, Thiago	Improved Silent Data Error Detection through Test Optimization using Reinforcement Learning
Madabhushi, Krishna Pramod	Scalable BIST for Linearity Testing of Sigma-Delta Modulators
Mahadevan, Subramanian	Deterministic In-Fleet Scan Test for a Cloud Computing Platform
Makris, Yiorgos	Generation and Quality Evaluation of Synthetic Process Control Monitoring Data
Mangilal, Kunal Jain	A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS
Marev, Miroslav	Test Time Optimization: A Novel Staggered-capture Architecture Using A Token-passing Architecture
Mariacher, Bruno	Virtual Test Development Using Pre-Silicon Verification Environment
Marinissen, Erik Jan	Testing STT-MRAMs: Do We Need Magnets in our Automated Test Equipment?
Marinov, Ivan	Test Time Optimization: A Novel Staggered-capture Architecture Using A Token-passing Architecture
Martin, John	Improved Silent Data Error Detection through Test Optimization using Reinforcement Learning
Mathanker, Ravindra	Test Time Optimization: A Novel Staggered-capture Architecture Using A Token-passing Architecture
Mayahinia, Mahta	Cross-Layer Reliability Evaluation of In-memory Similarity Computation Testing for aging in advanced SRAM : From front end of the line transistors to back end of the line interconnects
Mayer, Jeff	Driving deterministic In-System Test using Advanced Peripheral Bus (APB) Enhancing test quality for abutted designs with Logic BIST
McWithey, Preston	Layout-aware Chain Diagnosis for Backside Power Cell-aware Chain Diagnosis for Backside Power Adaptive Diagnosis Points for 100% Chain Diagnosis Coverage
Mejri, Jaafar	Identifying Undetectable Defects Using Equivalence Checking
Mejri, Mohamed	TEACH: Outlier Oriented Testing of Analog/Mixed-Signal Circuits Using One-class Clustering in Hyperdimensional Spaces
Minier, Dany	Experimental Evaluation of Multi-Stage Jitter-Reduction Circuits for 54 GHz ATE Clocks
Mishaeli, Michael	Finding Faulty Components In a Live Fleet Environment – Short Paper
Mishra, Abhishek Kumar	Wafer2Spike: Spiking Neural Network for Wafer Map Pattern Classification
Mitard, Kyle	Evaluating Vulnerability of Chiplet-Based Systems to Contactless Probing Techniques
Mohtar, Nursyahirah	Inline Full Test Flow Scoping Capability on V93K Smart Scale
Mongelli, Gianmarco	A Fast and Efficient Graph-Based Methodology for Cell-Aware Model Generation
Morozov, Andrey	(Short Paper) Efficient Noise Injection Methodology for Sample and Hold Circuits in AMS Behavioral Models
Mukherjee, Nilanjan	Driving deterministic In-System Test using Advanced Peripheral Bus (APB) Enhancing test quality for abutted designs with Logic BIST Deterministic In-Fleet Scan Test for a Cloud Computing Platform Delay Monitoring Under Different PVT Corners for Test and Functional Operation
N
Nadeau-Dostie, Benoit	Memory BIST for Automotive Non-destructive Memory Testing
Nahar, Pragya	Improving WLAN Rx PER Test Efficiency for Increased ATE Yield Optimizing ATE Resources for WLAN Rx PER Testing: A Cost-Effective Approach
Naik, Vinod	Internally generated scan resets using OCC
Nakura, Toru	TDR-Based S-Parameter Estimation of Signal Transmission Line on ATE Utilizing Built-In Driver and Comparator
Nalage, Chandra	Flexible Scan test Architecture with Scalable Bus in 2.5D/3D Packaged Chips
Nandigam, Ashok	Optimizing Mobile & Automotive GPUs with Streaming Fabric, SEQ/XLBIST, IEEE1687 and TSO.ai
Narayanan, Nijil	Accelerated 3D IC DFT Development using commercial multi-die solution
Narayanun, Kaushik	A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS
Nassif, Sani	Testing for aging in advanced SRAM : From front end of the line transistors to back end of the line interconnects
Natarajan, Suriyaprakash	TEACH: Outlier Oriented Testing of Analog/Mixed-Signal Circuits Using One-class Clustering in Hyperdimensional Spaces Effectiveness of Timing-Aware Scan Tests in Targeting Marginal Failures and Silent Data Errors in a Data Center Processor
Neerkundar, Vidya	Accelerated 3D IC DFT Development using commercial multi-die solution Flexible Scan test Architecture with Scalable Bus in 2.5D/3D Packaged Chips Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard From Hybrid to Integrated: The Evolution of DFT Integration in SoC Design at Intel
Nelapatla, Bala Tarun	Optimizing Mobile & Automotive GPUs with Streaming Fabric, SEQ/XLBIST, IEEE1687 and TSO.ai
Nezhadi, Ali	Cross-Layer Reliability Evaluation of In-memory Similarity Computation
Ng, Jiang Wen	JTAG Protocol Aware Debug Tool for efficient debugging on V93K
Ng, Kevin Khim Foong	JTAG Protocol Aware Debug Tool for efficient debugging on V93K
Nguyen, Nguyen	A Fast, Statistical, Machine-learning Approach for Automotive Semiconductor Test Reduction
Nguyen, Vuong	Scalable Multi-Chiplet Test Solution Using IEEE 1838 Handling Die-to-Die I/O Pads for 3DIC Interconnect Tests
Ni, Kai	Defect Analysis for FeFETs using a Compact Model
Nigh, Matthew	Generation and Quality Evaluation of Synthetic Process Control Monitoring Data
Nirmaier, Thomas	Industrial application of IEEE P1687.2 for post-Si verification of a smart power device
Nithyanandam, Jeyendran	Automation of PMU module using POP for TTR
Njinda, Charles	Improved area overhead with advanced memory dump and memory test automation for AI chips
Nooralinejad Eslamloo, Parsa	FAT-RABBIT: Fault-Aware Training towards Robustness Against Bit-flip Based Attacks in Deep Neural Networks
Nti-Darko, Emmanuel	A Robust On-Chip Sensor for Online Monitoring of BTI-Induced Aging in Integrated Circuits
O
O'Donnell, Mat	Embedded Trace: A Key Enabler for Silicon Debug and Continuous Monitoring
Oak, Chaitali	Effectiveness of Timing-Aware Scan Tests in Targeting Marginal Failures and Silent Data Errors in a Data Center Processor
Ochsenknecht, Sascha	High-Bandwidth IJTAG over SSN
Ogbogu, Chukwufumnanya	SEC-CiM: Selective Error Compensation for ReRAM-based Compute-in-Memory
Olejarz, Michał	High-Bandwidth IJTAG over SSN
Ooi, Chen Hee	Efficiency and Reliability Enhancement in Pre-Silicon Validation Lessons from ASIC Networking product
Orailoglu, Alex	Locked by Design: Enhancing White-box Logic Obfuscation with Effective Key Mutation
Orczyk, Makary	Power-Aware Test Scheduling for Memory BIST
Orlando, Peter	Efficient Test port access to address test time
Ortega, Eduardo	E-SCOUT: Efficient-Spatial Clustering-based OUtlier detection through Telemetry
P
Paik, Woohyun	E-SCOUT: Efficient-Spatial Clustering-based OUtlier detection through Telemetry
Pajak, Brian	From Hybrid to Integrated: The Evolution of DFT Integration in SoC Design at Intel
Pal, Manabendra	Accelerated 3D IC DFT Development using commercial multi-die solution
Pampana, Rajkumar	Optimizing Mobile & Automotive GPUs with Streaming Fabric, SEQ/XLBIST, IEEE1687 and TSO.ai
Pande, Partha Pratim	SEC-CiM: Selective Error Compensation for ReRAM-based Compute-in-Memory
Pant, Pankaj	From Hybrid to Integrated: The Evolution of DFT Integration in SoC Design at Intel Functional State Extraction Using Scan DFT
Pantskalashvili, Lana	Effective detection of uncommon faults by SMarchCHKBvcd algorithm
Papu, Julian	Efficient Test port access to address test time
Parekhji, Rubin	Safety-Guided Test Generation for Structural Faults
Park, Chanyeol	Probe Card Ground Noise Canceling Circuit
Park, Cheolmin	Method for Diagnosing Clock Jitter Using FPGA Probe Card Ground Noise Canceling Circuit
Park, Sunyong	Probe Card Ground Noise Canceling Circuit
Patel, Gruheshkumar	Solving Verification Challenges for Modern DRAM based Systems requiring Refresh and Refresh Management Compliance
Pathy, Sundar	Intel HDMT ATE Capabilities Poster
Patidar, Ankita	Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard Handling Die-to-Die I/O Pads for 3DIC Interconnect Tests
Patil, Chetan Arvind	UID Way Of End-To-End Specification Compliance And Data Analysis
Peng, Ke	Driving deterministic In-System Test using Advanced Peripheral Bus (APB)
Perfecto Reyes, Gerardo J.	Effectiveness of Timing-Aware Scan Tests in Targeting Marginal Failures and Silent Data Errors in a Data Center Processor
Pfabigan, Otto Karl	Virtual Test Development Using Pre-Silicon Verification Environment
Phan, Chanh Quoc	Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard
Phielipp, Mariano	Improved Silent Data Error Detection through Test Optimization using Reinforcement Learning
Pirsiavash, Hamed	FAT-RABBIT: Fault-Aware Training towards Robustness Against Bit-flip Based Attacks in Deep Neural Networks
Pogiel, Artur	Memory BIST for Automotive Non-destructive Memory Testing Power-Aware Test Scheduling for Memory BIST Diagnosis of intermittent faults and corresponding algorithm development beyond 5nm technologies
Pomeranz, Irith	Delay Monitoring Under Different PVT Corners for Test and Functional Operation Functionally-Possible Gate-Exhaustive Bridging Faults
Pourmehrani, Hossein	FAT-RABBIT: Fault-Aware Training towards Robustness Against Bit-flip Based Attacks in Deep Neural Networks
Press, Ron	Short Paper: Bus-based Packetized Scan Architecure Trade-offs for Hetrogeneous Multi-Die SoCs
Primawidodo, Cahyo	Bridging the EDA to ATE gap for mixed-signal with IEEE P1687.2 and P1450.1-2024 Industrial application of IEEE P1687.2 for post-Si verification of a smart power device
Przybilla, Adam	Virtual Test Development Using Pre-Silicon Verification Environment
Przybysz, Olga	High-Bandwidth IJTAG over SSN
R
R, Aravind	Improving WLAN Rx PER Test Efficiency for Increased ATE Yield
Rabenu, Amihay	Automation to Speed up the process of Timing Closure of the IJTAG Network
Racine, Etienne	Effective detection of uncommon faults by SMarchCHKBvcd algorithm Diagnosis of intermittent faults and corresponding algorithm development beyond 5nm technologies
Raja, Vishwanath	Improved area overhead with advanced memory dump and memory test automation for AI chips
Rajagopal, Selva	Efficient Test port access to address test time
Rajski, Janusz	Deterministic In-Fleet Scan Test for a Cloud Computing Platform Delay Monitoring Under Different PVT Corners for Test and Functional Operation Test Data Encryption with a New Stream Cipher
Rao, Siddharth	Testing STT-MRAMs: Do We Need Magnets in our Automated Test Equipment?
Reimer, Jan Dennis	Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing
Robins, Dylan	A Fast and Efficient Graph-Based Methodology for Cell-Aware Model Generation
Rongen, Rene	AI-Enabled Board Level Vibration Testing: Unveiling the Physics of Degradation
Roucou, Romuald	AI-Enabled Board Level Vibration Testing: Unveiling the Physics of Degradation
Roy, Soham	Effectiveness of Timing-Aware Scan Tests in Targeting Marginal Failures and Silent Data Errors in a Data Center Processor Unsupervised Learning Provides Intelligence for Testing Hard to Detect Faults
S
Sahoo, Deepesh	Safety-Guided Test Generation for Structural Faults
Samardzic, Darko	Virtual Test Development Using Pre-Silicon Verification Environment
Sami, Md Sami Ul Islam	SECT-HI: Enabling Secure Testing for Heterogeneous Integration to Prevent SiP Counterfeits
Sarangi, Shantanu	A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS
Saw, Yee Chung	Efficiency and Reliability Enhancement in Pre-Silicon Validation Lessons from ASIC Networking product
Scaramuzza, Pierre	A graph-based algorithm for RRAM address decoders testing
Schaub, Keith	AI Chip Testing: Transforming Challenges into Opportunities with AI/ML/LLM Technology
Schey, Thorben	(Short Paper) Efficient Noise Injection Methodology for Sample and Hold Circuits in AMS Behavioral Models
Schlagbauer, Florian	Virtual Test Development Using Pre-Silicon Verification Environment
Schleicher, Mario	Virtual Test Development Using Pre-Silicon Verification Environment
Schramm, Lori	High-Bandwidth IJTAG over SSN Diagnosis of intermittent faults and corresponding algorithm development beyond 5nm technologies
Seetharaman, Prashant	Effective detection of uncommon faults by SMarchCHKBvcd algorithm Improved area overhead with advanced memory dump and memory test automation for AI chips
Shamsa, Manu	Improved Silent Data Error Detection through Test Optimization using Reinforcement Learning
Shamsi, Kaveh	Towards Machine-Learning-based Oracle-Guided Analog Circuit Deobfuscation
Shankaranarayanan, Bharath	Scalable Multi-Chiplet Test Solution Using IEEE 1838 Handling Die-to-Die I/O Pads for 3DIC Interconnect Tests
Sharma, Ankita	Enhancing test quality for abutted designs with Logic BIST
Sharma, Ankita	Improved area overhead with advanced memory dump and memory test automation for AI chips
Sharma, Manish	Adaptive Diagnosis Points for 100% Chain Diagnosis Coverage
Sharma, Mohit	Accelerated 3D IC DFT Development using commercial multi-die solution
Sharma, Shyam	Solving Memory Subsystem Verification Challenges for Multi-Instance Designs. A Novel Solution for Efficient Signal Pattern Debug of Complex Devices Interconnect Solving Verification Challenges for Modern DRAM based Systems requiring Refresh and Refresh Management Compliance
Shirahata, Kazuki	TDR-Based S-Parameter Estimation of Signal Transmission Line on ATE Utilizing Built-In Driver and Comparator
Shroff, Mehul	A Fast, Statistical, Machine-learning Approach for Automotive Semiconductor Test Reduction
Shtulman, Ari	Test Time Optimization: A Novel Staggered-capture Architecture Using A Token-passing Architecture
Singh, Jaskaran Jeet	Accelerated 3D IC DFT Development using commercial multi-die solution
Singh, Pramod	Optimizing Mobile & Automotive GPUs with Streaming Fabric, SEQ/XLBIST, IEEE1687 and TSO.ai
Sinha, Arani	Functional State Extraction Using Scan DFT
Soestbergen, Michiel	AI-Enabled Board Level Vibration Testing: Unveiling the Physics of Degradation
Son, Hyeonuk	Diagnosis of intermittent faults and corresponding algorithm development beyond 5nm technologies
Stelmach, Artur	Adaptive Diagnosis Points for 100% Chain Diagnosis Coverage
Stępniewska, Marta	High-Bandwidth IJTAG over SSN
Su, Fei	E-SCOUT: Efficient-Spatial Clustering-based OUtlier detection through Telemetry
Subashchandran, Dharini	Solving Verification Challenges for Modern DRAM based Systems requiring Refresh and Refresh Management Compliance
Sugiura, Ohki	Short Paper: Bus-based Packetized Scan Architecure Trade-offs for Hetrogeneous Multi-Die SoCs
Sullivan, Patrick	Evolution of PXI(e) Test for Digital Solutions
Sunter, Stephen	Digital Scan and ATPG for Analog Circuits
T
Tajik, Shahin	Evaluating Vulnerability of Chiplet-Based Systems to Contactless Probing Techniques
Talukdar, Jonti	E-SCOUT: Efficient-Spatial Clustering-based OUtlier detection through Telemetry
Tan, Xuanyi	Safety-Guided Test Generation for Structural Faults
Tang, Fengfeng	Scalable Multi-Chiplet Test Solution Using IEEE 1838
Taouil, Mottaqiallah	Defects, Fault Modeling, and Test Development Framework for FeFETs Testing STT-MRAMs: Do We Need Magnets in our Automated Test Equipment? Robust Design-for-Testability Scheme for Conventional and Unique Defects in RRAMs
Tehranipoor, Mark	SECT-HI: Enabling Secure Testing for Heterogeneous Integration to Prevent SiP Counterfeits
Thapar, Dhruv	Safety-Guided Test Generation for Structural Faults
Thapar, Dhruv	Defect Analysis for FeFETs using a Compact Model
Thiruvengadam, Bharani	Intel HDMT ATE Capabilities Poster
Thota, Kiran	A Fast, Statistical, Machine-learning Approach for Automotive Semiconductor Test Reduction
Thukral, Varun	AI-Enabled Board Level Vibration Testing: Unveiling the Physics of Degradation
Ting, Yi-Ju	Boost CPU Turbo Yield Utilizing Explainable Artificial Intelligence
Tofte, Jan	Accelerated 3D IC DFT Development using commercial multi-die solution
Tokuz, Ahmet	Test Time Optimization: A Novel Staggered-capture Architecture Using A Token-passing Architecture Scan SerDes for Multi-die Packages
Trawka, Maciej	Test Data Encryption with a New Stream Cipher
Trock, Dan	Deterministic In-Fleet Scan Test for a Cloud Computing Platform
Tsao, Po-Chao	Boost CPU Turbo Yield Utilizing Explainable Artificial Intelligence
Tshagharyan, Grigor	Testing for aging in advanced SRAM : From front end of the line transistors to back end of the line interconnects
Tucknott, Michael	Improved Silent Data Error Detection through Test Optimization using Reinforcement Learning
Tyagi, Vistrita	Scalable Multi-Chiplet Test Solution Using IEEE 1838 1687 Solution for Tiled Based Design with Feedthroughs Enhanced Security Mechanism for 1687 Network
Tyszer, Jerzy	Deterministic In-Fleet Scan Test for a Cloud Computing Platform Test Data Encryption with a New Stream Cipher
U
Ullmann, Rudolf	A graph-based algorithm for RRAM address decoders testing
Upadhyay, Saurabh	Scan SerDes for Multi-die Packages
Urban, Szczepan	Layout-aware Chain Diagnosis for Backside Power Cell-aware Chain Diagnosis for Backside Power Adaptive Diagnosis Points for 100% Chain Diagnosis Coverage
V
Valiente, Patrick	Virtual Test Development Using Pre-Silicon Verification Environment
van Driel, Willem	AI-Enabled Board Level Vibration Testing: Unveiling the Physics of Degradation
van Ulsen, Paul	Evolution of PXI(e) Test for Digital Solutions
Vargas, Enzo	Virtual Test Development Using Pre-Silicon Verification Environment
Veltink, Gerwin	Evolution of PXI(e) Test for Digital Solutions
Virazel, Arnaud	A Fast and Efficient Graph-Based Methodology for Cell-Aware Model Generation
W
Wagner, Ilya	Functional State Extraction Using Scan DFT
Waicukauski, John	High-Performance ATPG with Loadable Nonscan Cells
Wang, Baohua	Diagnosis of Defects on Global Signals
Wang, Changhao	Defects, Fault Modeling, and Test Development Framework for FeFETs
Wang, Li-C	WM-Graph: Graph-Based Approach for Wafermap Analytics
Wang, Lin	Defects, Fault Modeling, and Test Development Framework for FeFETs
Wang, Lowry P.-T.	LESER-2: Detailed Consideration in Latch Design under Process Migration for Prevention of Single-Event Double-Node Upsets
Wang, Seongmoon	Optimizing Mobile & Automotive GPUs with Streaming Fabric, SEQ/XLBIST, IEEE1687 and TSO.ai
Wehn, Norbert	Testing for aging in advanced SRAM : From front end of the line transistors to back end of the line interconnects
Weis, Christian	Testing for aging in advanced SRAM : From front end of the line transistors to back end of the line interconnects
Wen, Charles H.-P.	LESER-2: Detailed Consideration in Latch Design under Process Migration for Prevention of Single-Event Double-Node Upsets
Weyrich, Michael	(Short Paper) Efficient Noise Injection Methodology for Sample and Hold Circuits in AMS Behavioral Models
Wlodarczak, Bartosz	Test Data Encryption with a New Stream Cipher
Wohl, Peter	High-Performance ATPG with Loadable Nonscan Cells
Won, Jun Yeon	Method for Diagnosing Clock Jitter Using FPGA Probe Card Ground Noise Canceling Circuit
Wu, Jiezhong	Delay Monitoring Under Different PVT Corners for Test and Functional Operation
Wu, Kai-Chiang	Wafer-View Defect-Pattern-Prominent GDBN Method Using Image-in-Image-out MetaFormer Variant
Wu, Meng-Chen	qFD: Coherent and Depolarizing Fault Diagnosis for Quantum Processors
Wunderlich, Hans-Joachim	Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing
X
Xi, Yuhao	Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States
Xun, Hanzhi	Defects, Fault Modeling, and Test Development Framework for FeFETs Testing STT-MRAMs: Do We Need Magnets in our Automated Test Equipment? Robust Design-for-Testability Scheme for Conventional and Unique Defects in RRAMs
Y
Yaldagard, Mohammad Amin	Robust Design-for-Testability Scheme for Conventional and Unique Defects in RRAMs
Yang, Min Jian	WM-Graph: Graph-Based Approach for Wafermap Analytics
Yang, Woonphil	Probe Card Ground Noise Canceling Circuit
Yang, Xin	Adaptive Diagnosis Points for 100% Chain Diagnosis Coverage
Yen, Chia-Heng	Wafer-View Defect-Pattern-Prominent GDBN Method Using Image-in-Image-out MetaFormer Variant
Yilmaz, Mahmut	A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS
Yin, Chujun	Defects, Fault Modeling, and Test Development Framework for FeFETs
Yordanov, Kristian	Test Time Optimization: A Novel Staggered-capture Architecture Using A Token-passing Architecture
Yuan, Sicong	Defects, Fault Modeling, and Test Development Framework for FeFETs Testing STT-MRAMs: Do We Need Magnets in our Automated Test Equipment? Robust Design-for-Testability Scheme for Conventional and Unique Defects in RRAMs
Yun, Jongsin	Diagnosis of intermittent faults and corresponding algorithm development beyond 5nm technologies MBIST-based MRAM defect screening for safety-critical applications
Z
Zaal, Jeroen	AI-Enabled Board Level Vibration Testing: Unveiling the Physics of Degradation
Zak, Marcel	Embedded Trace: A Key Enabler for Silicon Debug and Continuous Monitoring
Zamiri Azar, Kimia	SECT-HI: Enabling Secure Testing for Heterogeneous Integration to Prevent SiP Counterfeits
Zeng, Yueling	WM-Graph: Graph-Based Approach for Wafermap Analytics
Zhang, G.Q.	AI-Enabled Board Level Vibration Testing: Unveiling the Physics of Degradation
Zhang, Letian	AI-Enabled Board Level Vibration Testing: Unveiling the Physics of Degradation
Zhang, Weiming	Diagnosis of Defects on Global Signals
Zhang, Yin	Diagnosis of Defects on Global Signals
Zhang, Zhe	Testing for aging in advanced SRAM : From front end of the line transistors to back end of the line interconnects
Zhao, Guangwei	Towards Machine-Learning-based Oracle-Guided Analog Circuit Deobfuscation
Zhao, Xinyang	Diagnosis of Defects on Global Signals
Zhou, Jingbo	SECT-HI: Enabling Secure Testing for Heterogeneous Integration to Prevent SiP Counterfeits
Zikulnig, Otmar	Virtual Test Development Using Pre-Silicon Verification Environment
Zivkovic, Vladimir	Identifying Undetectable Defects Using Equivalence Checking
Zorian, Yervant	Testing for aging in advanced SRAM : From front end of the line transistors to back end of the line interconnects
Zou, Wei	Memory BIST for Automotive Non-destructive Memory Testing

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