Vinod Naik, Principal DFT Engineer, Infineon Technologies

As a seasoned Principal DFT Engineer at Infineon Technologies, I bring 12 years of Design for Testability (DFT) expertise. Holding a Master's degree in VLSI Design and Embedded Systems and an executive development program certificate in MBA from the University of Washington, I'm passionate about driving innovation in chip design and test methodology.

With hands-on experience in a range of areas, including Test Time improvement methodology, Defect analysis in Silicon debug, and Defining DFT architecture for SOC designs, I'm well-versed in developing DFT methodology flows for core DFT niches such as BSCAN, MBIST, Scan Insertion, ATPG, SDF Sims, and pattern hand-off to Tester for post-silicon debug.