ABSTRACT. This paper presents a novel approach named WM-Graph that supports flexible analytics of wafermaps. Given a set of wafermaps, the core idea is to construct a wafermap graph where two wafermaps are connected when they are semi-equivalent. Then, all analytics can be performed on the wafermap graph based on graph algorithms. The WM-Graph approach enables implementation of a wafermap analytics tool that can answer a variety of practical questions, hard to answer with a traditional multi-class classification approach. We will explain the technical innovation to realize the WM-Graph approach and how various simple graph algorithms can be used to accomplish a variety of analytics capabilities. Experiments to show the benefits of the WM-Graph approach are conducted based on the WM-811K public dataset and a private dataset from a recent production line.

ABSTRACT. We present XAI framework to enhance CPU turbo yield by optimizing WAT parameters. Our method uses XGBoost in the model and uses SHAP values to analyze the importance of WAT, enabling optimization of manufacturing processes. Compared to traditional Pearson correlation, our method overcomes traditional limitations, identifying WAT Rs_Metal_6 as a primary factor. Experiment confirms a 15% turbo yield increase, validating it an effective and comprehensive method for yield improvement.

ABSTRACT. This work presents a novel, fast, scalable, and statistically rigorous test-time reduction flow for automotive semiconductor products, combining an unsupervised machine-learning approach (association analysis) and a greedy algorithm, for identifying redundant tests for removal.

ABSTRACT. A pre-silicon design-for-diagnosis flow is essential to achieving high diagnosis quality, which is necessary to improve yield and meet time-to-volume business requirements. This paper describes a novel mechanism that inserts one XOR gate at scan cells, enabling the scan cells to operate in an additional mode to make them diagnosable. A combination of a diagnosis-enable signal bit and the scan-enable signal activates this extra mode. We use a local scan cell without an additional input pin to provide the diagnosis-enable signal.

ABSTRACT. In this paper, we propose an efficient built-in self-test scheme for the testing of inter-die interconnects of chiplet-based ICs. The drivers/receivers under test are logically arranged as a 2D array. A test algorithm with alternating row-stripe and column-stripe patterns is proposed. Then, the 2D test patterns are compressed into 1D test patterns such that the test application time can be reduced.

ABSTRACT. Motivated by the occurrence of silent data errors, this paper describes a framework for monitoring timing related issues under different PVT corners for test and functional operation. The framework consists of a procedure for the identification of the longest paths under different PVT corners, a design of a programmable slack monitor that can raise an alarm under different scenarios where paths have failed or are close to failure, and a selection procedure for paths that should be monitored.

ABSTRACT. This paper introduces a new high-bandwidth IJTAG DFT technology that leverages the optimized, packet-based streaming scan network (SSN) parallel bus to drive the serial IEEE 1687 (IJTAG) network. It describes the DFT implementation methodology, the impact to the backend timing and SDC, and how verification was done by Intel as they deployed it on multiple dielets in their next generation client CPU. Moreover, data on area overhead and the overall test cost savings achieved is presented.

ABSTRACT. ReRAM-based Compute-in-Memory architectures are an attractive design choice for accelerating Convolutional Neural Network inference. However, these architectures are prone to stuck-at-faults in ReRAM cells, significantly degrading inferencing accuracy. This work proposes a reduced-overhead selective error compensation technique. To enable selective error compensation, we present a theoretical framework that determines the minimum number of columns in a crossbar requiring error compensation.

ABSTRACT. Faults affect quantum processors(QPs). We propose a technique for diagnosing coherent and depolarizing faults for QPs. Our technique contains rough, fine, and depolarizing diagnosis. The diagnosis accuracy is over 99.95%, better than quantum process tomography.

ABSTRACT. FPGAs have become a well-established solution for systems aiming for high performance and flexibility. Furthermore, FPGA-based SoCs have facilitated the integration of software programmability and custom hardware acceleration. The sensitivity to disturbance, the scarcity of CAD tools dedicated to evaluating robustness, and the drastic increase in on-chip components pose challenges to analyzing and assessing the reliability of reconfigurable systems in safety-critical domains. The current work proposes methodologies for accurate and efficient robustness analysis of Reconfigurable SoCs. It focuses on the heterogeneous components and modules Reconfigurable SoCs embed, such as soft and hard processors, host-device interfacing systems, and custom hardware accelerators. The research explores and provides the methodology and practical tools for developing and evaluating reliable applications on Reconfigurable SoCs, enabling detailed analysis of systems and their components.

ABSTRACT. Machine learning (ML) offers solutions across diverse domains, including resource-constrained devices. Despite advances in performance optimization and reduced-precision implementations, ML susceptibility to soft errors from radiation is unclear. This work uses virtual platforms to conduct a comprehensive soft error reliability assessment, at early design phases, of ML algorithms for Arm processors. The test strategy integrates confidence metrics, extensive fault injection (FI) campaigns, application profiling, and fault classifications. The main goals comprise (i) analyzing the consistency of SOFIA, a JIT-based framework, against event-driven simulators and (ii) investigating correlations between FI results, NN-optimized kernels, and reduced-precision CNNs for IoT devices, promoting software-based mitigation techniques. Results covering over 14.8 million FIs highlight SOFIA’s consistency, offering insights into balancing performance and reliability in multithreaded IoT edge platforms.

ABSTRACT. Micro Electro-Mechanical Systems (MEMS) accelerometers are utilized in safety-critical applications. Despite providing highly accurate results, they require calibration during production and periodic recalibration due to potential degradation over time. The National Institutes of Standards and Technology (NIST) stipulates that the accuracy of motion sensors used in safety-critical applications must be maintained within a 1% error margin. In our research, we propose an electrical stimulus-based calibration method for sensors during production and in-field use. We propose an incremental sensor-based model that can correlate sensor sensitivity degradation and process variation to its electrical response for in-field monitoring. Simulations demonstrate that the model can forecast sensitivity changes within a 1% error margin. Additionally, we have developed a cost-effective rotating test platform for calibrating and measuring accelerometer sensitivity.

ABSTRACT. Adherence to the ISO 26262 standard necessitates periodic testing of the embedded memories within automobiles during operation. Such testing requires the preservation of memory contents post-test, along with a precise integration of test logic with system logic. This paper proposes a Memory Built-In Self-Test (MBIST) architecture designed to effectively address these testing challenges.

ABSTRACT. SSN oriented design provides a contained ATPG environment. Allowing us to implement a bottom-up automated validation flow from extracting block-level ICL to validate ATPG at-speed readiness at a preliminary design stage (RTL) ensuring our design architecture (TAP & SSN Networks), clock scheme are validated. Develop our power-up sequence in RTL before netlist availability, all of that help us reflect changes to improve our designs in early stages of the RTL.

ABSTRACT. Evaluating the clock quality of a device's phase-locked loop (PLL) using automatic test equipment (ATE) at an affordable cost is challenging due to the large number of channels and long test times required. This study proposes a novel low-cost method for testing the clock jitter of devices using only the built-in resources of the ATE. The method leverages field-programmable gate array (FPGA) resources, such as PLLs and delay elements, integrated into the ATE. By performing jitter evaluation on multiple devices simultaneously using the existing test equipment, without incurring additional costs, it is possible to detect clock quality defects in semiconductors in less than 1μs.

ABSTRACT. Introducing an efficient noise injection method for sample-and-hold circuit behavioral models in AMS circuits. By targeting key time points, computational requirements are significantly minimized. A Verilog-AMS implementation and simulation results are provided.

ABSTRACT. While full scan has widely recognized benefits, high-performance designs often trade off partial scan for area and timing benefits. Evidently, Automatic Test Pattern Generation can be significantly more difficult on partial scan designs. We present enhancements to an ATPG system that enable testing sequential faults with full scan performance using nonscan cells that are loadable during scan shift, avoiding the need for more complex sequential test generation.

ABSTRACT. Scan pattern count grows exponentially for designs with many asynchronous clock domains with one-hot clocking per pattern.Staggering multiple capture pulses per pattern is a way to address this. However if timing of capture pulses is incorrect it can result in silicon failures.The technique proposed in this paper employs a hardware solution to reliably stagger several clock domains using a token passing approach.

ABSTRACT. Engineers need to develop JTAG patterns for testing configs. Time delay for bringing a new JTAG pattern into the test program can be costly as the conversion from STIL to Tester Binary is long. We developed JTAG PA debug tool to address this time delay for bringing a new JTAG pattern into loaded test program. The tool has the ability translate the STIL directly into the tester memory without any delay for pattern conversion. Besides, debugged patterns can be used directly for a production run.

ABSTRACT. Engineer needs to collect the full test flow current/voltage profile during power-on to ensure no abnormal behavior such as sudden current spike or voltage drop that could damage the TIU. No combined profiling feature available on Advantest’s V93K DPS128 Smart Scale tester due to memory limitation. To overcome this, we have developed an Inline Full Test Flow Scoping Capability by enhancing the original V93K Smart Scale tester without needs to spend extra money for any tester hardware upgrading.

ABSTRACT. PMU is the core of any chip and supplies power to different modules of the chip. This module tested in SoC combo chips using conventional method consumes 15%-18% of the overall test time and it directly relates to increased test cost. The POP method has the feasibility to reduce test time by approximately 50%. However, the effort to bring-up is manual and error prone. This paper aims at addressing this issue by automating the POP implementation, so reducing bring-up time and TAT of the product.

ABSTRACT. As AI, communications, EV and self-driving automobiles drive the need for greater data acquisition and processing, smaller and smaller geometries have been used to preserve cost, power and footprint. This places greater stress on testing these high pin count devices thoroughly and cost effectively. Meeting this challenge requires testers and instruments with greater pin counts, made possible by lower power, higher density pin electronics. Elevate has collaborated with Salland Engineering (Advantest), a top instrument manufacturer, to offer Pin Cards with 2x-4x the density, speed and memory of existing instruments with the same power and footprint. This paper will detail the design and performance of a modular 64-channel PXI(e) card and the device that enabled it. The modular design of these cards allow for the flexibility to expand the design as the market needs require.

ABSTRACT. The Semiconductor New Product Introduction (NPI) process requires validating numerous datasheet specifications, making traceability to specific test programs complex and error-prone. The TNUM process of tracking and managing the specification analysis to achieve the needed compliance often becomes time-consuming as the number of specifications to validate increases with the increase in features a silicon chip provides. To avoid errors and test escapes and ensure 100% compliance and zero test escapes, The Unique Identifier (UID) method is introduced in this poster. It is a novel approach for design, silicon bring-up, and validation engineers. It enables efficient identification and cataloging of specifications within the Compliance Matrix (CM), Datasheet (DS), and Automated Test Equipment (ATE) programs. Overall, the UID method improves efficiency, simplifies specification management, and ensures 100% traceability and synchronization.

ABSTRACT. This paper is about defining DfT architecture for generating internal scan reset pulse using OCC. Traditional approaches for providing scan reset leads to certain limitations in the face of limited IOs, limited ATE resources and limited coverage. So, to overcome these limitations, a DfT architecture is defined which generates scan reset internally using OCC.

ABSTRACT. The constant need for efficiency in verification of smart power devices emphasizes the necessity for standardization also in lab environments. Currently, this field is mainly dominated by small-scale, improvised environments with limited reusability of test cases and patterns from other domains such as pre-Si verification or test engineering. In this paper, we illustrate the use of the IJTAG’s chip-level PDL to simplify the test implementation of smart power devices in lab environment.

ABSTRACT. The transition to STIL brought forth a unique set of challenges, particularly when it came to validation using Tessent Verilog replay. Traditionally, Tessent Verilog and pattern replay had been the preferred methods for test pattern validation. However, we encountered unexpected challenges, Tessent Verilog replay often yielded invalid results and pattern replay required extensive development effort. This prompted us to embark on a journey to redefine our validation strategy to the entire process. By introducing STIL replay to replace both Tessent Verilog replay and pattern replay, we aimed to streamline our validation process, reduce redundancy and enhance efficiency. STIL replay successfully captured and validated approximately X% of the pattern replay failures. The remaining Y% of cases are covered by Intel in-house offline STIL and Pattern checkers. The lessons learned from ASIC networking product will undoubtedly pave the way for more efficient, reliable and innovative validation.

ABSTRACT. With the increasing complexity of mixed-signal IC’s, the demand for automation in general and test program generation in particular is growing. This automation can be achieved by using mature standards. This poster illustrates a solution for bridging the gap between EDA tools and ATE for mixed signal test applications by using the new Functions language block in the IEEE P1450.1-2024 STIL extension.

ABSTRACT. Automotive electronic systems are subjected to a large range of operating conditions and workloads. Increasing reliance on advanced process nodes and complex technologies adds extra challenges related to semiconductor variability and resulting reliability. This leads to an extraordinary dispersion and complexity of in-field measurements making discrimination of anomalies, aging, and degradation events difficult and prone to false-positives or missed critical conditions causing safety incidents. This paper presents a synergetic methodology to combine pre-silicon data (workload and fine-grained mission profiles, reliability models), manufacturing testing data (variability and aging models) with in-field test and observation for comparative analytics that can lead to generative outlier and anomalies prediction. The evaluated metrics provide actionable insights and support prognosis and diagnostics of critical circuit conditions and events, supporting critical reliability and safety goals.

ABSTRACT. This poster demonstrates how Manufacturing and In-system Test requirements of Mobile and Automotive GPUs are met with Streaming Fabric, SEQ/XLBIST unified codec and 1687. It also showcases Automatic Test Pattern Generation (ATPG) cycle reductions using TSO.ai and SEQ diagnosability thus optimizing implementation turnaround times, test costs and test quality.

ABSTRACT. HDMT (High Density Modular Tester) is an ATE widely deployed at Intel today. It has enabled manufacturing test for generations of Intel products at low costs. This paper introduces key capabilities that create unique value proposition for customers.

ABSTRACT. DRAM data integrity is a core requirement for any of the modern SoCs NoC and PCBs where DRAM memories are used anywhere in the system. It is also one of the most difficult problems to verify in today’s complex memory subsystems. Beyond the basic Refresh, Row Hammer and PRHT (Per Row Hammer Tracking) is increasing becoming an important consideration for the DRAM based systems. In the latest generation of DRAMs like DDR5 and Lpddr5, Refresh Management features are added to help designers tackle the Row Hammer challenges. This presentation talks about the innovative tools and solutions we have come up to help IP and SoC verification engineers, ensuring they can not only achieve their verification goals for the Refresh requirement that DRAMs have but also test the different aspects of Refresh Management and quantify their verification completeness by getting measurement of what all has been tested with intuitive Refresh/RFM related functional coverage

ABSTRACT. There is a increasing trend of representing information in tabular form since it is more efficient than writing sentences. For Very Large-Scale Integration (VLSI) domain etc. lots of useful information is encapsulated in tabular form in data sheets, specification etc. Tabular data being roughly packed, it becomes very challenging to extract, process and convert it to user consumable form. “Double Data Rate Generation 5” (DDR5) specification, there are more than 330+ tables which contributes approximately ~20%-~25% of information of entire specification[1]. There have been >50 iterations of specification to reach at this stage. Manual extraction and processing of this data can be a tough task. In this poster we present a solution of speed to mode/timing API which provides user-friendly way to query and iterate over extracted tabular data in user-friendly format. Significant impact of this solution can be seen when size of database containing tabular information increases to folds.

ABSTRACT. Logic BIST (Built-In Self-Test) is customary to test designs in-field due to reduced memory and area overhead. Abutted designs pose a challenge to LBIST, as there is no logic between any two tiles. This implies that communication between non-neighboring tiles can happen only through the tile between them. Traditional hierarchical DFT is not suitable in this case. This poster discusses a solution based on enhanced secondary and client interfaces to the LBIST controller to honor the connection requirements for abutted designs. It performs LBIST from any tile, with minimum area overhead and congestion.

ABSTRACT. The increasing demand of AI/ML/Cloud is driving the shift towards 2.5D and 3D system-in-package (SiP) IC designs. The number of cores in a chiplet and number of chiplets in a package continues to grow. IEEE1687 (IJTAG) and IEEE1838 cater to the need of new scan test requirements for accessing test instruments in 2D/2.5D/3D packages. The use of scalable bus-width and packetized scan-data simplifies IP integration and maximizes test throughput.

ABSTRACT. This poster introduces a methodology for sourcing signals below 6 GHz on 16 sites using the Teradyne UltraFlex ATE, comprising two Ultrawave24 and one MX8 instruments. The idea was implemented on a Wi-Fi Combo product which support Single-chip, dual-band, and tri-band 802.11ax specification. By leveraging a minor modification to the load board design, we were able to increase parallelism from x8 to x16, without requiring any changes to the tester configuration. This innovative solution resulted in a significant 60% reduction in test costs, making it a highly cost-effective approach for ATE testing.

ABSTRACT. With advancement in DRAM technologies, the device operating speeds continues to increase with every new generation. Higher device operating speeds have led to substantial increase in the pre-defined signal patterns that are needed at device input or output ports to avoid transmission and link errors. These patterns are needed for both the device training and normal operations. Two of the most recognizable signal pattern are DRAM pre-amble and post-amble. These pre-data patterns on the data strobes are required to make sure the Host and the DRAM can sample data packets correctly. Typically, device specifications have strict compliance requirements for signal patterns for a given operating speed like length of pre-amble and post-amble. This paper presents a compressive solution offered by Cadence to check signal pattern compliance requirements involving a set of pattern function, smart log, and associated callback for coverage with an example from DDR5 SDRAM specification.

ABSTRACT. The advent of multi-die chiplet devices on System-in-Package (SiP) has opened a new era for design-for-test (DFT). This poster discusses techniques and adherence to standards for testing chiplets in their 2.5D/3D packaged environment. Fast turnaround time to develop, integrate, and test the SiP for correctness, reliability, and performance is crucial. We discuss how a commercial multi-die solution helped accelerate DFT development for 3D stacked devices.

ABSTRACT. Wireless Local Area Network (WLAN) technology enables fast and reliable wireless connectivity. In WLAN receiver (Rx) tests, Packet Error Rate (PER) measures the reliability and stability of wireless communication systems This poster presents a solution to a pervasive WLAN Rx PER test stability issue affecting Wi-Fi 6/6E IEEE 802.11ax & Bluetooth combo products, characterized by excessive packet errors, and achieve a remarkable 20% yield saving and reduced final test time, significantly enhancing the efficiency of WLAN ATE testing.

ABSTRACT. This poster talks about the importance of the higher memory sub system level verification needs for protocol compliance of recent generation of memory sub systems using DDR like DDR5, Lpddr5 and how Cadence verification IP memory model team has come up/implemented a generic solution to describe such interconnect hierarchy in a modular and simple way. This approach describes a feature, associated grammar to capture memory sub system and implementation of handshake mechanism with triggers (like commands) to enhance individual instance DRAM model to be able to get visibility into other DRAM devices present in the design sharing resources like data bus, ZQ registers etc. Paper also given example of how this innovative solution has been used a number of customers to enhance their sub system level verification to the next level while verifying protocol compliance for JEDEC define specification for multi-rank memory sub systems for DDR5 and Lpddr5 based designs.

ABSTRACT. This paper evaluates several (8) multi-stage jitter reduction circuits with two stages of frequency-doubling that produce an ultra-low jitter (<200fs), 54GHz clock, synchronized to a 13.5GHz ATE reference signal. Jitter-reduction is achieved using up to 7 cascaded stages of real-time signal averaging, reducing random jitter (RJ) by as much as 4-times to a minimum of 171fs (slightly above the jitter floor).

ABSTRACT. 1687 Network is an IEEE Standard which provides an automated access to the mounting number of embedded instruments in today’s integrated circuits. CSUS Signals: “CaptureEn”, “ShiftEn” ,”UpdateEn” and “Select” signals are the main signals of this 1687 Network but because of the high fanout of these signals the satiating the timing closure requirement require complex analysis and generation of proper timing constraints. The FSM of the TAP with which the whole system works is very critical and if the state transitions are not ensuing appropriately then the 1687 network is not going to work properly.

Presenting a GUI Interface with a TCL script which will exploit the generation of Patterns by modifying the SPF file on the basis of “Insertion of WFT” and “Insertion of dummy cycles”. This approach helps the user to resolve the timing simulations without compromising on the huge Test time. Also, it is not going to create any problem during Reverse log diagnosis flow.

ABSTRACT. Manufacturing defects can occur throughout the product lifecycle. During the early yield ramp phase, identifying these defects and eliminating them quickly are critical for product profitability. Scan chain diagnosis has long been used to identify these defects. When defects occur in the scan chains of the design, it prevents testing of the logic of that design. However, defects on the scan chain also provide extremely valuable data to improve defectivity on a process node. The advent of new technologies, like backside power, in advanced process nodes have made fault isolation extremely challenging, further impeding the path to successful physical failure analysis. A new software-based technology provides accurate localization to enable efficient failure analysis defects internal to a cell.

ABSTRACT. Scan chain diagnosis has long been used to identify manufacturing defects and yield issues in early ramp. Identifying and eliminating these yield issues quickly and efficiently are required to ensure business success of a product. Root causing defect mechanisms that produce yield loss require a combination of fault isolation and failure analysis. The advent of new technologies, like backside power, in advanced process nodes have made fault isolation extremely challenging. A new software-based technology provides accurate localization to enable efficient failure analysis.

ABSTRACT. The recent surge in applications incorporating AI and Machine Learning (ML) technologies has led to the development of increasingly complex multi-chip AI semiconductor devices. Built using heterogeneous integration (HI), these advanced devices combine an array of chiplets into a single packaged unit. While this achievement is laudable, it brings about substantial challenges for semiconductor test processes. This poster will delve into how AI-driven solutions and the innovative use of Large Language Models (LLMs) such as GPT-4 are transforming the capabilities of test engineers and driving significant improvements in semiconductor testing.

ABSTRACT. Shrinking semiconductor technology nodes and increasing SoC complexity have made efficient and effective test methods paramount. Traditional pseudo-random pattern based logic BIST (LBIST) cannot meet high test quality requirements in such cases. This poster explores using deterministic In-System Test (IST) to meet aggressive test quality and test time requirements for safety critical applications (ASIL D). Advanced Peripheral Bus (APB) manager controlled by CPU, delivers deterministic IST patterns to the Design Under Test (DUT). An experimental implementation is presented.

ABSTRACT. Chips are becoming multifaceted day by day and they hold mammoth amount of affluence in the form of Embedded Instruments,hi-end Sensors,hardware monitors,BIST Engines, OCC Controllers etc.

To protect this unabridged ecosystem, Encryption and Obfuscation practices need be espoused.Since we are obligated to use the Test and debug circuitry for testing the DFT logic, it regrettably opens the door for an unauthorized admittance to Internal registers of Instruments which can lead to reverse engineering. It results in counterfeiting and data theft attacks which is a very protuberant security challenges which would create a huge risk for the device itself.

We are proposing a distinctive mechanism to secure the 1687 Network by embracing a counter strategy to thwart these attack to appease below stated challenges. Securing the 1687 Network by adopting a small, scaled Hardware in the design. Selectively locking the SIBs to secure the Highly secure Instruments in the design.

ABSTRACT. IEEE 1687 has been implemented to qualify a significantly sophisticated, compliant, and automated access to the mounting number of embedded instruments in today’s integrated circuits. These instruments facilitate experienced post-silicon validation, wafer sort, package test, burn-in, bring-up and manufacturing test of printed circuit board assemblies, power-on self-test, and in-field test.

The poster which has been presented here depicts an overview of the intricate challenges, the strategies adopted to get over from one foremost obstacle frequented with the Feedthrough connections in the Design.

This poster conferences about the deep scrutiny involved in tackling the issues pertaining to the Feedthrough connections and the solutions used to surpass the hitches by empowering the connection matrix related to the Host interfaces of the SIB/Pipeline logic correlated to the Feedthrough channels.

The described solution will help the designer using the Abutted design.

ABSTRACT. Automatic test equipment (ATE) for high-performance memory devices needs to transmit and receive ultra-high-speed data/clock waveforms with high fidelity. So far this has been achieved by applying intricate calibrations with external equipment, which requires significant time, cost, and effort. This paper proposes a Time-domain reflectometry (TDR)-based S-parameter estimation method by utilizing the drivers and comparators equipped in the input/output (I/O) pins of the ATE. Without the necessity of external equipment, the proposed method estimates the characteristics of the transmission line from the I/O to the DUT so that the waveforms at the DUT end are estimated and calibrated. The feasibility of the proposed calibration framework is demonstrated by the experimental results.

ABSTRACT. Implementing memory testing in AI chip designs with increasing gate numbers and decreasing gate sizes calls for solutions that improve test time while minimizing any overhead. The advanced memory dump feature integrated with memory test automation enables debugging of memory in functional mode and supports scalability when adding memories to a module. Additionally, vital routing resources are saved, and timing closure is eased with this approach. This poster will go over significant area reductions in the overall MBIST footprint and how advanced memory dump assists to dump out the contents of the arrays.

ABSTRACT. Enabling manufacturing testing in multi-tile package has been proven to be challenging. Multi-die parallel testing, test port accessibility and test time cost are some of many DFT challenges posing complex 2.5D/3D designs today. A Fast IO test port provides a small pin count footprint to access each dielet while addressing the bandwidth needs to meet test time targets and multi-tile parallel test strategy.

ABSTRACT. Quality and reliability concerns of embedded memories in complex SoC designs are becoming increasingly prevalent. In the case of AI chips, supporting a wide range of memory types and optimizing test time and test data volume is quite challenging. This poster will explore various faults including uncommon faults covered by the SMarchCHKBvcd algorithm.

ABSTRACT. A key requirement for silicon debug and continuous monitoring is to detect and isolate functional failures that escape structural tests. Another emerging consideration is to enable the fast detection of silent data corruption (SDC) which is a major concern for datacenters and warehouse scale computing. An embedded trace system that can collect time stamped data to analyze the trajectory of the transactions involving the CPU, memory, I/Os, peripherals, and other sub-systems, is a key component. This paper will use the case study of an embedded trace system developed based on the Efficient Trace for RISV-V (E-Trace) specification to highlight the central position it occupies in building a comprehensive SLM solution. Results on some industrial benchmarks demonstrate the efficiency of this approach.

ABSTRACT. In the recent decade of increasing advanced technology node, it is becoming very difficult to process the scaling of the devices. Stacking multiple dies in a single stack opens chip design to a world of unexplored challenges. One such challenge is testing of the individual dies and the integrated complex stack to improve DPM. Another challenge is testing the die-to-die interconnects between dies as the number of D2D can be very large and projected to grow rapidly. Our 3DIC DFT solution provides the key to handle the above stated challenges using IEEE-1838 compliant infrastructure with Multi-STAP. However multiple test challenges were involved to test the interconnect and the stacked dies. The poster depicts about the methodology and the challenges faced while developing the solution.

ABSTRACT. A test chip design aiming to test and diagnose the small delay faults in combinational cells of a cell library is proposed. The test chip design comprises C-testable test arrays and scan registers that are constructed in a two-dimensional format to achieve high testability and diagnosability. A novel approach is developed to systematically map each standard cell to a bijective-modified cell in order to make the test arrays C-testable. An efficient procedure is developed to enhance the test resolution for small delay defects (SDDs) testing. This procedure leverages the concept of mutually orthogonal Latin squares to place the modified cells in the test arrays such that the delays on the I-O paths in the test chip are balanced. Preliminary results show that under TSMC 40nm process technology, the test resolution for SDDs can achieve 0.077 ns

ABSTRACT. We explore synthetic generation of Process Control Monitoring (PCM) data and its accuracy, comparing to actual measurements from manufactured GlobalFoundries FinFET wafers. Our methodology leverages correlations across tests and locations, enhancing early process data availability.

ABSTRACT. Propagating faults to safety-critical primary outputs presents a significant challenge for ATPG tools. We propose a machine learning-based neural twin framework to generate safety-guided test patterns that can maximize faults' propagation capability towards critical outputs.

ABSTRACT. We present Efficient Spatial Clustering-based OUtlier detection through Telemetry (E-SCOUT) to monitor a chip's status through performance counters/sensors. Prior work does these at the software level and do not explore the hardware/software silicon lifecycle management (SLM) codesign. E-SCOUT provides novel SLM additions twofold. The first is outlier detection implemented at the SLM edge. The second is an end-to-end outlier detection and diagnosis performed with real telemetry data.

ABSTRACT. Screening for subtle defects and process variability that can result in timing failures and frequency-dependent silent data errors (SDE) is addressed through timing-aware scan tests. Vmin experiments on a server Core demonstrate promise of this approach.

ABSTRACT. In this work, we perform Built-In Self-Repair (BISR) of bridging faults occurring to cycle-based interconnects in a chiplet design. We fixed the potential “under-testing” problem in the traditional Pulse-Vanishing Test (PV-test) by adjusting the test pulse width in the test pulse signal, involving two steps – the offline adjustment procedure and the on-chip adjustment circuit. The adjusted PV-test scheme supports an at-speed BISR procedure for arbitrary interconnects in a chiplet design.

ABSTRACT. In modern Integrated Circuits (ICs), intra-cell defects have increased, and traditional fault models fail to represent them. Cell-Aware (CA) was introduced to tackle this problem, but it requires time-consuming analog SPICE simulations. To speed-up the CA model generation process, this paper presents a methodology based on graph theory that was trialed on combinational and sequential cells of two standard cell libraries.

ABSTRACT. In this paper, we review the electrical properties of marginal defects inserted in an SRAM device to evaluate test escapes in the latest technology. Defects introduced here can lead to different intermittent behaviors, some of which might not appear as fails during traditional testing procedures but might manifest as a system failure in the field. Subsequently, we present a new algorithm to improve test coverage efficiency.

ABSTRACT. Global control signals account for over 10% of circuit area and are challenging to diagnose when defects occur. This paper introduces a global signal diagnosis technique that is applicable in volume diagnosis. In addition to clock and scan enable signals, set and reset signals are also taken into account. The layout topology of global nets is utilized to enhance diagnosis accuracy and resolution. The effectiveness of this method is validated through several physical failure analysis results.

ABSTRACT. We develop a model to estimate lifetime performance, yield, and power of Static Random-Access Memories (SRAMs) that captures the combination of process variations and aging. Using this model, we design and validate predictive tests to detect future aging failures. We use the results of predictive tests to reconfigure dynamic voltage and frequency scaling (DVFS) to reduce aging failures at minimal energy and latency overheads.

ABSTRACT. Outsourcing SiPs to untrusted testing facilities in heterogeneous integration leads to overproduction and counterfeits. Our paper proposes SECT-HI, which secures SiP testing by granting test control to SiP designers and inserting watermarks to combat counterfeiting.

ABSTRACT. The paper introduces a simple and lightweight, yet effective and scalable, test data stream cipher developed for the Streaming Scan Network (SSN) technology to decrypt and encrypt the content of the IJTAG communication and the SSN bus. It builds on a hybrid ring generator working in tandem with two nonlinear Galois feedback shift registers to yield a large number of parallel, cryptographically secure pseudorandom keystreams. A comprehensive evaluation shows the efficiency of the proposed cipher.

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ABSTRACT. This paper describes a scan SerDes implementation to transfer test data between the IO-die and core-dice of a multi-die package. The goals include keeping it transparent to the SoC DFX logic, which can simply view it as a fixed number of pipeline stages, and minimizing ATPG programming overhead. This solution is particularly suitable for multi-die packages with narrow die-to-die interconnect link, where the narrowness of the interconnect can become a bottleneck for parallel test data transfer.

ABSTRACT. This paper describes a structural, scan-based DfT and ATPG technique for 'random analog' circuitry that has minimal area and performance impact. The tests can be applied by digital ATE and IEEE 1687 networks. Results show that automatically generated tests for a filter, bandgap + voltage regulator, 8-bit DAC, and 11-bit SAR ADC achieve comparable or higher coverage of IEEE P2427-specified shorts and opens, relative to specification tests, in <1 ms. Defect coverage can be simulated in <1 hour.

ABSTRACT. Functional state extraction of both sequential logic and arrays in a design is widely used in the industry to debug logic and timing bugs. Typically, this is done by repurposing logic and array test DFT that is already present in the design. In this paper, we describe the logic state extraction methodology as practiced in Intel servers, which is referred to as “scan dump”. First, we motivate the state extraction problem and provide contextual background. Secondly, we describe design-for-test (DFT) implementation in support of scan dump for state extraction. Thirdly, we describe the pre-silicon validation methodology for scan dump. Fourthly, we describe a set of best practices for implementing the scan dump feature. Finally, we describe an actual debug example using scan dump.

ABSTRACT. This paper proposes a new testing scheme for magnetic RAM (MRAM) that compensates for the additive line resistance effect by automatically adjusting the read reference using a memory built-in self-test (MBIST) circuit. The proposed method provides full defect screening coverage with a minor access time increase (~1N). The detected fault will be further evaluated for repair by ECC or redundancy bits to maximize product quality and yield.

ABSTRACT. This paper explores the effect of applying the external magnetic field (Hext) on the test quality of STT-MRAMs, which could be achieved by integrating magnets in the Automated Test Equipment (ATE). A framework of so-called Hext-based tests is put forward, and thereafter used to design tests for two unique defects as examples. Hext-based tests present superior coverage and time-efficiency than regular function tests; the effectiveness of these tests is validated through silicon measurements.

ABSTRACT. RRAMs are now undergoing commercialization. However, RRAMs are prone to exhibit new faults. Those unique faults require a specific Design-for-Testability (DfT) design. This paper proposes a DfT based on a write circuit that serves as a DfT scheme and as a normal write circuit simultaneously. Furthermore, the DfT is configurable for efficient diagnosis and yield learning. The results of the simulations show that the DfT is robust to process variations and can detect all RRAM faults.