View: session overviewtalk overview
Mike Slessor
Chief Executive Officer at FormFactor Inc.
Title: From the Shadows to the Spotlight – Probe’s Role in Enabling Electronics Industry Innovation
See: https://www.itctestweek.org/2024-keynote-visionary-talks/
Job fair on the exhibit floor. Visit recruitment booths.
| 10:30 | Power-Aware Test Scheduling for Memory BIST PRESENTER: Michal Kepinski ABSTRACT. An increasing number of embedded memory instances, despite lowering the power supply voltage and technology node size, leads to higher power dissipation during the memory test phase when manufacturing an SoC. The paper comprises two topics. First, it presents a toolchain aimed at a thorough monitoring of the power dispersed by memory instances and associated Memory BIST instruments. Secondly, several algorithms are proposed that optimize the memory test scheduling for a commercial DFT tool. |
| 11:00 | Deterministic In-Fleet Scan Test for a Cloud Computing Platform PRESENTER: Dan Trock ABSTRACT. The paper demonstrates a successful application of the Streaming Scan Network technology to run in-fleet deterministic scan testing on an ultralarge industrial multi-chiplet design at Amazon Web Services (AWS) cloud. One of the key advantages of the presented technology is its ability to use the same infrastructure to perform both manufacturing and in-field tests. A silicon implementation along with test power analysis are also presented. |
| 11:30 | A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS PRESENTER: Kunal Jain Mangilal ABSTRACT. Streaming scan test architectures can greatly optimize the test data delivery to large industrial designs. This paper discusses what happens when such architectures are combined with nearly unlimited data bandwidth provided by NVIDIA MATHS (Mechanism to Access Test-Data over High-Speed Link). We have architected various techniques for efficient use of bandwidth & debug techniques for silicon bring-up. This was designed for highest throughput to test multiple chiplets in parallel. |
JTAG IEEE 1687 – Upping the Game for the Next Decade
The IJTAG standard IEEE1687 has had wide adoption within the industry and is the most influential DfT standard since IEEE 1149.1. After 10 years the next generation is around the corner. It will do much more than just making incremental improvements based on feedback from users. So, the base standard is undergoing a major revision after its first decade. The P1687.1 extension got a refocus and P1687.2 is nearing its completion. The prime driver behind the revision and the extensions is to widen the application of the IJTAG standard principles to real-world challenges. The major developments of the past two years range from basic things like bidirectional signals and switches (relays) to the concept of transfer procedures that describe behavioural blocks (arbitrary low pin count test interfaces, A/D converters, etc.), supporting both the analog and the digital aspects of test. This is also the case for PDL, which got a major update to better match real-world test program behaviour. Stay tuned!
- IJTAG Family Update – Learn from the Children, Martin Keim, Siemens
- IJTAG Goes Real-World, Hans Martin von Staudt, Renesas
- ITJAG PDL2 Describes Real Test Programs, Jeff Rearick, AMD
- IJTAG.1 There and Back Again, a Databit’s “EHPIC” Journey, Michael Laisne, Renesas
| 10:30 | LESER-2: Detailed Consideration in Latch Design under Process Migration for Prevention of Single-Event Double-Node Upsets PRESENTER: Lowry P.-T. Wang ABSTRACT. SEDU threatens sub-65nm cells, nullifying traditional methods. Original LESER offers 100% SEDU tolerance with minimal overhead but lacks wider applicability. New LESER maintains a two-stage structure, enhancing device and circuit levels for accurate simulation and precise resolution. Experiments show 100% soft error protection with 16.5% area cost. New LESER efficiently guards against SEDU, suitable for industrial processes. |
| 11:00 | A graph-based algorithm for NVM address decoders testing PRESENTER: Pierre Scaramuzza ABSTRACT. This paper introduces a solution for screening defective memory address decoders, with a special focus on RRAM modules architectures. The strength of the proposed approach relies on the definition of a decoder graph model and on an optimal algorithm to traverse it. The presented software-based test decreases field application returns and ensures a consistent test time reduction with respect to the previous implementation. |
| 11:30 | TEACH: Outlier Oriented Testing of Analog/Mixed-Signal Circuits Using One-class Clustering in Hyperdimensional Spaces PRESENTER: Mohamed Mejri ABSTRACT. Specification testing of embedded analog/mixed-signal(AMS) circuits is difficult due to the inability to measure critical specs in-situ.To resolve this, we propose novel test stimulus generation using clustering of test data in hyperdimensional spaces that maximizes the sensitivity of the test response to outlier defects and process variations.A one-class hyperdimensional classifier is used to separate pass vs. fail devices.Simulation results on test circuits show the benefits of this approach. |
- “In-Field Test under PVT-Variations”, Hans-Joachim Wunderlich, University of Stuttgart
- “Addressing SDC challenges with Silicon Lifecycle Management”, Yervant Zorian, Jyotika Athavale, Synopsys
- "Silent Data Corruptions in AI Workloads - A Deep Dive", Harish Dattatraya Dixit, Meta
| 13:30 | AI-Enabled Board Level Vibration Testing: Unveiling the Physics of Degradation PRESENTER: Chen He ABSTRACT. The reliability requirements of electronic packages for safety-critical applications have spurred developments in real-time monitoring of components. A key aspect of these advancements is the availability of physical health sensing elements and failure-predicting algorithms that can be embedded within the IC. Here, 4-wire resistance measurement features are embedded in packages to detect physical damages at the PCB-solder interface. Several AI algorithms are assessed under vibration loads. |
| 14:00 | Virtual Test Development Using Pre-Silicon Verification Environment PRESENTER: Ernst Aderholz ABSTRACT. The demand for a fast time to market in the semiconductor industry requires novel approaches to speed up test package development. This paper describes the Virtual Test Development. It uses the pre-Si verification environment and the top-level IC design to simulate test cases, especially for the complex mixed-signal blocks. The paper describes the process and models for VTD. Using VTD, we can reduce the test development cycle time significantly by capturing test program issues in pre-Si phase. |
| 14:30 | Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard PRESENTER: Ankita Patidar ABSTRACT. Interconnect clusters on a chiplet in a multi-die system are arranged in bump array patterns. The most common defects affecting them are shorts and opens. In this paper, we present a fully automated EDA tool flow that extracts physical location of all interconnects using 3Dblox Open standard and generates physical-aware test patterns for an optimized set of die-to-die interconnects. This results in testing all relevant interconnects that are critical for a defect free 3DIC system. |
IEEE Standards – Keeping Up with the Moore’s
As the old panel title alluded to, IEEE Std 1149.1 is not dead. And neither is Moore’s Law. But clearly, industry is in the midst of turning a corner. Chiplets are modernizing Moore’s Law, and literally up-leveling it. What test methodologies need to change with it as chiplets come to the fore of the electronics design industry? The new buzzword in multi-die design is “interface.” Each chiplet will need to interface with another chiplet or the outside world. This session will educate you on what IEEE Std P1149.1 is (and is not) doing to keep up. Interfaced perfectly with 1149.1, IEEE Std P1838a is also adding and clarifying facilities to help access and test certain categories of 2.5D and 3D multi-die package content. That leaves a lot of interfaces to address. So, IEEE Std P3405 is defining a set of constructs to help test and repair all the interface connections between chiplets. Come to this session to get updated and educated about how these IEEE standards are keeping pace with industry’s new direction.
P1149.1: Alive and Kicking, Jason Doege, Siemens
P1838a: Asked and Answered, Adam Cron, Synopsys
P3405: Make it So, Sreejit Chakravarty, Ampere Computing
Moderator: Savita Banerjee, Sr. Manager, Meta
Panelists:
Rob Aitken, Program Manager, NAPMP CHIPS R&D Office
Yervant Zorian, Fellow & Chief Architect, Synposys
Jennifer Dworak, Texoma Semi Tech Hub Professor, ECE, SMU
Krishnendu Chakrabarty, CTO, SWAP Hub, DoD Professor, EECE, ASU
The CHIPS Act provided over $280 billion for advanced chip manufacturing, packaging, and workforce development. The latest NOFO is out, and the ideas are flowing. This special session assembles experts who are actively leading critical CHIPS workstreams. They will discuss the importance of this national initiative, the ecosystem that needs to be developed to ensure its goals are achieved as well as the challenges that need the broader tech community to support. See how you can contribute to this historic effort and join the conversation.
1. Best Paper: Optimized Timing Aware ATPG for At-Speed Test of Cell Internal Faults,
Authors: Aneri Jain (Google), Wilson Pradeep* (Google) and Andreas Glowatz (Siemens)
2. 1st Honorable Mention: An FPGA based Emulation of Source Synchronous Protocol-Aware Timing Stress Test,
Authors: Prrk Tirumalesu Manda*, Vinodh J Rakesh, Vasavi Ghanta and Jagadish Raju Krishna Raju
Affiliation: Infineon Technologies India Pvt. Ltd.