ABSTRACT. An increasing number of embedded memory instances, despite lowering the power supply voltage and technology node size, leads to higher power dissipation during the memory test phase when manufacturing an SoC. The paper comprises two topics. First, it presents a toolchain aimed at a thorough monitoring of the power dispersed by memory instances and associated Memory BIST instruments. Secondly, several algorithms are proposed that optimize the memory test scheduling for a commercial DFT tool.

ABSTRACT. The paper demonstrates a successful application of the Streaming Scan Network technology to run in-fleet deterministic scan test on an ultralarge industrial multi-chiplet design at the heart of Amazon Web Services (AWS) cloud computing platform. One of the key advantages of the presented technology is its ability to use the same infrastructure to perform both manufacturing and in-field tests. A silicon implementation along with test power analysis are also presented.

ABSTRACT. Streaming scan test architectures can greatly optimize the test data delivery to large industrial designs. This paper discusses what happens when such architectures are combined with nearly unlimited data bandwidth provided by NVIDIA MATHS (Mechanism to Access Test-Data over High-Speed Link). We have architected various techniques for efficient use of bandwidth & debug techniques for silicon bring-up. This was designed for highest throughput to test multiple chiplets in parallel.

ABSTRACT. The reliability requirements of electronic packages for safety-critical applications have spurred developments in real-time monitoring of components. A key aspect of these advancements is the availability of physical health sensing elements and failure-predicting algorithms that can be embedded within the IC. Here, 4-wire resistance measurement features are embedded in packages to detect physical damages at the PCB-solder interface. Several AI algorithms are assessed under vibration loads.

ABSTRACT. The demand for a fast time to market in the semiconductor industry requires novel approaches to speed up test package development. This paper describes the Virtual Test Development. It uses the pre-Si verification environment and the top-level IC design to simulate test cases, especially for the complex mixed-signal blocks. The paper describes the process and models for VTD. Using VTD, we can reduce the test development cycle time significantly by capturing test program issues in pre-Si phase.

ABSTRACT. Interconnect clusters on a chiplet in a multi-die system are arranged in bump array patterns. The most common defects affecting them are shorts and opens. In this paper, we present a fully automated EDA tool flow that extracts physical location of all interconnects using 3Dblox Open standard and generates physical-aware test patterns for an optimized set of die-to-die interconnects. This results in testing all relevant interconnects that are critical for a defect free 3DIC system.

ABSTRACT. SEDU threatens sub-65nm cells, nullifying traditional methods. Original LESER offers 100% SEDU tolerance with minimal overhead but lacks wider applicability. New LESER maintains a two-stage structure, enhancing device and circuit levels for accurate simulation and precise resolution. Experiments show 100% soft error protection with 16.5% area cost. New LESER efficiently guards against SEDU, suitable for industrial processes.

ABSTRACT. This paper introduces a solution for screening defective memory address decoders, with a special focus on RRAM modules architectures. The strength of the proposed approach relies on the definition of a decoder graph model and on an optimal algorithm to traverse it. The presented software-based test decreases field application returns and ensures a consistent test time reduction with respect to the previous implementation.

ABSTRACT. Specification testing of embedded analog/mixed-signal(AMS) circuits is difficult due to the inability to measure critical specs in-situ.To resolve this, we propose novel test stimulus generation using clustering of test data in hyperdimensional spaces that maximizes the sensitivity of the test response to outlier defects and process variations.A one-class hyperdimensional classifier is used to separate pass vs. fail devices.Simulation results on test circuits show the benefits of this approach.