ITC 2021: INTERNATIONAL TEST CONFERENCE
PROGRAM

Days: Tuesday, October 12th Wednesday, October 13th Thursday, October 14th

Tuesday, October 12th

View this program: with abstractssession overviewtalk overview

08:00-08:30 Session Opening

General Chair: Jennifer Dworak

Program Chair: Teresa McLaurin

TTTC President: Yervant Zorian

2022 Program Chair: Kuen-Jong Lee

09:00-09:30Coffee Break (Social Time in Gather.Town)
09:30-10:30 Session 1A: Enhancing Testability
Location: Zoom Room A
09:30
A Fast and Low Cost Embedded Test Solution for CMOS Image Sensors (abstract)
PRESENTER: Julia Lefevre
09:50
ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph (abstract)
10:10
Testability-Enhancing Resynthesis of Reconfigurable Scan Networks (abstract)
PRESENTER: Natalia Lylina
09:30-10:30 Session 1B: ML for Diagnosis
Location: Zoom Room B
09:30
Machine Learning for Circuit Aging Estimation under Workload Dependency (abstract)
PRESENTER: Florian Klemme
09:50
Adaptive NN-based Root Cause Analysis in Volume Diagnosis for Yield Improvement (abstract)
PRESENTER: Xin Huang
10:10
Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning (abstract)
PRESENTER: Chun Chen
09:30-10:30 Session 1C: Special Session: Start to Finish: 2.5D and 3D Device Testing Challenges and Solutions

With the help of standards, like IEEE 1687, IEEE 1838, and the currently completing second edition of IEEE 1500, the industry could consider the test challenges of 3D devices solved. The reality is far from it. While these standards certainly play an important role in any DFT solution for 3D devices (and to an extend to 2.5D devices or any combination thereof), there are wide gaps to be filled. These gaps prevent a coherent picture how to fully test such devices at each integration level. It became apparent at past conferences and workshops, that today only partial solutions exist, looking at one or the other slice of the DFT puzzle. Many details are not yet fully understood and to a certain degree, confusion reigns in our industry. To address this, the proposed special session, with its representative cross-section of our industry, focuses on drawing a complete and coherent picture of Design-for-Test for 3D devices

Location: Zoom Room C
09:30
Moderator: Intro and framing of the session (abstract)
09:45
3DIC Test Challenges, Trends and Solutions - an EDA perspective
10:00
Designing and testing 3D devices – A fabless company perspective
10:15
Testing challenges and solutions for advanced packaging technologies - A foundry perspective
09:30-10:30 Session 1D: ITC-Asia 2021 Top 3 papers
Chair:
Location: Zoom Room D
09:30
Smart Sampling for Efficient System Level Test: A Robust Machine Learning Approach (abstract)
PRESENTER: Chenwen Liu
09:50
The Security Enhancement Techniques of the Double-layer PUF Against the ANN-based Modeling Attack (abstract)
PRESENTER: Yongliang Chen
10:10
Software-Based Self-Test for Transition Delay Faults in Pipelined Processors (abstract)
10:30-11:00Coffee Break (Social Time in Gather.Town)
11:00-12:00Diamond Supporter Presentation
12:00-13:00 Session 2A: AI Hardware

AI Hardware

Location: Zoom Room A
12:00
On-line Functional Testing of Memristor-mapped Deep Neural Networks using Backdoored Checksums (abstract)
PRESENTER: Ching-Yuan Chen
12:20
Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin (abstract)
PRESENTER: Arjun Chaudhuri
12:40
Functional In-Field Self-Test with Ultra-HighTest-Coverage for Deep Learning Accelerators (abstract)
PRESENTER: Yi He
12:00-13:00 Session 2B: Wafer Map Classification I

Wafer map pattern recognition, analysis, and classification

Location: Zoom Room B
12:00
Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process (abstract)
12:20
Brain-Inspired Computing for Wafer Map Defect Pattern Classification (abstract)
PRESENTER: Paul R. Genssler
12:40
Semi-supervised Wafer Map Pattern Recognition using Domain-Specific Data Augmentation and Contrastive Learning (abstract)
PRESENTER: Hanbin Hu
12:00-13:00 Session 2C: Special Session: STT-MRAMs: Technology, Design and Test

The conventional embedded memories such as Static Random Access Memories (SRAM), embedded Dynamic Random Access Memory (eDRAM) and eFlash are now struggling to meet the increasing demands in terms of energy efficiency, reliability, scalability and manufacturing costs [1]. As one of the most promising non-volatile memory technologies, spin-transfer torque magnetic random access memory (STTMRAM) offers competitive write/read performance, endurance, density, retention, and power consumption benefits [2]. The tunability of these aspects makes it customizable as both embedded and discrete memory solutions for a variety of applications such as Internet-of-Things (IoT), automotive, aerospace, and last-level caches [3]. Therefore, STT-MRAM technology has received a large amount of attention for commercialization from major semiconductor companies such as Everspin, TSMC, Samsung, and Intel [3–5]. This session will address different aspects of STT-MRAM; it will cover state-of-the art, some new results and future challenging related to technology, design and test. While STT-MRAM devices have shown encouraging performance metrics at device-level, a key challenge has been achieving backend-of-line (BEOL) CMOS compatibility, while retaining the benefits of low power operation. Scaling demands to improve data densities have placed additional challenges in terms of addressing the impact of process- induced damage on device performance at CDs < 100 nm. In addition, the session will discuss the design of reliable read mechanism considering the variability effects. Moreover, the session will demonstrate based on silicon data how traditional fault modeling and test approaches fail to model STT-MRAM unique defects and hence fail in providing appropriate test solutions.

Location: Zoom Room C
12:00
STT-MRAM technology for embedded applications (abstract)
12:20
Design of Reliable Sensing Mechanisms in STT-MRAM (abstract)
12:40
Device-Aware Test for STT-MRAM (abstract)
12:00-13:00 Session 2D: TTTC McCluskey PhD Competition
Location: Zoom Room D
12:00
Study on High-Accuracy and Low-Cost Recycled FPGA Detection (abstract)
12:20
Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions (abstract)
12:50
Adaptive Methods for Machine Learning-Based Testing of Integrated Circuits and Boards (abstract)
13:00-14:00Lunch Break (Social Time in Gather.Town)
14:00-15:00 Session P1: SLT - What is it today? Why is it needed?

The panelists will discuss a series of topics about SLT such as:

After all the ATE/structural testing done -- why is SLT needed ?

Is SLT done broadly for 100% of products ? Or is it only done on sample ?

Is the use growing or staying steady?

Does SLT only focus on adding functional test content ? Or are people adding a lot of structural tests ? –

How does ATE Final Test change if SLT is done ?

How do SLT requirements change for different applications ? High end processors. Data Centers / AI / ML Mobile processors Auto ICs –

System-level perspective -- how to enable component SLT to deliver higher quality systems ?

Organizer/Moderator: Phil Nigh

Panelists: Harry Chen (Mediatek), Sajjad Pagarkar (Google), Davide Appello (ST Microelectronics), John Yi (AMD), Paul Maccoux (Intel)

Chair:
Location: Zoom Room A
14:00-15:00 Session P2: What is the best high-speed I/O Test Method: 1149.10 or high speed I/O protocol?

Because shorter digital test time with an increasingly limited number of pins is a constant goal for manufacturing test, various high test bandwidth methods have been deployed with others in the final stages of development. While ad-hoc methods, such as using serializing-deserializing techniques, were coming online, the IEEE 1149.10 standard appeared. The standard defines a common high-speed interface for greater digital test bandwidth (especially for scan patterns), but practical considerations regarding physical implementation could potentially inhibit its deployment. On the other hand, functional high-speed interfaces, with defined protocols already exist for functional data could be reused for test data, but no standard exists for such applications. What are the advantages and disadvantages of using IEEE 1149.10 vs functional high-speed I/O such as USB and PCIe? Are there any other competing high-speed I/O techniques? What are the practical considerations for any such solution? And, how soon will DFT teams need to consider using a highspeed I/O for test data?

Organizers: Ramsay Allen/Robert Ruiz (Synopsys)

Moderator: Anne Meixner

Panelists: Claudia Bertani (ST Microelectronics), Klaus-Dieter Hilliges (Advantest-Europe), Steve Pateras (Synopsys), Suketu Bhatt (Intel)

Location: Zoom Room B
15:00-16:00Dedicated Social Networking in Gather.Town (Diamond & Platinum Supporter Recognition)
Wednesday, October 13th

View this program: with abstractssession overviewtalk overview

09:00-09:30Coffee Break (Social Time in Gather.Town)
09:30-10:30 Session 3A: Security Hardware
Location: Zoom Room A
09:30
Impeccable Circuits III (abstract)
09:50
A BIST-based Dynamic Obfuscation Scheme for Resilience against Removal and Oracle-guided Attacks (abstract)
PRESENTER: Jonti Talukdar
10:10
LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment (abstract)
PRESENTER: M Sazadur Rahman
09:30-10:30 Session 3B: Wafer Map Classification II
Location: Zoom Room B
09:30
Triplet Convolutional Networks for Classifying Mixed-Type WBM Patterns with Noisy Labels (abstract)
PRESENTER: Chenwei Liu
09:50
Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling (abstract)
10:10
MINiature Interactive Offset Networks (MINIONs) for Wafer Map Classification (abstract)
09:30-10:30 Session 3C: Special Session: Current Development in Test Standards

An update on a few of the test standards currently being developed or updated. Discussion that standards need to evolve to meet the changing needs of the industries that rely on them.

Location: Zoom Room C
09:30
Revisions to IEEE Std 1500, Standard Testability Method for Embedded Core-based Integrated Circuits
09:50
IEEE P1687.1: The Trouble with Transforms
10:10
Assisting board level connectivity test with IEEE Std 1581
09:30-10:30 Session 3D: ITC-India 2021 Top 3 Papers
Location: Zoom Room D
09:30
Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis (best paper award, ITC-India 2021) (abstract)
PRESENTER: Aravinda Acharya
09:50
Addressing High Speed Memory Interface Test Quality Gaps in Shared Bus Architecture (1st honorable mention paper award, ITC-India 2021) (abstract)
PRESENTER: Wilson Pradeep
10:10
A Novel Method to measure PLL Bandwidth in a 5G RF transceiver (2nd honorable mention paper award, ITC-India 2021) (abstract)
PRESENTER: Pradeep Nair
10:30-11:00Coffee Break (Social Time in Gather.Town)
11:00-12:00Supporter/Exhibitor Presentations
12:00-13:00 Session 4A: Secure and Trusted Microelectronics
Location: Zoom Room A
12:00
Characterizing Corruptibility of Logic Locks using ATPG (abstract)
12:20
SymbA: Symbolic Execution at C-level for Hardware Trojan Activation (abstract)
PRESENTER: Arash Vafaei
12:40
Security and Provisioning of Automotive IC’s through Test and Safety (abstract)
12:00-13:00 Session 4B: Failure Diagnosis
Location: Zoom Room B
12:00
Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization (abstract)
PRESENTER: Cheng-Sian Kuo
12:20
Relevant Signals and Devices for Failure Analysis of Analog and Mixed-signal Circuits (abstract)
12:40
Open-short Normalization Method for a Quick Defect Identification in Branched Traces with High-resolution Time-domain Reflectometry (abstract)
PRESENTER: Yang Shang
12:00-13:00 Session 4C: Test Enhancements
Location: Zoom Room C
12:00
On Reduction of Deterministic Test Pattern Sets (abstract)
PRESENTER: Janusz Rajski
12:20
Multi-Transition Fault Model (MTFM) ATPG patterns towards achieving 0 DPPB on AUTOMOTIVE designs (abstract)
PRESENTER: Saidapet Ramesh
12:40
Analyzing and Mitigating Sensing Failures in Spintronic-based Computing in Memory (abstract)
PRESENTER: Mahta Mayahinia
12:00-13:00 Session 4D: ET1: Memory Testing Embedded Tutorial

This embedded tutorial is divided into three modules addressing various aspects of memory BIST. Modern chips can contain over a Gigabit of memory distributed over thousands of macros. These memories need to be thoroughly tested and repaired at manufacturing time and in-system and in increasing number of applications. The first module provides a comprehensive checklist of requirements for engineers responsible for the implementation and verification of memory BIST. Memory repair has become a necessary condition to obtain acceptable yields in advanced technologies. The second module explores the impact of memory repair on area and techniques to reduce this impact. Emerging memory technologies introduce new challenges for memory BIST. The third module introduces some of them such as fault modeling, repair and trimming related to embedded MRAM.

Location: Zoom Room D
12:00
Memory BIST requirements
12:20
Memory repair
12:40
Built-in self-test functions to mitigate eMRAM test challenges
13:00-14:00Lunch Break (Social Time in Gather.Town)
14:00-15:00 Session P3: Talk to the TTSC (Test Technology Standard Committee)

Rather than a traditional panel, this will be an interactive session in which the audience can ask questions of the Test Technology Standards Committee members, and even make requests and provide feedback and guidance. Likewise, the TTSC members could survey the audience as well.

Possible topics include:

• Do we have holes in any of our test standards?

• Do we have any idea how widely-used our standards are?

• How do we gauge adoption rates?

• How do we get feedback on the technical aspects of standards?

• Where should we use one standard instead of another? How do they fit together?

• Should there be an architecture board at the TTSC level to help make sure that things fit together?

• Can we create one unifying language for all the TTSC standards?

• Should we do a better job of promoting standards to encourage adoption?

• Should the TTSC take an active role in creating and maintaining examples? Do we need an application engineer per standard? Or is this the job of the EDA companies?

• How should a standard be supported? Can we keep the e-mail reflectors active and staffed?

• Is security something that we should tackle in a standard?

• What do the stakeholders and users and volunteers in the standards community want from TTSC, and what can TTSC do better?

Organizer: Mike Ricchetti

Moderator: Jeff Rearick

Location: Zoom Room A
14:00-15:30 Session Poster: Poster Session

Note all poster videos and authors are available for the full session time. Poster videos are available for viewing throughout the conference.

Location: Gather.Town
14:00
Understanding Tool Synthesis Behavior and Safe Finite State Machine Design (abstract)
PRESENTER: Tim McDonley
14:05
Generalized Insider Attack Detection Implementation using NetFlow Data for Distributed Test Range Networks (abstract)
PRESENTER: Yash Samtani
14:10
FR4 could be better than Tachyon-100G for post-silicon validation on LVDS signaling (abstract)
14:15
Defect-Directed Stress Testing Using I-PAT Inline Defect Inspection Results (abstract)
PRESENTER: Chen He
14:20
Layout Informed Multiple Bit Upset Hardening of Finite State Machines (abstract)
PRESENTER: Tim McDonley
14:25
Power-Aware ATPG Using Sign-Off Models (abstract)
14:30
In-Field Embedded Sensing & PVT Monitoring for Increased Device Power and Performance Optimization (abstract)
14:35
Jitter Injection with pre- and post- emphasis circuits (abstract)
PRESENTER: Tm Mak
14:40
A Novel Fault Grading Technique to Establish RTL-ATPG Top-Off Coverage (abstract)
PRESENTER: Pawini Mahajan
14:45
Unified Test Flow for DFT Power, Performance & Area Optimization (abstract)
PRESENTER: Surya Duggirala
14:50
A Multi-Threaded Single-Pass Diagnosis of Scan Chain Failures (abstract)
PRESENTER: Emil Gizdarski
14:55
High Bandwidth Current Sourcing with the Howland Current Source (abstract)
15:00
Practical Methods to Test MIPI C-Phy Data Interfaces (abstract)
15:05
Utilizing IEEE Std 1687 for board level test (abstract)
PRESENTER: Heiko Ehrenberg
Thursday, October 14th

View this program: with abstractssession overviewtalk overview

09:00-09:30Coffee Break (Social Time in Gather.Town)
09:30-10:30 Session 5A: Circuits and Monitors (Ind. Papers)
Location: Zoom Room A
09:30
Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies (abstract)
PRESENTER: Keno Sato
09:45
Adaptive High Voltage Stress Methodology to Enable Automotive Quality on FinFET Technologies (abstract)
PRESENTER: Stephen Traynor
10:00
3.5Gsps MIPI C-PHY Receiver Circuit for Automatic Test Equipment (abstract)
PRESENTER: Seongkwan Lee
10:15
A Scalable Design Flow for Performance Monitors Using Functional Path Ring Oscillators (abstract)
PRESENTER: Tobias Kilian
09:30-10:30 Session 5B: Test Data (Short Paper)
Location: Zoom Room B
09:30
WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques (abstract)
PRESENTER: Peter Yi-Yu Liao
09:45
AAA: Automated On-ATE AI Debug of Scan Chain Failures (abstract)
PRESENTER: Chris Nigh
10:00
Systematic Hardware Error Identification and Calibration for Massive Multisite Testing (abstract)
PRESENTER: Praise Farayola
10:15
Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits (abstract)
PRESENTER: Yi Sun
09:30-10:30 Session 5C: Test Architecture and Infrastructure (Short Paper)
Location: Zoom Room C
09:30
Is your secure test infrastructure secure enough? Attacks based on delay test patterns using transient behavior analysis (abstract)
PRESENTER: Sergej Meschkov
09:45
Seamless Physical Implementation of ASIC Hierarchical Integrated Scan Architecture (abstract)
PRESENTER: Bambang Suparjo
10:00
Testability-Aware Low Power Controller Design with Evolutionary Learning (abstract)
PRESENTER: Min Li
10:15
An automated formal-based approach for reducing Undetected faults in ISO26262 hardware compliant designs (abstract)
10:30-11:00Coffee Break (Social Time in Gather.Town)
11:00-12:00Supporter/Exhibitor Presentations
12:00-13:00 Session 6A: What's going on with 1687*?
Location: Zoom Room A
12:00
Security EDA Extension through P1687.1 and 1687 Callbacks (abstract)
12:20
Accessing general IEEE Std. 1687 networks via functional ports (abstract)
PRESENTER: Erik Larsson
12:40
(Invited) IEEE P1687.1 Data Retargeting and Transfer Procedures for Accessing Internal Cores (abstract)
PRESENTER: Michael Laisne
12:00-13:00 Session 6B: Analog Testing
Location: Zoom Room B
12:00
Operational Amplifier AC Characteristics Testing by Summing Node Method (abstract)
PRESENTER: Daisuke Iimori
12:20
Automatic Verification of Mixed-Signal ATE Test Programs using Device Variation (abstract)
PRESENTER: Franziska Mayer
12:40
Background Receiver IQ Imbalance Correction for in-Field and Post-Production Testing and Calibration (abstract)
PRESENTER: Muslum Emir Avci
12:00-13:00 Session 6C: Automotive FuSa Tolerance
Location: Zoom Room C
12:00
Exploiting Application Tolerance for Functional Safety (abstract)
12:20
Hierarchical Failure Modeling and Machine Learning Assisted Correction of Subsystem Failures in Autonomous Vehicles (abstract)
12:40
Compositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation (abstract)
13:00-14:00Lunch Break (Social Time in Gather.Town)
14:00-15:00 Session P4: Challenges of 3rd party IPs to achieve Automotive Zero Defect quality and Functional Safety

The advent of autonomous driving as well as the switch towards electric cars are causing a continuous growth of the electronic content in modern vehicles. As a result, automotive semiconductor manufacturers are demanded to meet Zero Defect (ZD) quality level as well as Functional Safety (FuSa) requirements. Testing and stressing to screen out potential early life failures caused by extrinsic defects is crucial to ensure ZD quality. However, screening defects is only as good as the test and stress coverage enabled in the design. Design for ZD needs to be addressed at both IP level and SOC/SIP (system on chip/system in package) level. As the technology feature size keeps scaling down, the design complexity has increased exponentially. Driven by cost and time-to-market considerations, it has become more and more popular for automotive semiconductor suppliers to adopt the off-the-shelf 3rd party IPs on their SOC/SIPs. This, however, poses unique challenges on ZD testing and stressing due to the lack of automotive ZD stress/test requirements built in the 3rd party IPs as well as the lack of the detailed design knowledge of those IPs from the system integration point of view. Adding manufacturing test flow awareness to the DFT/stress guidelines followed by IP providers is not straightforward. Information about how transforming provided fault coverage achievements into actual test coverage is not part of the typical IP utilization guidelines. Consequently we have seen cases in which the 3rd -party IP were not tested or stressed sufficiently resulting in quality issues as well as cases in which the 3rd -party IPs were overstressed and caused qualification failures. Meanwhile, FuSa is usually considered at the system level, not at the IP level. Moreover, for different FuSa integrity levels, we may need different stress testing requirements. How to ensure the 3rd party IP designs meet FuSa requirements while achieving ZD quality in a systemic and holistic way has become a common but important challenge faced by the automotive semiconductor industry. It is important to clearly define the requirements for IP providers before the design starts and make sure they have the effectively access to all necessary inputs regarding to the ZD quality and FuSa objectives. In this panel, experts in this field will exchange their views and discuss possible solutions and remaining challenges on this important topic.

Organizer and Moderator: Chen He (NXP)

Panelists: Davide Appello (ST Microelectronics), Wim Dobbelaere (ON Semiconductor), Fei Su (Intel), Daniel Tille (Infineon), Jody Defazio (Synopsys), John Xu (Xscend Technology)

Chair:
Location: Zoom Room A