General Chair: Jennifer Dworak

Program Chair: Teresa McLaurin

TTTC President: Yervant Zorian

2022 Program Chair: Kuen-Jong Lee

Please see ITC site at: http://www.itctestweek.org/2021-keynote-talks/

The panelists will discuss a series of topics about SLT such as:

After all the ATE/structural testing done -- why is SLT needed ?

Is SLT done broadly for 100% of products ? Or is it only done on sample ?

Is the use growing or staying steady?

Does SLT only focus on adding functional test content ? Or are people adding a lot of structural tests ? –

How does ATE Final Test change if SLT is done ?

How do SLT requirements change for different applications ? High end processors. Data Centers / AI / ML Mobile processors Auto ICs –

System-level perspective -- how to enable component SLT to deliver higher quality systems ?

Organizer/Moderator: Phil Nigh

Panelists: Harry Chen (Mediatek), Sajjad Pagarkar (Google), Davide Appello (ST Microelectronics), John Yi (AMD), Paul Maccoux (Intel)

Because shorter digital test time with an increasingly limited number of pins is a constant goal for manufacturing test, various high test bandwidth methods have been deployed with others in the final stages of development. While ad-hoc methods, such as using serializing-deserializing techniques, were coming online, the IEEE 1149.10 standard appeared. The standard defines a common high-speed interface for greater digital test bandwidth (especially for scan patterns), but practical considerations regarding physical implementation could potentially inhibit its deployment. On the other hand, functional high-speed interfaces, with defined protocols already exist for functional data could be reused for test data, but no standard exists for such applications. What are the advantages and disadvantages of using IEEE 1149.10 vs functional high-speed I/O such as USB and PCIe? Are there any other competing high-speed I/O techniques? What are the practical considerations for any such solution? And, how soon will DFT teams need to consider using a highspeed I/O for test data?

Organizers: Ramsay Allen/Robert Ruiz (Synopsys)

Moderator: Anne Meixner

Panelists: Claudia Bertani (ST Microelectronics), Klaus-Dieter Hilliges (Advantest-Europe), Steve Pateras (Synopsys), Suketu Bhatt (Intel)

Please see ITC site at: http://www.itctestweek.org/2021-keynote-talks/

Rather than a traditional panel, this will be an interactive session in which the audience can ask questions of the Test Technology Standards Committee members, and even make requests and provide feedback and guidance. Likewise, the TTSC members will survey the audience.

Possible topics include:

• Do we have holes in any of our test standards?

• Do we have any idea how widely-used our standards are?

• How do we gauge adoption rates?

• How do we get feedback on the technical aspects of standards?

• Where should we use one standard instead of another? How do they fit together?

• Should there be an architecture board at the TTSC level to help make sure that things fit together?

• Can we create one unifying language for all the TTSC standards?

• Should we do a better job of promoting standards to encourage adoption?

• Should the TTSC take an active role in creating and maintaining examples? Do we need an application engineer per standard? Or is this the job of the EDA companies?

• How should a standard be supported? Can we keep the e-mail reflectors active and staffed?

• Is security something that we should tackle in a standard?

• What do the stakeholders and users and volunteers in the standards community want from TTSC, and what can TTSC do better?

Organizer: Mike Ricchetti

Moderator: Jeff Rearick

Panelists: Erik Jan Marinissen (IMEC), Adam Cron (Synopsys), Heiko Ehrenberg (Goepel USA), Yervant Zorian (Synopsys)

Please see ITC site at: http://www.itctestweek.org/2021-keynote-talks/

An informative session about a new Functional Safety standard being developed by Accellera. We have all the WG leads present to discuss it. 

Organizers: Nir Maor, Qualcomm &  Yervant Zorian, Synopsys

Moderators: Alessandra Nardi, Cadence & Nir Maor, Qualcomm

Discussants:

- Ghani Kanawati, Arm

- Andres Barrilado, NXP

- Meirav Nitzan, Synopsys

- Bala Chavali, AMD  

- Shrenik Mehta, Xilinx   

The advent of autonomous driving as well as the switch towards electric cars are causing a continuous growth of the electronic content in modern vehicles. As a result, automotive semiconductor manufacturers are demanded to meet Zero Defect (ZD) quality level as well as Functional Safety (FuSa) requirements. Testing and stressing to screen out potential early life failures caused by extrinsic defects is crucial to ensure ZD quality. However, screening defects is only as good as the test and stress coverage enabled in the design. Design for ZD needs to be addressed at both IP level and SOC/SIP (system on chip/system in package) level. As the technology feature size keeps scaling down, the design complexity has increased exponentially. Driven by cost and time-to-market considerations, it has become more and more popular for automotive semiconductor suppliers to adopt the off-the-shelf 3rd party IPs on their SOC/SIPs. This, however, poses unique challenges on ZD testing and stressing due to the lack of automotive ZD stress/test requirements built in the 3rd party IPs as well as the lack of the detailed design knowledge of those IPs from the system integration point of view. Adding manufacturing test flow awareness to the DFT/stress guidelines followed by IP providers is not straightforward. Information about how transforming provided fault coverage achievements into actual test coverage is not part of the typical IP utilization guidelines. Consequently we have seen cases in which the 3rd -party IP were not tested or stressed sufficiently resulting in quality issues as well as cases in which the 3rd -party IPs were overstressed and caused qualification failures. Meanwhile, FuSa is usually considered at the system level, not at the IP level. Moreover, for different FuSa integrity levels, we may need different stress testing requirements. How to ensure the 3rd party IP designs meet FuSa requirements while achieving ZD quality in a systemic and holistic way has become a common but important challenge faced by the automotive semiconductor industry. It is important to clearly define the requirements for IP providers before the design starts and make sure they have the effectively access to all necessary inputs regarding to the ZD quality and FuSa objectives. In this panel, experts in this field will exchange their views and discuss possible solutions and remaining challenges on this important topic.

Organizer and Moderator: Chen He (NXP)

Panelists: Davide Appello (ST Microelectronics), Wim Dobbelaere (ON Semiconductor), Fei Su (Intel), Daniel Tille (Infineon), Jody Defazio (Synopsys), John Xu (Xscend Technology)