Program for Wednesday, October 13th: Talk View

PROGRAM FOR WEDNESDAY, OCTOBER 13TH: TALK VIEW

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8:00

8:30

9:00

9:30

10:00

10:30

11:00

11:30

12:00

12:30

13:00

13:30

14:00

14:30

15:00

15:30

08:00-09:00 Keynote2: Refusing Limits in Technology Innovation, Ron Nersesian (Chairman, Pres. & CEO, Keysight); Visionary Talk1: Machine Learning and Corpus Design for EDA and Beyond, Jyh-Shing Roger Jang (CTO, E. Sun Financial Holding Co./Professor, Dept. of Computer Science and Information Engineering, NTU)

09:30-10:30

Impeccable Circuits III

Shahram Rasoolzadeh, Aein Rezaei Shahmirzadi, Amir Moradi

09:30-10:30

A BIST-based Dynamic Obfuscation Scheme for Resilience against Removal and Oracle-guided Attacks

J. Talukdar, S. Chen, A. Das, S. Aftabjahani, P. Song, K. Chakrabarty

09:30-10:30

LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment

M.S. Rahman, H. Li, R. Guo, F. Rahman, F. Farahmandi, M. Tehranipoor

09:30-10:30

Triplet Convolutional Networks for Classifying Mixed-Type WBM Patterns with Noisy Labels

Chenwei Liu, Qiaoyue Tang

09:30-10:30

Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling

Chen, Li, Jiang, Wang, Huang, Chen, Liang, Hsu

09:30-10:30

MINiature Interactive Offset Networks (MINIONs) for Wafer Map Classification

Yueling Zeng, Li-C Wang, Chuanhe Shan

09:30-10:30

Revisions to IEEE Std 1500, Standard Testability Method for Embedded Core-based Integrated Circuits

Mike Ricchetti

09:30-10:30

IEEE P1687.1: The Trouble with Transforms

Michael Laisne

09:30-10:30

Assisting board level connectivity test with IEEE Std 1581

Heiko Ehrenberg

09:30-10:30

Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis (best paper award, ITC-India

Acharya, Naresh, Narayanan, Parekhji, Roush, Ibarra, Sheth, Flora, Pradeep

09:30-10:30

Addressing High Speed Memory Interface Test Quality Gaps in Shared Bus Architecture (1st honorable mention paper award, ITC-India

Wilson Pradeep, Rajesh Gottumukkala, Srinivas Vooka

09:30-10:30

A Novel Method to measure PLL Bandwidth in a 5G RF transceiver (2nd honorable mention paper award, ITC-India

Pradeep Nair, Dineej A

12:00-13:00

Characterizing Corruptibility of Logic Locks using ATPG

Danielle Duvalsaint, Shawn Blanton

12:00-13:00

SymbA: Symbolic Execution at C-level for Hardware Trojan Activation

Arash Vafaei, Nick Hooten, Mark Tehranipoor, Farimah Farahmandi

12:00-13:00

(Invited) Security and Provisioning of Automotive IC’s through Test and Safety

Lee Harrison

12:00-13:00

Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization

Mu-Ting Wu, Cheng-Sian Kuo, James Chien-Mo Li, Chris Nigh, Gaurav Bhargava

12:00-13:00

Relevant Signals and Devices for Failure Analysis of Analog and Mixed-signal Circuits

Tommaso Melis, Emmanuel Simeu, Luc Saury, Etienne Auvray

12:00-13:00

Open-short Normalization Method for a Quick Defect Identification in Branched Traces with High-resolution Time-domain

Yang Shang, Makoto Shinohara, Eiji Kato, Masaichi Hashimoto, Joanna Kiljan

12:00-13:00

On Reduction of Deterministic Test Pattern Sets

Jerzy Tyszer, Janusz Rajski, Sylwester Milewski, Stephan Eggersgluess

12:00-13:00

Multi-Transition Fault Model (MTFM) ATPG patterns towards achieving 0 DPPB on AUTOMOTIVE designs

Jorge Corso, Saidapet Ramesh, Kumar Abishek, Ley Teng Tan, Chik Hooi Lew

12:00-13:00

Analyzing and Mitigating Sensing Failures in Spintronic-based Computing in Memory

Mahta Mayahinia, Christopher Münch, Mehdi B. Tahoori

12:00-13:00

Memory BIST requirements

Raghav Mehta

12:00-13:00

Memory repair

Benoit Nadeau-Dostie

12:00-13:00

Built-in self-test functions to mitigate eMRAM test challenges

Jongsin Yun

14:00-15:00 Talk to the TTSC (Test Technology Standard Committee)

14:00-15:30

Understanding Tool Synthesis Behavior and Safe Finite State Machine Design

Tim McDonley, Katie Liszewski, Adam Kimura

14:00-15:30

Generalized Insider Attack Detection Implementation using NetFlow Data for Distributed Test Range

Yash Samtani, Jesse Elwell

14:00-15:30

FR4 could be better than Tachyon-100G for post-silicon validation on LVDS signaling

Pui Ling Lee

14:00-15:30

Defect-Directed Stress Testing Using I-PAT Inline Defect Inspection Results

He, Grosch, Anilturk, Witowski, Ford, Kalyan, Robinson, Price, Rathert, Saville

14:00-15:30

Layout Informed Multiple Bit Upset Hardening of Finite State Machines

Tim McDonley, Josh Delozier, Katie Liszewski, Adam Kimura

14:00-15:30

Power-Aware ATPG Using Sign-Off Models

Wenhao Hsueh, Smith Lai, Khader Abdel-Hafez, Adam Cron

14:00-15:30

In-Field Embedded Sensing & PVT Monitoring for Increased Device Power and Performance Optimization

Ramsay Allen

14:00-15:30

Jitter Injection with pre- and post- emphasis circuits

Tm Mak, Louis Ungar, Neil Jacobson

14:00-15:30

A Novel Fault Grading Technique to Establish RTL-ATPG Top-Off Coverage

F. Shukla, P. Mahajan, H. Eriksson, K. Adebo, E. Brazil, S. Pillai

14:00-15:30

Unified Test Flow for DFT Power, Performance & Area Optimization

Surya Duggirala, Rahul Singhal

14:00-15:30

A Multi-Threaded Single-Pass Diagnosis of Scan Chain Failures

Emil Gizdarski, Yasunari Kanzawa

14:00-15:30

High Bandwidth Current Sourcing with the Howland Current Source

Daniel Marsh

14:00-15:30

Practical Methods to Test MIPI C-Phy Data Interfaces

Timothy Lyons

14:00-15:30

Utilizing IEEE Std 1687 for board level test

Heiko Ehrenberg, Norbert Muench, Thomas Wenzel

09:00-09:30 Coffee Break (Social Time in Gather.Town)

10:30-11:00 Coffee Break (Social Time in Gather.Town)

11:00-12:00 Supporter/Exhibitor Presentations

13:00-14:00 Lunch Break (Social Time in Gather.Town)