ITC 2021: INTERNATIONAL TEST CONFERENCE

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A, Dineej	A Novel Method to measure PLL Bandwidth in a 5G RF transceiver (2nd honorable mention paper award, ITC-India 2021)
Abdel-Hafez, Khader	Power-Aware ATPG Using Sign-Off Models
Abishek, Kumar	Multi-Transition Fault Model (MTFM) ATPG patterns towards achieving 0 DPPB on AUTOMOTIVE designs
Acharya, Aravinda	Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis (best paper award, ITC-India 2021)
Adebo, King	A Novel Fault Grading Technique to Establish RTL-ATPG Top-Off Coverage
Aftabjahani, Sohrab	A BIST-based Dynamic Obfuscation Scheme for Resilience against Removal and Oracle-guided Attacks
Ahmed, Foisal	Study on High-Accuracy and Low-Cost Recycled FPGA Detection
Ahrens, Heiko	A Scalable Design Flow for Performance Monitors Using Functional Path Ring Oscillators
Allen, Ramsay	In-Field Embedded Sensing & PVT Monitoring for Increased Device Power and Performance Optimization
Amarnath, Chandramouli	Hierarchical Failure Modeling and Machine Learning Assisted Correction of Subsystem Failures in Autonomous Vehicles
Amrouch, Hussam	Machine Learning for Circuit Aging Estimation under Workload Dependency Brain-Inspired Computing for Wafer Map Defect Pattern Classification
Amrutur, Bharadwaj	Exploiting Application Tolerance for Functional Safety
Anilturk, Onder	Defect-Directed Stress Testing Using I-PAT Inline Defect Inspection Results
Augusto da Silva, Felipe	An automated formal-based approach for reducing Undetected faults in ISO26262 hardware compliant designs
Auvray, Etienne	Relevant Signals and Devices for Failure Analysis of Analog and Mixed-signal Circuits
Avci, Muslum Emir	Background Receiver IQ Imbalance Correction for in-Field and Post-Production Testing and Calibration
B
Bagbaba, Ahmet Cagri	An automated formal-based approach for reducing Undetected faults in ISO26262 hardware compliant designs
Bahar, Iris	Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits
Bartsch, Christian	Compositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation
Beadon, Matt	Silent Data Corruptions at Scale
Bhargava, Gaurav	AAA: Automated On-ATE AI Debug of Scan Chain Failures Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization
Billich, Enrico	Automatic Verification of Mixed-Signal ATE Test Programs using Device Variation
Blanton, R.D.	AAA: Automated On-ATE AI Debug of Scan Chain Failures Characterizing Corruptibility of Logic Locks using ATPG
Brazil, Edward	A Novel Fault Grading Technique to Establish RTL-ATPG Top-Off Coverage
Bruce, Isaac	Systematic Hardware Error Identification and Calibration for Massive Multisite Testing
C
Chaganti, Shravan	Systematic Hardware Error Identification and Calibration for Massive Multisite Testing
Chakrabarty, Krishnendu	Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin
Chakrabarty, Krishnendu	A BIST-based Dynamic Obfuscation Scheme for Resilience against Removal and Oracle-guided Attacks On-line Functional Testing of Memristor-mapped Deep Neural Networks using Backdoored Checksums Adaptive Methods for Machine Learning-Based Testing of Integrated Circuits and Boards
Chakravarthy, Tejasvi	Silent Data Corruptions at Scale
Chang, Yu-Teng	ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph
Chatterjee, Abhijit	Hierarchical Failure Modeling and Machine Learning Assisted Correction of Subsystem Failures in Autonomous Vehicles
Chaudhuri, Arjun	Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin
Chen, Cheng	Adaptive NN-based Root Cause Analysis in Volume Diagnosis for Yield Improvement
Chen, Ching-Yuan	On-line Functional Testing of Memristor-mapped Deep Neural Networks using Backdoored Checksums Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin
Chen, Chun	Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning
Chen, Degang	Systematic Hardware Error Identification and Calibration for Massive Multisite Testing
Chen, Harry	ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph
Chen, Jwu E	Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling
Chen, Leon Li-Yang	WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling
Chen, Siyuan	A BIST-based Dynamic Obfuscation Scheme for Resilience against Removal and Oracle-guided Attacks
Chen, Yongliang	The Security Enhancement Techniques of the Double-layer PUF Against the ANN-based Modeling Attack
Cheng, Ken Chau-Cheung	WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques
Chetia, Jugantor	Seamless Physical Implementation of ASIC Hierarchical Integrated Scan Architecture
Choi, Jaemoo	3.5Gsps MIPI C-PHY Receiver Circuit for Automatic Test Equipment
Chou, Leon	WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques
Colon-Benet, Glenn	A Software Solution for Managing Silicon Defects in Data Centers
Corso, Jorge	Multi-Transition Fault Model (MTFM) ATPG patterns towards achieving 0 DPPB on AUTOMOTIVE designs
Cron, Adam	Power-Aware ATPG Using Sign-Off Models
Crouch, Alfred	(Invited) IEEE P1687.1 Data Retargeting and Transfer Procedures for Accessing Internal Cores
Cui, Xiaole	The Security Enhancement Techniques of the Double-layer PUF Against the ANN-based Modeling Attack
Cui, Xiaoxin	The Security Enhancement Techniques of the Double-layer PUF Against the ANN-based Modeling Attack
Culler, David E.	Cores that don’t count
D
Daler, Georg	Automatic Verification of Mixed-Signal ATE Test Programs using Device Variation
Daley, Daniel L.	A Software Solution for Managing Silicon Defects in Data Centers
Das, Amitabh	A BIST-based Dynamic Obfuscation Scheme for Resilience against Removal and Oracle-guided Attacks
Debaud, Philippe	A Fast and Low Cost Embedded Test Solution for CMOS Image Sensors
Delozier, Josh	Layout Informed Multiple Bit Upset Hardening of Finite State Machines
Di Natale, Giorgio	Security EDA Extension through P1687.1 and 1687 Callbacks
Dickenscheid, Wolfgang	Automatic Verification of Mixed-Signal ATE Test Programs using Device Variation
Ding, Zhihao	Adaptive NN-based Root Cause Analysis in Volume Diagnosis for Yield Improvement
Dixit, Harish Dattatraya	Silent Data Corruptions at Scale
Dubey, Abhishek Kumar	Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin
Duggirala, Surya	Unified Test Flow for DFT Power, Performance & Area Optimization
Duvalsaint, Danielle	Characterizing Corruptibility of Logic Locks using ATPG
Dworak, Jennifer	Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits
E
Eggersgluess, Stephan	On Reduction of Deterministic Test Pattern Sets
Ehrenberg, Heiko	Assisting board level connectivity test with IEEE Std 1581 Utilizing IEEE Std 1687 for board level test
Eiki, Makoto	Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process
Elwell, Jesse	Generalized Insider Attack Detection Implementation using NetFlow Data for Distributed Test Range Networks
Eriksson, Henrik	A Novel Fault Grading Technique to Establish RTL-ATPG Top-Off Coverage
F
Fang, Eric Jia-Wei	Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning
Farahmandi, Farimah	LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment SymbA: Symbolic Execution at C-level for Hardware Trojan Activation
Farayola, Praise	Systematic Hardware Error Identification and Calibration for Massive Multisite Testing
Flora, Clarence	Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis (best paper award, ITC-India 2021)
Ford, Carl	Defect-Directed Stress Testing Using I-PAT Inline Defect Inspection Results
G
Genssler, Paul R.	Brain-Inspired Computing for Wafer Map Defect Pattern Classification
Girard, Patrick	A Fast and Low Cost Embedded Test Solution for CMOS Image Sensors
Gizdarski, Emil	A Multi-Threaded Single-Pass Diagnosis of Scan Chain Failures
Gnad, Dennis R. E.	Is your secure test infrastructure secure enough? Attacks based on delay test patterns using transient behavior analysis
Goel, Sandeep	Testing challenges and solutions for advanced packaging technologies - A foundry perspective
Gottumukkala, Rajesh	Addressing High Speed Memory Interface Test Quality Gaps in Shared Bus Architecture (1st honorable mention paper award, ITC-India 2021)
Govindaraju, Rama	Cores that don’t count
Grosch, Paul	Defect-Directed Stress Testing Using I-PAT Inline Defect Inspection Results
Guo, Rui	LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment
H
Hamdioui, Said	An automated formal-based approach for reducing Undetected faults in ISO26262 hardware compliant designs Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions Device-Aware Test for STT-MRAM
Harrison, Lee	(Invited) Security and Provisioning of Automotive IC’s through Test and Safety
Hashimoto, Masaichi	Open-short Normalization Method for a Quick Defect Identification in Branched Traces with High-resolution Time-domain Reflectometry
Hatayama, Kazumi	Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer
Hatta, Akemi	Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer
He, Chen	Adaptive High Voltage Stress Methodology to Enable Automotive Quality on FinFET Technologies Semi-supervised Wafer Map Pattern Recognition using Domain-Specific Data Augmentation and Contrastive Learning Defect-Directed Stress Testing Using I-PAT Inline Defect Inspection Results
He, Yi	Efficient Functional In-Field Self-Test for Deep Learning Accelerators
Heinkel, Ulrich	Automatic Verification of Mixed-Signal ATE Test Programs using Device Variation
Heo, Yun	Designing and testing 3D devices – A fabless company perspective
Hochschild, Peter H.	Cores that don’t count
Hooten, Nick	SymbA: Symbolic Execution at C-level for Hardware Trojan Activation
Hsieh, Chao-Ho	Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning
Hsu, Chun-Lun	Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling
Hsu, Ting-Shuo	ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph
Hsueh, Sung S.-Y.	Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning
Hsueh, Wenhao	Power-Aware ATPG Using Sign-Off Models
Hu, Hanbin	Semi-supervised Wafer Map Pattern Recognition using Domain-Specific Data Augmentation and Contrastive Learning
Huang, Andrew Yi-Ann	WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling
Huang, Jiun-Lang	Software-Based Self-Test for Transition Delay Faults in Pipelined Processors
Huang, Xin	Adaptive NN-based Root Cause Analysis in Volume Diagnosis for Yield Improvement
Huang, Yu	Adaptive NN-based Root Cause Analysis in Volume Diagnosis for Yield Improvement Testability-Aware Low Power Controller Design with Evolutionary Learning
Huch, Martin	A Scalable Design Flow for Performance Monitors Using Functional Path Ring Oscillators
I
Ibarra, Humberto	Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis (best paper award, ITC-India 2021)
Ichikawa, Tamotsu	Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer
Iimori, Daisuke	Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer
Inoue, Michiko	Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process Study on High-Accuracy and Low-Cost Recycled FPGA Detection
Ishida, Takashi	Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer
J
Jacobson, Neil	Jitter Injection with pre- and post- emphasis circuits
Jiang, Hui	Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits
Jorgensen, Bryan	A Software Solution for Managing Silicon Defects in Data Centers
Jui, Shangling	Adaptive NN-based Root Cause Analysis in Volume Diagnosis for Yield Improvement
K
Kajiyama, Masuo	Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process
Kalyan, Rahul	Defect-Directed Stress Testing Using I-PAT Inline Defect Inspection Results
Kang, Minho	3.5Gsps MIPI C-PHY Receiver Circuit for Automatic Test Equipment
Kanzawa, Yasunari	A Multi-Threaded Single-Pass Diagnosis of Scan Chain Failures
Katayama, Shogo	Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer
Kato, Eiji	Open-short Normalization Method for a Quick Defect Identification in Branched Traces with High-resolution Time-domain Reflectometry
Keim, Martin	(Invited) IEEE P1687.1 Data Retargeting and Transfer Procedures for Accessing Internal Cores
Kilian, Tobias	A Scalable Design Flow for Performance Monitors Using Functional Path Ring Oscillators
Kiljan, Joanna	Open-short Normalization Method for a Quick Defect Identification in Branched Traces with High-resolution Time-domain Reflectometry
Kimura, Adam	Understanding Tool Synthesis Behavior and Safe Finite State Machine Design Layout Informed Multiple Bit Upset Hardening of Finite State Machines
Klein, Ken	Adaptive High Voltage Stress Methodology to Enable Automotive Quality on FinFET Technologies
Klemme, Florian	Machine Learning for Circuit Aging Estimation under Workload Dependency
Kobayashi, Haruo	Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer
Krautter, Jonas	Is your secure test infrastructure secure enough? Attacks based on delay test patterns using transient behavior analysis
Kunz, Wolfgang	Compositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation
Kuo, Cheng-Sian	Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization
Kuo, Yen-Ting	Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning
Kuwana, Anna	Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer
Kästner, Daniel	Compositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation
L
Lai, Smith	Power-Aware ATPG Using Sign-Off Models
Laisne, Michael	IEEE P1687.1: The Trouble with Transforms (Invited) IEEE P1687.1 Data Retargeting and Transfer Procedures for Accessing Internal Cores
Larsson, Erik	Accessing general IEEE Std. 1687 networks via functional ports
Lee, Pui Ling	FR4 could be better than Tachyon-100G for post-silicon validation on LVDS signaling
Lee, Seongkwan	3.5Gsps MIPI C-PHY Receiver Circuit for Automatic Test Equipment
Lefevre, Julia	A Fast and Low Cost Embedded Test Solution for CMOS Image Sensors
Leveugle, Regis	Security EDA Extension through P1687.1 and 1687 Callbacks
Lew, Chik Hooi	Multi-Transition Fault Model (MTFM) ATPG patterns towards achieving 0 DPPB on AUTOMOTIVE designs
Li, Henian	LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment
Li, James Chien-Mo	Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization
Li, Katherine Shu-Min	WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling
Li, Min	Testability-Aware Low Power Controller Design with Evolutionary Learning
Li, Peng	Semi-supervised Wafer Map Pattern Recognition using Domain-Specific Data Augmentation and Contrastive Learning
Li, Pengyun	Adaptive NN-based Root Cause Analysis in Volume Diagnosis for Yield Improvement
Li, Yanjing	Efficient Functional In-Field Self-Test for Deep Learning Accelerators
Liang, Hsing-Chung	Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling
Liao, Peter Yi-Yu	WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling
Lin, Wei-Chen	Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning
Liou, Jing-Jia	ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph
Liszewski, Katie	Understanding Tool Synthesis Behavior and Safe Finite State Machine Design Layout Informed Multiple Bit Upset Hardening of Finite State Machines
Liu, Chenwei	Triplet Convolutional Networks for Classifying Mixed-Type WBM Patterns with Noisy Labels Smart Sampling for Efficient System Level Test: A Robust Machine Learning Approach
Liu, Mengyun	Adaptive Methods for Machine Learning-Based Testing of Integrated Circuits and Boards
Lylina, Natalia	Testability-Enhancing Resynthesis of Reconfigurable Scan Networks
Lyons, Timothy	Practical Methods to Test MIPI C-Phy Data Interfaces
M
Madala, Siddarth	Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin
Mahajan, Pawini	A Novel Fault Grading Technique to Establish RTL-ATPG Top-Off Coverage
Maistri, Paolo	Security EDA Extension through P1687.1 and 1687 Callbacks
Mak, Tm	Jitter Injection with pre- and post- emphasis circuits
Manikas, Theodore	Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits
Marsh, Daniel	High Bandwidth Current Sourcing with the Howland Current Source
Mason, Chris	Silent Data Corruptions at Scale
Mayahinia, Mahta	Analyzing and Mitigating Sensing Failures in Spintronic-based Computing in Memory
Mayer, Franziska	Automatic Verification of Mixed-Signal ATE Test Programs using Device Variation
McDonley, Tim	Understanding Tool Synthesis Behavior and Safe Finite State Machine Design Layout Informed Multiple Bit Upset Hardening of Finite State Machines
Mehta, Raghav	Memory BIST requirements
Melis, Tommaso	Relevant Signals and Devices for Failure Analysis of Analog and Mixed-signal Circuits
Meschkov, Sergej	Is your secure test infrastructure secure enough? Attacks based on delay test patterns using transient behavior analysis
Mian, Riaz-Ul-Haque	Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process
Milewski, Sylwester	On Reduction of Deterministic Test Pattern Sets
Mogul, Jeffrey C.	Cores that don’t count
Momtaz, Md	Hierarchical Failure Modeling and Machine Learning Assisted Correction of Subsystem Failures in Autonomous Vehicles
Moradi, Amir	Impeccable Circuits III
Muench, Norbert	Utilizing IEEE Std 1687 for board level test
Murali, Prathamesh	Accessing general IEEE Std. 1687 networks via functional ports
Muthiah, Bharath	Silent Data Corruptions at Scale
Münch, Christopher	Analyzing and Mitigating Sensing Failures in Spintronic-based Computing in Memory
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Nadeau-Dostie, Benoit	Memory repair
Nair, Pradeep	A Novel Method to measure PLL Bandwidth in a 5G RF transceiver (2nd honorable mention paper award, ITC-India 2021)
Nakamura, Tomoki	Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process
Nakatani, Takayuki	Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer
Narayanan, Prakash	Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis (best paper award, ITC-India 2021)
Naresh, Nikita	Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis (best paper award, ITC-India 2021)
Nepal, Kundan	Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits
Nigh, Chris	AAA: Automated On-ATE AI Debug of Scan Chain Failures Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization
O
Obaidi, Abdullah	Systematic Hardware Error Identification and Calibration for Massive Multisite Testing
Ogihara, Gaku	Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer
Okamoto, Toshiyuki	Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer
Ou, Jie	Smart Sampling for Efficient System Level Test: A Robust Machine Learning Approach
Ozev, Sule	Background Receiver IQ Imbalance Correction for in-Field and Post-Production Testing and Calibration
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Pannuzzo, Ricardo	Automatic Verification of Mixed-Signal ATE Test Programs using Device Variation
Parekhji, Rubin	Exploiting Application Tolerance for Functional Safety
Parekhji, Rubin	Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis (best paper award, ITC-India 2021)
Park, Cheolmin	3.5Gsps MIPI C-PHY Receiver Circuit for Automatic Test Equipment
Pendharkar, Sneha	Silent Data Corruptions at Scale
Pillai, Shruthi	A Novel Fault Grading Technique to Establish RTL-ATPG Top-Off Coverage
Portolan, Michele	Security EDA Extension through P1687.1 and 1687 Callbacks (Invited) IEEE P1687.1 Data Retargeting and Transfer Procedures for Accessing Internal Cores
Pradeep, Wilson	Addressing High Speed Memory Interface Test Quality Gaps in Shared Bus Architecture (1st honorable mention paper award, ITC-India 2021)
Pradeep, Wilson	Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis (best paper award, ITC-India 2021)
Price, David	Defect-Directed Stress Testing Using I-PAT Inline Defect Inspection Results
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Qin, Min	Adaptive NN-based Root Cause Analysis in Volume Diagnosis for Yield Improvement
R
Rahman, Fahim	LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment
Rahman, M Sazadur	LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment
Rajski, Janusz	On Reduction of Deterministic Test Pattern Sets
Ramakrishnan, Lakshmi	Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits
Ramesh, Saidapet	Multi-Transition Fault Model (MTFM) ATPG patterns towards achieving 0 DPPB on AUTOMOTIVE designs
Ranganathan, Parthasarathy	Cores that don’t count
Rao, Siddharth	STT-MRAM technology for embedded applications
Rasoolzadeh, Shahram	Impeccable Circuits III
Rathert, Jay	Defect-Directed Stress Testing Using I-PAT Inline Defect Inspection Results
Ravi, Srivaths	Systematic Hardware Error Identification and Calibration for Massive Multisite Testing
Rearick, Jeff	Moderator: Intro and framing of the session (Invited) IEEE P1687.1 Data Retargeting and Transfer Procedures for Accessing Internal Cores
Reynaud, Vincent	Security EDA Extension through P1687.1 and 1687 Callbacks
Rezaei Shahmirzadi, Aein	Impeccable Circuits III
Ricchetti, Mike	Revisions to IEEE Std 1500, Standard Testability Method for Embedded Core-based Integrated Circuits
Robinson, John	Defect-Directed Stress Testing Using I-PAT Inline Defect Inspection Results
Roush, Kevin	Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis (best paper award, ITC-India 2021)
Ruf, Bernhard	Automatic Verification of Mixed-Signal ATE Test Programs using Device Variation
Ryu, Hyungsun	3.5Gsps MIPI C-PHY Receiver Circuit for Automatic Test Equipment
S
Samtani, Yash	Generalized Insider Attack Detection Implementation using NetFlow Data for Distributed Test Range Networks
Sankar, Sririam	Silent Data Corruptions at Scale
Sato, Keno	Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer
Sauer, Christian	An automated formal-based approach for reducing Undetected faults in ISO26262 hardware compliant designs
Saury, Luc	Relevant Signals and Devices for Failure Analysis of Analog and Mixed-signal Circuits
Saville, Barry	Defect-Directed Stress Testing Using I-PAT Inline Defect Inspection Results
Schlichtmann, Ulf	A Scalable Design Flow for Performance Monitors Using Functional Path Ring Oscillators
Schott, Christian	Automatic Verification of Mixed-Signal ATE Test Programs using Device Variation
Shah, Ankit R	Seamless Physical Implementation of ASIC Hierarchical Integrated Scan Architecture
Shan, Chuanhe	MINiature Interactive Offset Networks (MINIONs) for Wafer Map Classification
Shang, Yang	Open-short Normalization Method for a Quick Defect Identification in Branched Traces with High-resolution Time-domain Reflectometry
Sheikh, Abalhassan	Systematic Hardware Error Identification and Calibration for Massive Multisite Testing
Sheth, Rajiv	Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis (best paper award, ITC-India 2021)
Shi, Zhengyuan	Testability-Aware Low Power Controller Design with Evolutionary Learning
Shinohara, Makoto	Open-short Normalization Method for a Quick Defect Identification in Branched Traces with High-resolution Time-domain Reflectometry
Shintani, Michihiro	Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process Study on High-Accuracy and Low-Cost Recycled FPGA Detection
Shukla, Fenil	A Novel Fault Grading Technique to Establish RTL-ATPG Top-Off Coverage
Simeu, Emmanuel	Relevant Signals and Devices for Failure Analysis of Analog and Mixed-signal Circuits
Singhal, Rahul	Unified Test Flow for DFT Power, Performance & Area Optimization
Song, Peilin	A BIST-based Dynamic Obfuscation Scheme for Resilience against Removal and Oracle-guided Attacks
Stoffel, Dominik	Compositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation
Sun, Yi	Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits
Suparjo, Bambang	Seamless Physical Implementation of ASIC Hierarchical Integrated Scan Architecture
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Tahoori, Mehdi B.	Is your secure test infrastructure secure enough? Attacks based on delay test patterns using transient behavior analysis Design of Reliable Sensing Mechanisms in STT-MRAM Analyzing and Mitigating Sensing Failures in Spintronic-based Computing in Memory
Talukdar, Jonti	A BIST-based Dynamic Obfuscation Scheme for Resilience against Removal and Oracle-guided Attacks Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin
Tan, Ley Teng	Multi-Transition Fault Model (MTFM) ATPG patterns towards achieving 0 DPPB on AUTOMOTIVE designs
Tang, Qiaoyue	Triplet Convolutional Networks for Classifying Mixed-Type WBM Patterns with Noisy Labels
Taouil, Mottaqiallah	Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions
Tehranipoor, Mark	LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment SymbA: Symbolic Execution at C-level for Hardware Trojan Activation
Tille, Daniel	A Scalable Design Flow for Performance Monitors Using Functional Path Ring Oscillators
Tran, Tri	Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer
Traynor, Stephen	Adaptive High Voltage Stress Methodology to Enable Automotive Quality on FinFET Technologies
Tsai, Cheng-Yen	WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques
Turner, Paul	Cores that don’t count
Tyszer, Jerzy	On Reduction of Deterministic Test Pattern Sets
U
Uezono, Takumi	Efficient Functional In-Field Self-Test for Deep Learning Accelerators
Ungar, Louis	Jitter Injection with pre- and post- emphasis circuits
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Vafaei, Arash	SymbA: Symbolic Execution at C-level for Hardware Trojan Activation
Vahdat, Amin	Cores that don’t count
Van Treuren, Bradford	(Invited) IEEE P1687.1 Data Retargeting and Transfer Procedures for Accessing Internal Cores
Virazel, Arnaud	A Fast and Low Cost Embedded Test Solution for CMOS Image Sensors
Viswanathan Pillai, Prasanth	Exploiting Application Tolerance for Functional Safety
von Staudt, Hans Martin	(Invited) IEEE P1687.1 Data Retargeting and Transfer Procedures for Accessing Internal Cores
Vooka, Srinivas	Addressing High Speed Memory Interface Test Quality Gaps in Shared Bus Architecture (1st honorable mention paper award, ITC-India 2021)
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Wang, Chih-Hao	Testability-Enhancing Resynthesis of Reconfigurable Scan Networks
Wang, Li-C	MINiature Interactive Offset Networks (MINIONs) for Wafer Map Classification
Wang, Sying-Jyan	WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling
Wang, Zezhong	Testability-Aware Low Power Controller Design with Evolutionary Learning
Wei, Jiang-Lin	Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies
Wei, Jianglin	Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer
Wenzel, Thomas	Utilizing IEEE Std 1687 for board level test
Wilhelm, Stephan	Compositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation
Witowski, Joyce	Defect-Directed Stress Testing Using I-PAT Inline Defect Inspection Results
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