ABSTRACT. This paper presents a novel Built-In Self-Test (BIST) solution for CMOS Image Sensors (CIS) used to sort out PASS and FAIL dies during production test. By using simplified image processing algorithms, the proposed solution executes a wide range of optical tests usually applied with an ATE without the drawbacks of long test time and huge amount of test data storage. Results obtained on more than 2,400 sensors have shown that our solution reduces test time by about 30% without impacting the defect coverage. The area cost of our solution is about 0.25% of the total sensor area.

ABSTRACT. In this paper, we proposed a novel method (ACE-Pro) to reduce the functional fault list. The method extends Architecturally Correct Execution (ACE) analysis by creating a propagation graph, where a node is a fault marked with a ACE bit at a cycle and a directed link between nodes represents the propagation condition to another register at next cycle. By checking and propagating the property of masking or single-fault equivalence through above graph, we could reduce faults by as much as 99% in our experiments on a RISC-V core.

ABSTRACT. Testing the control logic of Reconfigurable Scan Networks (RSNs) is a complex sequential test problem. This paper proposes a design-for-test method which simplifies the offline and online RSN test with negligible hardware costs. Algorithms are presented which analyze the testability of an RSN and modify its structure such that each single fault at the control lines is detectable by standard test methods. The approach complements state-of-the-art RSN test methods and is compliant with all the applicable standards.

ABSTRACT. Circuit analysis with respect to aging-induced degradation is critical to ensure correct operation throughout the lifetime of a chip. However, state-of-the-art techniques only allow for the consideration of uniformly applied degradation, despite the fact that different workloads will lead to different degradations. This imposes over-pessimism and unnecessary losses of performance and efficiency. We propose an approach that takes workload dependencies into account and generates workload-specific aging-aware standard cell libraries. This enables accurate analysis of circuits under the actual effect of aging-induced degradation. We use machine learning techniques to overcome infeasible simulation times for individual transistor aging while sustaining high accuracy.

ABSTRACT. Root Cause Analysis (RCA) is a critical technology for yield improvement in integrated circuit. Traditional RCA prefers unsupervised algorithms such as Expectation Maximization. However, these methods are limited by the statistical models and can't effectively transfer the diagnosis experience to the new designs. In this paper we propose a Neural-Network-based adaptive framework for RCA in yield improvement. The proposed framework consists of an inference module and a self-adaptive module. Experiments show that a relatively large improvement on accuracy is achieved by the proposed framework on simulated diagnosis data. Furthermore, the transferring capability is also validated by the results.

ABSTRACT. We propose a new methodology to predict minimum operating voltage (Vmin) for production chips. In addition, we propose two new key features to improve the prediction accuracy. Our proposed accumulative learning can reduce the impact of lot-to-lot variations. Experimental results on two 7nm industry designs (about 1.2M chips from 142 lots) show that we can achieve above 95% good prediction. Our methodology can save 75% test time compared with traditional testing. To implement this method, we will need to have separate test flow for the initial training and accumulative training.

ABSTRACT. Without a doubt, 2.5D and 3D device design, test, and manufacturing is more than the current “hot topics of the year.” As opposed to the interest in 3D devices from a couple of years ago, all parts of the semiconductor industry are now moving forward with it. Today, we face an industry-wide inflection point as higher cost and lower yield, as well as a myriad of technology challenges drive the need for alternatives to monolithic solutions. 3D devices are the promising answer. With the help of standards, like IEEE 1687, IEEE 1838, and the currently completing second edition of IEEE 1500, the industry could consider the test challenges of 3D devices solved. The reality is far from it. While these standards certainly play an important role in any DFT solution for 3D devices (and to an extend to 2.5D devices or any combination thereof), there are wide gaps to be filled. These gaps prevent a coherent picture how to fully test such devices at each integration level. It became apparent at past conferences and workshops, that today only partial solutions exist, looking at one or the other slice of the DFT puzzle. Many details are not yet fully understood and to a certain degree, confusion reigns in our industry. To address this, the proposed special session, with its representative cross-section of our industry, focuses on drawing a complete and coherent picture of Design-for-Test for 3D devices

ABSTRACT. System level tests (SLTs) are important and expensive procedures to ensure high quality of IC products. In the volume production stage with stable yield, efforts such as random sampling have been made to improve testing efficiency. However random sampling doesn’t fully utilize information gathered before SLT and is not optimal. In this paper we propose both supervised (SVM) and unsupervised (AutoEncoder ) machine learning algorithms to predict or estimate the SLT failure based on earlier stage Final Test (FT) data and use the estimated pseudo probabilities to guide the selection of some chips for system level test. Experiments on a real product dataset, consisting of 158 wafers from 8 lots, each with 3118 FT testing variables reveal robustness of the models to data shift such as lot variations and missing test items. Through the gains chart of the models, we provide a flexible smart sampling strategy and demonstrate its potential of reducing SLT testing cost by 40% with minor impact on Defective Parts Per Million (DPPM). Our cases also show that such robust machine learning based sampling approach is very well suited for engaging adaptive test flow optimization to achieve balanced goals of improving test efficiency, reducing cost and ensuring high product quality at the same time.

ABSTRACT. The physical unclonable function (PUF) against the modeling attack is of great concern in recent years, since the modeling attack has been proved to be a serious security threat to the PUF circuits. The double-layer PUF was reported as a PUF scheme to resist the fully connected artificial neural network based modeling attack, and its test chip was fabricated and tested. This work proposes an artificial neural network (ANN) based modeling method according to the working principle of the target PUF, and successfully attacks the double-layer PUF. To enhance the anti-modeling-attack capability of the double-layer PUF, the address swapping, the XORing, and the dimensional extension techniques are proposed. The attack results show that the prediction accuracy of the proposed ANN-based model with the proposed techniques drops obviously. And the prediction accuracy is about 50.04% if all the three proposed techniques are applied in combination. It manifests that the proposed security enhancement techniques are able to improve the resilience of the double-layer PUF against the modeling attacks effectively. Both the randomness and uniqueness of the improved doublelayer PUFs are approximate to the ideal value (50%), and the reliability of the improved PUFs remain unchanged compared with the original counterpart because the operations on the resistive random memory (RRAM) array are the same.

ABSTRACT. For processor cores, software-based self-test (SBST) is a promising complement to scan-based testing, especially for applications that demand high in-field reliability. However, most prior SBST techniques only target stuck-at faults and thus fall short in detecting aging induced timing violations. In this paper, we propose an automatic test program generator for detection of transition delay faults (TDFs) in pipelined processors. The key technique is the conversion of scan-based launch-on-capture (LoC) TDF test patterns to instruction sequences, which are combined to form the self-test program. In the field, the processor under test can execute the test program on demand, in its functional mode, to detect TDFs. To facilitate the pattern-to-instruction conversion, a test program template is developed. Derived from the pipelined operation principle, the template helps systematically and efficiently set the flip-flop values as specified in LoC test patterns. The proposed technique is validated on a MIPS32 processor and achieves 97.82% TDF coverage.

ABSTRACT. We present a backdooring technique that fine-tunes deep neural network (DNN) weights to implement a checksum function for on-line functional testing. The DNN is next mapped to memristor crossbars, and the backdoored checksum indicates if model weights are deviated by faults. The implemented checksum functions for DNNs remarkably outperform baseline approaches. Based on the proposed functional testing solution, we present an on-line computing framework that can efficiently recover the inferencing accuracy of a memristor-mapped DNN from weight deviations. Compared to related recent work, the proposed framework achieves 5.6× speed-up in time-to-recovery and reduces the on-chip test data volume by 99.99%.

ABSTRACT. Supervised-learning techniques for fault-criticality assessment require ground-truth collection involving extensive fault simulations. We present a framework for criticality analysis using a negligible amount of ground-truth data. We incorporate the structural and functional information of the processing elements (PEs) in a systolic array in their ``neural twins'', called ``PE-Nets'', to alleviate the need for strong supervision. We utilize misclassification-driven training to identify biases in PE-Net that are critical to the accelerator’s functionality. Our framework achieves up to 100% accuracy in fault-criticality classification in 16-bit and 32-bit PEs by using the criticality knowledge of only 2% of all faults in a PE.

ABSTRACT. We present a novel technique to generates high-quality functional test programs, which can be applied during in-field self-test of deep learning accelerators for a wide range of applications (including safety-critical automotive applications). Our technique takes advantage of special architectural characteristics and workload requirements to achieve high functional test coverage which incurring minimal in-field self-test time. We demonstrate the efficacy of our technique using Nvidia's open-source accelerator, which shows that our technique achieves >=99.8% single stuck-at test coverage for compute units, 100% test coverage for any single fault in control units, and <= 7.5ms in-field self-test time.

ABSTRACT. In this paper, we propose a wafer-level performance prediction method for multi-site testing, which can take into account the site-to-site variation. The proposed method applies the Gaussian process hierarchically by utilizing the site information of the multi-site test provided by the test engineer, and models in consideration of the variation between sites. In addition, we propose an active test site sampling method to maximize the measurement cost reduction. Through experiments using industrial production test data, we demonstrate that the proposed method can reduce the estimation error to 1/19 compared to that using a conventional method.

ABSTRACT. Brain-Inspired hyperdimensional computing is an alternative machine-learning concept. Hypervectors with thousands of dimensions make the system robust against noisy input data, similar to the human brain. The light-weight operations with hypervectors are fully parallelizable enabling fast learning and inference at the edge. A classifier can be created through one-shot learning from few examples. This is particularly valuable if training samples are expensive, like in the area of semiconductor testing. In this work, we explore the applicability of brain-inspired hyperdimensional computing to the field of semiconductor testing for the first time with the example of wafer map defect pattern classification.

ABSTRACT. Wafer map pattern recognition is instrumental for detecting systemic manufacturing process issues. However, due to the high labor cost for labeling, not all data are utilized to train the wafer map pattern recognizer. We proposed a semi-supervised learning framework, where contrastive learning is applied for good representation learning in an unsupervised manner via comparing different transforms of wafer maps. We identified a set of domain-specific transforms and proposed a novel twist transform through a smooth rotation at different radius to extract pattern similarity. Experimental results demonstrate that the proposed semi-supervised framework greatly improves recognition accuracy compared to the supervised methods.

ABSTRACT. STT-MRAM has long been a promising non-volatile memory solution for the embedded application space owing to its attractive characteristics such as non-volatility, low leakage, high endurance, and scalability. However, the operating requirements for high-performance computing (HPC) and low power (LP) applications involve different challenges. In this talk, we will review the fundamentals and operating principles of an STT-MRAM device. This will be followed by an understanding of the manufacturing process flow of embedded STT-MRAMs, with a specific focus on the under-lying challenges towards market adoption. Overcoming these challenges are critical to minimizing defects and maximizing yield, and we will review the current state-of-the-art within the framework of these challenges. We will also briefly cover modelling efforts to better understand and minimize process-induced damage in STT-MRAM. Finally, we demonstrate state-of-the-art arraylevel performance on BEOL-compatible (backend-of-line) devices with switching energies < 1 pJ at 100 MHz, 1ppm error-free switching and endurance exceeding 1010 cycles with no device degradation and data retention over 10 years.

ABSTRACT. STT-MRAM is one of the front-runners for industry adaptation of emerging resistive nonvolatile memory technologies. However, due to the small ratio of on and off resistances in this technology, it is extremely sensitive to read errors. Therefore, it is very challenging to devise a reliable reading mechanism for large STT-MRAM arrays that can work property under several conditions. This talk focuses on reliable read operations in STT-MRAM and how the process and runtime variations can impact the correct read operation. We will investigate how these variations impacts the sensed cells as well as the sensing paths and circuitry under different sources of variations. Then, the efficiency of various sensing schemes are analyzed from reliability as well as performance, area and power consumption.

ABSTRACT. This talk will discuss the practicality of STT-MRAM testing and introduces Device-Aware Test (DAT) and demonstrates it based on industrial STT-MRAM design. DAT is a new test approach that goes beyond Cell-Aware Test. DAT does not assume that a defect in a device (or a cell) can be modeled electrically as a linear resistor (as the state-of-the art approach suggests), but it rather incorporates the impact of the physical defect in the technology parameters of the device and thereafter in its electrical parameters. Once the defective electrical model is defined, a systematic fault analysis is performed to derive appropriate fault models and subsequently test solutions. For the considered memory, the industrial results show that DAT sensitizes realistic faults as well as new unique defects and faults that can never be caught with the traditional approach. In addition, the results will show how powerful is DAT for fast diagnosis and yield learning.

ABSTRACT. We resent a novel method for the detection of recycled FPGAs, where delay information of all paths LUTs in the FPGAs is analyzed exhaustively through an advanced ring oscillator (RO) design. Although the proposed X-FP characterization technique can accurately capture the aging degradation of each path in the FPGA, it considerably increases RO measurement cost. Furthermore, X-FP yields a large amount of measurement data To combat these challenges, we additionally propose two techniques: compressed sensing (CS) based prediction and with-in die (WID) modeling based feature engineering. In CS-based estimation, we incorporate the virtual probe (VP) technique for low-cost RO measurement.

ABSTRACT. This paper focuses on testing of STT-MRAM testing, covering manufacturing defects, fault models, and test solutions. We first survey STT-MRAM manufacturing defect space and apply the conventional test approach. We then demonstrate with silicon measurements and circuit simulations that it fails to appropriately model and test the device. Therefore, we propose a new approach: Device-Aware Test to target device-internal defects. We apply DAT to three key types of MTJ defects: pinhole, synthetic anti-ferromagnet flip, and intermediate state defects. Some STT-MRAM unique faults are identified, both permanent and intermittent. Based on the obtained fault models, high-quality test solutions are proposed.

ABSTRACT. In this paper, we describe efficient solutions for adapting machine-learning techniques to testing and diagnosis. To reduce manufacturing cost, we select different test items for chips with different predicted quality levels. To avoid the periodic interruption of computing tasks in accelerators for AI, we describe an efficient online testing method that interrupts the regular computation only when a high defect rate is estimated. To identify board-level functional faults with high accuracy, we utilize online incremental learning and transfer learning to address the practical issues that arise when we deal with real-life test data in a high-volume production environment.