ITC 2021: INTERNATIONAL TEST CONFERENCE
TALK KEYWORD INDEX

This page contains an index consisting of author-provided keywords.

1
1. shift verification left
2
2. Functional fault-simulation
2.5D
3
3. test coverage
3D
3DIC
4
4. test coverage correlation between post-RTL and post-ATPG
A
adaptive stress
ADC testing
address swapping
aging
AI accelerator
algorithm
analog and mixed-signal circuit
Analog to Digital Converter
ANN attack
Application-based protection
Architecturally Correct Execution
area
artificial intelligence
ATE
ATPG
Authentication
AutoEncoder
Automated Test Environments
Automatic Test Equipment
automatic test pattern generation
automatic testing
automotive
Autonomous Vehicles
B
Backdoored checksum
BIST
board level connectivity
Board Test
C
C-Phy
C-PHY Receiver
Calibration
Callbacks
cell aware test
Cell-Net
chain diagnosis
Charge pump
Chip Performance Prediction
CIS
CMOS image sensor
Computing-in-Memory
Concurrent Error Correction
Concurrent Error Detection
congestion
contrastive learning
cores
Corruptibility
count
Cross-Layer Safety Analysis
CTLE
Current Source
custom ASIC
D
data center
data centers
decision tree
deep learning accelerators
Deep neural network
Defect
defect dependent reflection (DDR)
defect identification
defect independent reflection (DIR)
defect pattern
Defect pattern classification
Delay Testing
design convergence
Design for testability
Design-for-Test
Deviation tolerance
Device Variation
device-aware
DFT
diagnosis resolution
DIB Hardware Solution
Digital circuit testing
Digital to Analog Converter
dimensional extension
Direct conversion receiver
Domain-Specific Languages
DPPM
Dynamic Obfuscation
E
EDA
embedded
Embedded Core
embedded core testing
embedded cores
embedded instruments
Embedding learning
Equalizer
ETS-800
Evolutionary Learning
expert system
F
fabless
Failure Analysis
Failure Correction
False Summing Node Method
Fast Fourier Transform (FFT)
Fault Analysis Countermeasure
Fault Injection
fault modeling
Fault Models
Fault Reduction
Fault Sensitivity Analysis
faulty CPUs
Feature extraction
FFT
FinFET
Fingerprinting
Finite State Machine
flat-top window
Formal Fault Propagation Analysis
Formal Methods
Foundry
FPGA
FR4
functional criticality
Functional Fault
functional path
functional port as test interface
Functional Safety
functional self test
Functional testing
G
Gaussian process
generic IEEE P1687.1 transformations
Genetic Algorithm
H
Hardware Security
Hardware Systematic Errors
Hardware Trojans
Harmonic Distortion
hierarchical integrated scan
Hierarchical Systems
High Bandwidth
high coverage
High Reliability
High-Reliability
high-resolution TDR
Howland Current Source
HVST
HW/SW Systems
I
IC Test
IEEE 1500
IEEE 1687
IEEE 1838
IEEE Std 1500
IEEE Std 1581
IEEE Std. 1149.1
IEEE Std. 1687
IEEE Std. P1687.1
IJTAG
In-Field
incoherent sampling
Inline
Insider Attack Detection
Integrated Circuits and Boards
IOT
IP Security
IQ correction
IQ imbalance
ir-drop
ISO26262
J
jitter generation
jitter injection
L
Layout
LED Driver
Logic Locking
Logic Testing
low DPPM
Low Power Controller
Low Power Test
LVDS
M
Machine Learning
Manufacturing
Manufacturing Defects
Manufacturing test
Memory
memory interface test
memory repair
memory yield
Memristor crossbar
Minions
MIPI
misclassification-driven training
Monitoring
MRAM
Multi-Pattern Wafer Map
Multi-site test
Multiple Bit Upset
multiple transition
Multisite Testing
Mutation Testing
N
necessary assignments
neural twin
NeuralNetwork
non-TAP interface
O
On-Chip Decompressor
On-line testing
One-shot learning
open-short normalization (OSN)
Operational Amplifier
optical test
P
Packaging
path delay
pattern optimization
PCB material
PE-Net
performance
performance screening
periodic maintenance
Phase Locked loop (PLL)
physical design
physical implementation
physical layer
physical synthesis
pixel array
power
power-aware
PPA
process and runtime variation
Process variation
production test
PUF
R
Radio Frequency (RF)
RAM sequential ATPG
Read Decision Failure
Reconfigurable Scan Networks
Recycling Detection
relevant devices
relevant signals
Reliability
reliable sensing mechanisms
repair sharing
ReRAM
RF receiver
ring oscillator
robustness
RootCauseAnalysis
RoT (Root of Trust)
routing
S
Safe Faults
scan chain failure
scan compression
scan-based designs
Secure Access
security
Security Metrics
Self-AdaptiveLearning
semi-supervised learning
Semiconductor testing
SerDes
serial interface
Shared bus interface
Silent data corruption
silicon
Simulation
SINAD
Single Event Upset
Site to Site Variations
SLT
small delay defects
Smart Sampling
Soft error mitigation
Soft Errors
Soft-Errors
software-based self-test
Spintronic
Standards
static test compaction
Statistical Ineffective Fault Attack (SIFA)
Stress
structural faults
STT-MRAM
Stuck At
Summing Node Method
SVM
Symbolic execution
Synthesis
systematic defect
T
Tachyon-100G
Template Attack
Test
Test Compression
test debug
Test Infrastructure Security
test program generation
Test Program Verification
Test Range networks
Test Standards
Test Technology
Test Volume Data
Testability
Tester
Testing
threaded diagnosis
timing constraints
trace with branches
Transfer learning
transformation algorithm
Transient Fault
transistor aging
Transition
transition delay fault
Trim search
Triplet CNN
tunability
U
udfm
unsupervised machine learning
Untrusted foundry
V
validation
variability
Verification
Voltage controlled Oscillator (VCO)
volume diagnosis
W
wafer map
Wafer map classification
wafer map pattern recognition
Wafer-level Variation Modeling
Weakly Supervised Learning
Weight deviation
Wrapper
X
XORing
Y
yield learning
YieldImprovement
Z
zero defect
Zero IF Receiver