ITC 2021: INTERNATIONAL TEST CONFERENCE

This page contains an index consisting of author-provided keywords.

1
1. shift verification left	A Novel Fault Grading Technique to Establish RTL-ATPG Top-Off Coverage
2
2. Functional fault-simulation	A Novel Fault Grading Technique to Establish RTL-ATPG Top-Off Coverage
2.5D	3DIC Test Challenges, Trends and Solutions - an EDA perspective Moderator: Intro and framing of the session
3
3. test coverage	A Novel Fault Grading Technique to Establish RTL-ATPG Top-Off Coverage
3D
3DIC	3DIC Test Challenges, Trends and Solutions - an EDA perspective Designing and testing 3D devices – A fabless company perspective Testing challenges and solutions for advanced packaging technologies - A foundry perspective Moderator: Intro and framing of the session
4
4. test coverage correlation between post-RTL and post-ATPG	A Novel Fault Grading Technique to Establish RTL-ATPG Top-Off Coverage
A
adaptive stress	Adaptive High Voltage Stress Methodology to Enable Automotive Quality on FinFET Technologies
ADC testing	Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies
address swapping	The Security Enhancement Techniques of the Double-layer PUF Against the ANN-based Modeling Attack
aging	Software-Based Self-Test for Transition Delay Faults in Pipelined Processors
AI accelerator	Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin
algorithm	Memory BIST requirements
analog and mixed-signal circuit	Relevant Signals and Devices for Failure Analysis of Analog and Mixed-signal Circuits
Analog to Digital Converter	A Novel Method to measure PLL Bandwidth in a 5G RF transceiver (2nd honorable mention paper award, ITC-India 2021)
ANN attack	The Security Enhancement Techniques of the Double-layer PUF Against the ANN-based Modeling Attack
Application-based protection	Exploiting Application Tolerance for Functional Safety
Architecturally Correct Execution	ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph
area	Unified Test Flow for DFT Power, Performance & Area Optimization
artificial intelligence	AAA: Automated On-ATE AI Debug of Scan Chain Failures
ATE	3.5Gsps MIPI C-PHY Receiver Circuit for Automatic Test Equipment Systematic Hardware Error Identification and Calibration for Massive Multisite Testing Practical Methods to Test MIPI C-Phy Data Interfaces
ATPG	Multi-Transition Fault Model (MTFM) ATPG patterns towards achieving 0 DPPB on AUTOMOTIVE designs A Scalable Design Flow for Performance Monitors Using Functional Path Ring Oscillators Power-Aware ATPG Using Sign-Off Models Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis (best paper award, ITC-India 2021)
Authentication	Security EDA Extension through P1687.1 and 1687 Callbacks
AutoEncoder	Smart Sampling for Efficient System Level Test: A Robust Machine Learning Approach
Automated Test Environments	Security EDA Extension through P1687.1 and 1687 Callbacks
Automatic Test Equipment	Automatic Verification of Mixed-Signal ATE Test Programs using Device Variation
automatic test pattern generation	On Reduction of Deterministic Test Pattern Sets
automatic testing	(Invited) IEEE P1687.1 Data Retargeting and Transfer Procedures for Accessing Internal Cores
automotive	(Invited) Security and Provisioning of Automotive IC’s through Test and Safety
Autonomous Vehicles	Hierarchical Failure Modeling and Machine Learning Assisted Correction of Subsystem Failures in Autonomous Vehicles
B
Backdoored checksum	On-line Functional Testing of Memristor-mapped Deep Neural Networks using Backdoored Checksums
BIST	Background Receiver IQ Imbalance Correction for in-Field and Post-Production Testing and Calibration A BIST-based Dynamic Obfuscation Scheme for Resilience against Removal and Oracle-guided Attacks A Fast and Low Cost Embedded Test Solution for CMOS Image Sensors Memory BIST requirements Built-in self-test functions to mitigate eMRAM test challenges
board level connectivity	Assisting board level connectivity test with IEEE Std 1581
Board Test	Utilizing IEEE Std 1687 for board level test
C
C-Phy	Practical Methods to Test MIPI C-Phy Data Interfaces
C-PHY Receiver	3.5Gsps MIPI C-PHY Receiver Circuit for Automatic Test Equipment
Calibration	Systematic Hardware Error Identification and Calibration for Massive Multisite Testing
Callbacks	Security EDA Extension through P1687.1 and 1687 Callbacks
cell aware test	Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis (best paper award, ITC-India 2021)
Cell-Net	Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin
chain diagnosis	A Multi-Threaded Single-Pass Diagnosis of Scan Chain Failures
Charge pump	A Novel Method to measure PLL Bandwidth in a 5G RF transceiver (2nd honorable mention paper award, ITC-India 2021)
Chip Performance Prediction	Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning
CIS	3.5Gsps MIPI C-PHY Receiver Circuit for Automatic Test Equipment
CMOS image sensor	A Fast and Low Cost Embedded Test Solution for CMOS Image Sensors
Computing-in-Memory	Analyzing and Mitigating Sensing Failures in Spintronic-based Computing in Memory
Concurrent Error Correction	Impeccable Circuits III
Concurrent Error Detection	Impeccable Circuits III
congestion	Unified Test Flow for DFT Power, Performance & Area Optimization
contrastive learning	Semi-supervised Wafer Map Pattern Recognition using Domain-Specific Data Augmentation and Contrastive Learning
cores	Cores that don’t count
Corruptibility	Characterizing Corruptibility of Logic Locks using ATPG
count	Cores that don’t count
Cross-Layer Safety Analysis	Compositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation
CTLE	3.5Gsps MIPI C-PHY Receiver Circuit for Automatic Test Equipment
Current Source	High Bandwidth Current Sourcing with the Howland Current Source
custom ASIC	Seamless Physical Implementation of ASIC Hierarchical Integrated Scan Architecture
D
data center	Silent Data Corruptions at Scale
data centers	A Software Solution for Managing Silicon Defects in Data Centers
decision tree	Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin
deep learning accelerators	Efficient Functional In-Field Self-Test for Deep Learning Accelerators
Deep neural network	On-line Functional Testing of Memristor-mapped Deep Neural Networks using Backdoored Checksums
Defect	Defect-Directed Stress Testing Using I-PAT Inline Defect Inspection Results
defect dependent reflection (DDR)	Open-short Normalization Method for a Quick Defect Identification in Branched Traces with High-resolution Time-domain Reflectometry
defect identification	Open-short Normalization Method for a Quick Defect Identification in Branched Traces with High-resolution Time-domain Reflectometry
defect independent reflection (DIR)	Open-short Normalization Method for a Quick Defect Identification in Branched Traces with High-resolution Time-domain Reflectometry
defect pattern	Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques
Defect pattern classification	Brain-Inspired Computing for Wafer Map Defect Pattern Classification
Delay Testing	Is your secure test infrastructure secure enough? Attacks based on delay test patterns using transient behavior analysis
design convergence	Seamless Physical Implementation of ASIC Hierarchical Integrated Scan Architecture
Design for testability	LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment
Design-for-Test	Testability-Enhancing Resynthesis of Reconfigurable Scan Networks
Deviation tolerance	On-line Functional Testing of Memristor-mapped Deep Neural Networks using Backdoored Checksums
Device Variation	Automatic Verification of Mixed-Signal ATE Test Programs using Device Variation
device-aware	Device-Aware Test for STT-MRAM
DFT	Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits Unified Test Flow for DFT Power, Performance & Area Optimization Moderator: Intro and framing of the session
diagnosis resolution	Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization
DIB Hardware Solution	High Bandwidth Current Sourcing with the Howland Current Source
Digital circuit testing	Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis (best paper award, ITC-India 2021)
Digital to Analog Converter	A Novel Method to measure PLL Bandwidth in a 5G RF transceiver (2nd honorable mention paper award, ITC-India 2021)
dimensional extension	The Security Enhancement Techniques of the Double-layer PUF Against the ANN-based Modeling Attack
Direct conversion receiver	Background Receiver IQ Imbalance Correction for in-Field and Post-Production Testing and Calibration
Domain-Specific Languages	Security EDA Extension through P1687.1 and 1687 Callbacks
DPPM	Smart Sampling for Efficient System Level Test: A Robust Machine Learning Approach
Dynamic Obfuscation	A BIST-based Dynamic Obfuscation Scheme for Resilience against Removal and Oracle-guided Attacks
E
EDA	3DIC Test Challenges, Trends and Solutions - an EDA perspective
embedded	In-Field Embedded Sensing & PVT Monitoring for Increased Device Power and Performance Optimization STT-MRAM technology for embedded applications
Embedded Core	Revisions to IEEE Std 1500, Standard Testability Method for Embedded Core-based Integrated Circuits
embedded core testing	(Invited) IEEE P1687.1 Data Retargeting and Transfer Procedures for Accessing Internal Cores
embedded cores	(Invited) IEEE P1687.1 Data Retargeting and Transfer Procedures for Accessing Internal Cores
embedded instruments	Accessing general IEEE Std. 1687 networks via functional ports
Embedding learning	MINiature Interactive Offset Networks (MINIONs) for Wafer Map Classification
Equalizer	3.5Gsps MIPI C-PHY Receiver Circuit for Automatic Test Equipment
ETS-800	High Bandwidth Current Sourcing with the Howland Current Source
Evolutionary Learning	Testability-Aware Low Power Controller Design with Evolutionary Learning
expert system	AAA: Automated On-ATE AI Debug of Scan Chain Failures
F
fabless	Designing and testing 3D devices – A fabless company perspective
Failure Analysis	Relevant Signals and Devices for Failure Analysis of Analog and Mixed-signal Circuits
Failure Correction	Hierarchical Failure Modeling and Machine Learning Assisted Correction of Subsystem Failures in Autonomous Vehicles
False Summing Node Method	Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer
Fast Fourier Transform (FFT)	A Novel Method to measure PLL Bandwidth in a 5G RF transceiver (2nd honorable mention paper award, ITC-India 2021)
Fault Analysis Countermeasure	Impeccable Circuits III
Fault Injection	An automated formal-based approach for reducing Undetected faults in ISO26262 hardware compliant designs
fault modeling	Hierarchical Failure Modeling and Machine Learning Assisted Correction of Subsystem Failures in Autonomous Vehicles Device-Aware Test for STT-MRAM
Fault Models	Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis (best paper award, ITC-India 2021)
Fault Reduction	ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph
Fault Sensitivity Analysis	Is your secure test infrastructure secure enough? Attacks based on delay test patterns using transient behavior analysis
faulty CPUs	A Software Solution for Managing Silicon Defects in Data Centers
Feature extraction	Brain-Inspired Computing for Wafer Map Defect Pattern Classification
FFT	Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies
FinFET	Adaptive High Voltage Stress Methodology to Enable Automotive Quality on FinFET Technologies
Fingerprinting	Study on High-Accuracy and Low-Cost Recycled FPGA Detection
Finite State Machine	Layout Informed Multiple Bit Upset Hardening of Finite State Machines Understanding Tool Synthesis Behavior and Safe Finite State Machine Design
flat-top window	Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies
Formal Fault Propagation Analysis	Compositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation
Formal Methods	SymbA: Symbolic Execution at C-level for Hardware Trojan Activation An automated formal-based approach for reducing Undetected faults in ISO26262 hardware compliant designs
Foundry	Testing challenges and solutions for advanced packaging technologies - A foundry perspective
FPGA	Study on High-Accuracy and Low-Cost Recycled FPGA Detection
FR4	FR4 could be better than Tachyon-100G for post-silicon validation on LVDS signaling
functional criticality	Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin
Functional Fault	ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph
functional path	A Scalable Design Flow for Performance Monitors Using Functional Path Ring Oscillators
functional port as test interface	Accessing general IEEE Std. 1687 networks via functional ports
Functional Safety	Exploiting Application Tolerance for Functional Safety An automated formal-based approach for reducing Undetected faults in ISO26262 hardware compliant designs
functional self test	Efficient Functional In-Field Self-Test for Deep Learning Accelerators
Functional testing	On-line Functional Testing of Memristor-mapped Deep Neural Networks using Backdoored Checksums
G
Gaussian process	Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process
generic IEEE P1687.1 transformations	(Invited) IEEE P1687.1 Data Retargeting and Transfer Procedures for Accessing Internal Cores
Genetic Algorithm	Testability-Aware Low Power Controller Design with Evolutionary Learning
H
Hardware Security	A BIST-based Dynamic Obfuscation Scheme for Resilience against Removal and Oracle-guided Attacks Characterizing Corruptibility of Logic Locks using ATPG
Hardware Systematic Errors	Systematic Hardware Error Identification and Calibration for Massive Multisite Testing
Hardware Trojans	SymbA: Symbolic Execution at C-level for Hardware Trojan Activation
Harmonic Distortion	Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer
hierarchical integrated scan	Seamless Physical Implementation of ASIC Hierarchical Integrated Scan Architecture
Hierarchical Systems	Hierarchical Failure Modeling and Machine Learning Assisted Correction of Subsystem Failures in Autonomous Vehicles
High Bandwidth	High Bandwidth Current Sourcing with the Howland Current Source
high coverage	Efficient Functional In-Field Self-Test for Deep Learning Accelerators
High Reliability	Layout Informed Multiple Bit Upset Hardening of Finite State Machines
High-Reliability	Understanding Tool Synthesis Behavior and Safe Finite State Machine Design
high-resolution TDR	Open-short Normalization Method for a Quick Defect Identification in Branched Traces with High-resolution Time-domain Reflectometry
Howland Current Source	High Bandwidth Current Sourcing with the Howland Current Source
HVST	Adaptive High Voltage Stress Methodology to Enable Automotive Quality on FinFET Technologies
HW/SW Systems	Compositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation
I
IC Test	Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer
IEEE 1500
IEEE 1687	Utilizing IEEE Std 1687 for board level test IEEE P1687.1: The Trouble with Transforms
IEEE 1838
IEEE Std 1500	Revisions to IEEE Std 1500, Standard Testability Method for Embedded Core-based Integrated Circuits
IEEE Std 1581	Assisting board level connectivity test with IEEE Std 1581
IEEE Std. 1149.1	Accessing general IEEE Std. 1687 networks via functional ports
IEEE Std. 1687	Accessing general IEEE Std. 1687 networks via functional ports
IEEE Std. P1687.1	Accessing general IEEE Std. 1687 networks via functional ports
IJTAG	Utilizing IEEE Std 1687 for board level test IEEE P1687.1: The Trouble with Transforms
In-Field	Efficient Functional In-Field Self-Test for Deep Learning Accelerators In-Field Embedded Sensing & PVT Monitoring for Increased Device Power and Performance Optimization
incoherent sampling	Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies
Inline	Defect-Directed Stress Testing Using I-PAT Inline Defect Inspection Results
Insider Attack Detection	Generalized Insider Attack Detection Implementation using NetFlow Data for Distributed Test Range Networks
Integrated Circuits and Boards	Adaptive Methods for Machine Learning-Based Testing of Integrated Circuits and Boards
IOT	(Invited) IEEE P1687.1 Data Retargeting and Transfer Procedures for Accessing Internal Cores
IP Security	A BIST-based Dynamic Obfuscation Scheme for Resilience against Removal and Oracle-guided Attacks
IQ correction	Background Receiver IQ Imbalance Correction for in-Field and Post-Production Testing and Calibration
IQ imbalance	Background Receiver IQ Imbalance Correction for in-Field and Post-Production Testing and Calibration
ir-drop	Power-Aware ATPG Using Sign-Off Models
ISO26262	An automated formal-based approach for reducing Undetected faults in ISO26262 hardware compliant designs
J
jitter generation	Jitter Injection with pre- and post- emphasis circuits
jitter injection	Jitter Injection with pre- and post- emphasis circuits
L
Layout	Layout Informed Multiple Bit Upset Hardening of Finite State Machines Unified Test Flow for DFT Power, Performance & Area Optimization
LED Driver	High Bandwidth Current Sourcing with the Howland Current Source
Logic Locking	A BIST-based Dynamic Obfuscation Scheme for Resilience against Removal and Oracle-guided Attacks Characterizing Corruptibility of Logic Locks using ATPG LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment
Logic Testing	SymbA: Symbolic Execution at C-level for Hardware Trojan Activation
low DPPM	Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis (best paper award, ITC-India 2021)
Low Power Controller	Testability-Aware Low Power Controller Design with Evolutionary Learning
Low Power Test	Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits
LVDS	FR4 could be better than Tachyon-100G for post-silicon validation on LVDS signaling
M
Machine Learning	Brain-Inspired Computing for Wafer Map Defect Pattern Classification Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning Machine Learning for Circuit Aging Estimation under Workload Dependency WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques Generalized Insider Attack Detection Implementation using NetFlow Data for Distributed Test Range Networks Smart Sampling for Efficient System Level Test: A Robust Machine Learning Approach Adaptive Methods for Machine Learning-Based Testing of Integrated Circuits and Boards
Manufacturing	Brain-Inspired Computing for Wafer Map Defect Pattern Classification
Manufacturing Defects	Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions
Manufacturing test	LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment
Memory	Memory BIST requirements
memory interface test	Addressing High Speed Memory Interface Test Quality Gaps in Shared Bus Architecture (1st honorable mention paper award, ITC-India 2021)
memory repair	Memory repair
memory yield	Memory repair
Memristor crossbar	On-line Functional Testing of Memristor-mapped Deep Neural Networks using Backdoored Checksums
Minions	MINiature Interactive Offset Networks (MINIONs) for Wafer Map Classification
MIPI	3.5Gsps MIPI C-PHY Receiver Circuit for Automatic Test Equipment Practical Methods to Test MIPI C-Phy Data Interfaces
misclassification-driven training	Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin
Monitoring	In-Field Embedded Sensing & PVT Monitoring for Increased Device Power and Performance Optimization
MRAM	Design of Reliable Sensing Mechanisms in STT-MRAM Built-in self-test functions to mitigate eMRAM test challenges
Multi-Pattern Wafer Map	Triplet Convolutional Networks for Classifying Mixed-Type WBM Patterns with Noisy Labels
Multi-site test	Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process
Multiple Bit Upset	Layout Informed Multiple Bit Upset Hardening of Finite State Machines
multiple transition	Multi-Transition Fault Model (MTFM) ATPG patterns towards achieving 0 DPPB on AUTOMOTIVE designs
Multisite Testing	Systematic Hardware Error Identification and Calibration for Massive Multisite Testing
Mutation Testing	Automatic Verification of Mixed-Signal ATE Test Programs using Device Variation
N
necessary assignments	On Reduction of Deterministic Test Pattern Sets
neural twin	Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin
NeuralNetwork	Adaptive NN-based Root Cause Analysis in Volume Diagnosis for Yield Improvement
non-TAP interface	IEEE P1687.1: The Trouble with Transforms
O
On-Chip Decompressor	Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits
On-line testing	On-line Functional Testing of Memristor-mapped Deep Neural Networks using Backdoored Checksums
One-shot learning	MINiature Interactive Offset Networks (MINIONs) for Wafer Map Classification
open-short normalization (OSN)	Open-short Normalization Method for a Quick Defect Identification in Branched Traces with High-resolution Time-domain Reflectometry
Operational Amplifier	Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer
optical test	A Fast and Low Cost Embedded Test Solution for CMOS Image Sensors
P
Packaging	Testing challenges and solutions for advanced packaging technologies - A foundry perspective
path delay	A Scalable Design Flow for Performance Monitors Using Functional Path Ring Oscillators
pattern optimization	Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis (best paper award, ITC-India 2021)
PCB material	FR4 could be better than Tachyon-100G for post-silicon validation on LVDS signaling
PE-Net	Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin
performance	Unified Test Flow for DFT Power, Performance & Area Optimization
performance screening	A Scalable Design Flow for Performance Monitors Using Functional Path Ring Oscillators
periodic maintenance	A Software Solution for Managing Silicon Defects in Data Centers
Phase Locked loop (PLL)	A Novel Method to measure PLL Bandwidth in a 5G RF transceiver (2nd honorable mention paper award, ITC-India 2021)
physical design	Seamless Physical Implementation of ASIC Hierarchical Integrated Scan Architecture
physical implementation	Unified Test Flow for DFT Power, Performance & Area Optimization
physical layer	Practical Methods to Test MIPI C-Phy Data Interfaces
physical synthesis	Unified Test Flow for DFT Power, Performance & Area Optimization
pixel array	A Fast and Low Cost Embedded Test Solution for CMOS Image Sensors
power	Unified Test Flow for DFT Power, Performance & Area Optimization
power-aware	Power-Aware ATPG Using Sign-Off Models
PPA	Unified Test Flow for DFT Power, Performance & Area Optimization
process and runtime variation	Analyzing and Mitigating Sensing Failures in Spintronic-based Computing in Memory
Process variation	Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning
production test	Practical Methods to Test MIPI C-Phy Data Interfaces
PUF	The Security Enhancement Techniques of the Double-layer PUF Against the ANN-based Modeling Attack
R
Radio Frequency (RF)	A Novel Method to measure PLL Bandwidth in a 5G RF transceiver (2nd honorable mention paper award, ITC-India 2021)
RAM sequential ATPG	Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis (best paper award, ITC-India 2021) Addressing High Speed Memory Interface Test Quality Gaps in Shared Bus Architecture (1st honorable mention paper award, ITC-India 2021)
Read Decision Failure	Analyzing and Mitigating Sensing Failures in Spintronic-based Computing in Memory
Reconfigurable Scan Networks	Testability-Enhancing Resynthesis of Reconfigurable Scan Networks Security EDA Extension through P1687.1 and 1687 Callbacks
Recycling Detection	Study on High-Accuracy and Low-Cost Recycled FPGA Detection
relevant devices	Relevant Signals and Devices for Failure Analysis of Analog and Mixed-signal Circuits
relevant signals	Relevant Signals and Devices for Failure Analysis of Analog and Mixed-signal Circuits
Reliability	Machine Learning for Circuit Aging Estimation under Workload Dependency ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph Software-Based Self-Test for Transition Delay Faults in Pipelined Processors
reliable sensing mechanisms	Design of Reliable Sensing Mechanisms in STT-MRAM
repair sharing	Memory repair
ReRAM	On-line Functional Testing of Memristor-mapped Deep Neural Networks using Backdoored Checksums
RF receiver	Background Receiver IQ Imbalance Correction for in-Field and Post-Production Testing and Calibration
ring oscillator	A Scalable Design Flow for Performance Monitors Using Functional Path Ring Oscillators
robustness	Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin
RootCauseAnalysis	Adaptive NN-based Root Cause Analysis in Volume Diagnosis for Yield Improvement
RoT (Root of Trust)	(Invited) Security and Provisioning of Automotive IC’s through Test and Safety
routing	Layout Informed Multiple Bit Upset Hardening of Finite State Machines Unified Test Flow for DFT Power, Performance & Area Optimization
S
Safe Faults	An automated formal-based approach for reducing Undetected faults in ISO26262 hardware compliant designs
scan chain failure	AAA: Automated On-ATE AI Debug of Scan Chain Failures
scan compression	A Multi-Threaded Single-Pass Diagnosis of Scan Chain Failures
scan-based designs	On Reduction of Deterministic Test Pattern Sets
Secure Access	Security EDA Extension through P1687.1 and 1687 Callbacks
security	(Invited) Security and Provisioning of Automotive IC’s through Test and Safety
Security Metrics	Characterizing Corruptibility of Logic Locks using ATPG
Self-AdaptiveLearning	Adaptive NN-based Root Cause Analysis in Volume Diagnosis for Yield Improvement
semi-supervised learning	Semi-supervised Wafer Map Pattern Recognition using Domain-Specific Data Augmentation and Contrastive Learning
Semiconductor testing	Brain-Inspired Computing for Wafer Map Defect Pattern Classification
SerDes	Jitter Injection with pre- and post- emphasis circuits
serial interface	(Invited) IEEE P1687.1 Data Retargeting and Transfer Procedures for Accessing Internal Cores
Shared bus interface	Addressing High Speed Memory Interface Test Quality Gaps in Shared Bus Architecture (1st honorable mention paper award, ITC-India 2021)
Silent data corruption	Silent Data Corruptions at Scale
silicon	Silent Data Corruptions at Scale Cores that don’t count
Simulation	An automated formal-based approach for reducing Undetected faults in ISO26262 hardware compliant designs
SINAD	Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies
Single Event Upset	Layout Informed Multiple Bit Upset Hardening of Finite State Machines Understanding Tool Synthesis Behavior and Safe Finite State Machine Design
Site to Site Variations	Systematic Hardware Error Identification and Calibration for Massive Multisite Testing
SLT	Smart Sampling for Efficient System Level Test: A Robust Machine Learning Approach
small delay defects	Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis (best paper award, ITC-India 2021)
Smart Sampling	Smart Sampling for Efficient System Level Test: A Robust Machine Learning Approach
Soft error mitigation	Exploiting Application Tolerance for Functional Safety
Soft Errors	ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph
Soft-Errors	Compositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation
software-based self-test	Software-Based Self-Test for Transition Delay Faults in Pipelined Processors
Spintronic	Analyzing and Mitigating Sensing Failures in Spintronic-based Computing in Memory
Standards
static test compaction	On Reduction of Deterministic Test Pattern Sets
Statistical Ineffective Fault Attack (SIFA)	Impeccable Circuits III
Stress	Defect-Directed Stress Testing Using I-PAT Inline Defect Inspection Results
structural faults	Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin
STT-MRAM	Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions STT-MRAM technology for embedded applications Device-Aware Test for STT-MRAM
Stuck At	Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits
Summing Node Method	Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer
SVM	Smart Sampling for Efficient System Level Test: A Robust Machine Learning Approach
Symbolic execution	SymbA: Symbolic Execution at C-level for Hardware Trojan Activation
Synthesis	Understanding Tool Synthesis Behavior and Safe Finite State Machine Design
systematic defect	Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization
T
Tachyon-100G	FR4 could be better than Tachyon-100G for post-silicon validation on LVDS signaling
Template Attack	Is your secure test infrastructure secure enough? Attacks based on delay test patterns using transient behavior analysis
Test	Defect-Directed Stress Testing Using I-PAT Inline Defect Inspection Results Designing and testing 3D devices – A fabless company perspective Assisting board level connectivity test with IEEE Std 1581
Test Compression	On Reduction of Deterministic Test Pattern Sets Testability-Aware Low Power Controller Design with Evolutionary Learning
test debug	AAA: Automated On-ATE AI Debug of Scan Chain Failures
Test Infrastructure Security	Is your secure test infrastructure secure enough? Attacks based on delay test patterns using transient behavior analysis
test program generation	Software-Based Self-Test for Transition Delay Faults in Pipelined Processors
Test Program Verification	Automatic Verification of Mixed-Signal ATE Test Programs using Device Variation
Test Range networks	Generalized Insider Attack Detection Implementation using NetFlow Data for Distributed Test Range Networks
Test Standards	Security EDA Extension through P1687.1 and 1687 Callbacks
Test Technology
Test Volume Data	Systematic Hardware Error Identification and Calibration for Massive Multisite Testing
Testability	Testability-Enhancing Resynthesis of Reconfigurable Scan Networks
Tester	3.5Gsps MIPI C-PHY Receiver Circuit for Automatic Test Equipment
Testing	Adaptive Methods for Machine Learning-Based Testing of Integrated Circuits and Boards Testing challenges and solutions for advanced packaging technologies - A foundry perspective
threaded diagnosis	A Multi-Threaded Single-Pass Diagnosis of Scan Chain Failures
timing constraints	Seamless Physical Implementation of ASIC Hierarchical Integrated Scan Architecture
trace with branches	Open-short Normalization Method for a Quick Defect Identification in Branched Traces with High-resolution Time-domain Reflectometry
Transfer learning	MINiature Interactive Offset Networks (MINIONs) for Wafer Map Classification
transformation algorithm	(Invited) IEEE P1687.1 Data Retargeting and Transfer Procedures for Accessing Internal Cores
Transient Fault	ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph
transistor aging	Machine Learning for Circuit Aging Estimation under Workload Dependency
Transition	Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits
transition delay fault	Software-Based Self-Test for Transition Delay Faults in Pipelined Processors
Trim search	Built-in self-test functions to mitigate eMRAM test challenges
Triplet CNN	Triplet Convolutional Networks for Classifying Mixed-Type WBM Patterns with Noisy Labels
tunability	STT-MRAM technology for embedded applications
U
udfm	Multi-Transition Fault Model (MTFM) ATPG patterns towards achieving 0 DPPB on AUTOMOTIVE designs
unsupervised machine learning	Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling
Untrusted foundry	LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment
V
validation	FR4 could be better than Tachyon-100G for post-silicon validation on LVDS signaling
variability	Design of Reliable Sensing Mechanisms in STT-MRAM
Verification	An automated formal-based approach for reducing Undetected faults in ISO26262 hardware compliant designs
Voltage controlled Oscillator (VCO)	A Novel Method to measure PLL Bandwidth in a 5G RF transceiver (2nd honorable mention paper award, ITC-India 2021)
volume diagnosis	Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization
W
wafer map	Brain-Inspired Computing for Wafer Map Defect Pattern Classification Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques
Wafer map classification	MINiature Interactive Offset Networks (MINIONs) for Wafer Map Classification
wafer map pattern recognition	Semi-supervised Wafer Map Pattern Recognition using Domain-Specific Data Augmentation and Contrastive Learning
Wafer-level Variation Modeling	Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process
Weakly Supervised Learning	Triplet Convolutional Networks for Classifying Mixed-Type WBM Patterns with Noisy Labels
Weight deviation	On-line Functional Testing of Memristor-mapped Deep Neural Networks using Backdoored Checksums
Wrapper	Revisions to IEEE Std 1500, Standard Testability Method for Embedded Core-based Integrated Circuits
X
XORing	The Security Enhancement Techniques of the Double-layer PUF Against the ANN-based Modeling Attack
Y
yield learning	Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques
YieldImprovement	Adaptive NN-based Root Cause Analysis in Volume Diagnosis for Yield Improvement
Z
zero defect	Multi-Transition Fault Model (MTFM) ATPG patterns towards achieving 0 DPPB on AUTOMOTIVE designs
Zero IF Receiver	Background Receiver IQ Imbalance Correction for in-Field and Post-Production Testing and Calibration

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