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09:00-09:30Coffee Break (Social Time in Gather.Town)
09:30-10:30 Session 5A: Circuits and Monitors (Ind. Papers)
Location: Zoom Room A
Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies

ABSTRACT. This paper describes that the mature ADC testing method with a simple test system using the incoherent sampling and the standard algorithm of windowing and FFT with 4K-point data can measure the SINAD of our target 12-bit SAR ADC accurately by proper setting of the input and sampling frequencies, which is industry-friendly. We show the input sinusoidal signal and sampling clock frequency relationship for accurate testing of the ADC dynamic characteristics with an incoherent sampling method using a flat-top window. We have clarified the measured SINAD accuracy of the input signal frequency dependency for a fixed sampling frequency.

Adaptive High Voltage Stress Methodology to Enable Automotive Quality on FinFET Technologies
PRESENTER: Stephen Traynor

ABSTRACT. High Voltage Stress Test (HVST) is critical for screening out latent defects to ensure quality on automotive semiconductor devices. This paper describes a novel way to adaptively adjust HVST stress voltage based on real-time current measurement to ensure every part is stressed reliably at the highest possible voltage within the tester hardware current limit as well as with equivalent extrinsic defect coverage on FinFET technologies.

3.5Gsps MIPI C-PHY Receiver Circuit for Automatic Test Equipment
PRESENTER: Seongkwan Lee

ABSTRACT. This paper presents 3.5Gsps MIPI C-PHY analog front end receiver circuit for Automatic Test Equipment. This circuit has two features. First, it is made entirely of off-the-shelf components. Second, it has powerful CTLE to compensate for transmission line loss. Since it does not use ASIC, it is possible to add functions at a low cost and in a short time. In the wafer test environment, the loss between the wafer and the receiving circuit is large. This CTLE can be fine-tuned and effectively eliminate the transmission line loss of the developed equipment.

A Scalable Design Flow for Performance Monitors Using Functional Path Ring Oscillators
PRESENTER: Tobias Kilian

ABSTRACT. The automotive industry sets high reliability standards for microcontroller (MCUs). To increase reliability, the automotive MCU manufacturers are looking for accurate performance screening. One of these performance screening mechanisms are functional path ring oscillators (RO). In this paper, a scalable and efficient method for creating functional path ring oscillators is presented. Implementation data demonstrate that functional path RO monitors show a significant advantage in area and power consumption over comparable performance screening methods.

09:30-10:30 Session 5B: Test Data (Short Paper)
Location: Zoom Room B
WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques
PRESENTER: Peter Yi-Yu Liao

ABSTRACT. Wafer map defect pattern recognition provides a visual way for root cause analysis. Specially, recognizing grid, including line and intersection point types, is a challenging problem for process and test engineers. Grid is a repeating defect pattern that appears in multiple wafers, so identifying such patterns helps to trace the root cause of defects for yield ramp up. In this paper, we propose a systematic methodology to search for hidden grid patterns in wafers. Experimental results show the proposed method can achieve 100% prediction accuracy for all grid types, and achieve 96.45% for all nine common wafer defect types.

AAA: Automated On-ATE AI Debug of Scan Chain Failures

ABSTRACT. Failing test debug is human-time-intensive, requiring domain experts to develop and execute fact-finding experiments. With the increasing size and complexity of modern circuits it is impossible for these few experts to support all required debug. To overcome this bottleneck to expertise we propose AAA, a rule-based expert system to perform the procedure of an expert performing failure debug, including dynamic creation/application of targeted debug tests, collection of on-tester failure results, and results interpretation for root-cause analysis. We demonstrate the system on industrial chips with scan-chain failures, showing that debug tasks that previously took hours can complete automatically in minutes.

Systematic Hardware Error Identification and Calibration for Massive Multisite Testing
PRESENTER: Praise Farayola

ABSTRACT. Multisite testing tests multiple chips simultaneously. When implemented on a large scale (massive multisite), interference and coupling on the test hardware often affect test sites differently, introducing variations in site measurements. Making a reasonable assumption that each site introduces errors to test measurement, we model each test site’s measurement as a weak nonlinear function of the true chip measurement with systematic errors. We propose an algorithm to solve for these systematic errors using volume test data and calibrate test data. We apply the proposed method to simulated and real test volume data and confirm the accuracy of the method.

Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits

ABSTRACT. This paper proposes a DFT-based approach which reduces both shift and capture power during test by splitting the scan chains into segments that ideally only capture when new faults are detected. Unlike our previous work, here extra control bits are inserted in between the segments to determine whether a particular segment will capture. A significant advantage of this approach is that a standard ATPG tool is capable of automatically generating the control bits value without the need for successive post processing or modification for the tool. For the circuits we have studied, up to 37% power reduction can be achieved.

09:30-10:30 Session 5C: Test Architecture and Infrastructure (Short Paper)
Location: Zoom Room C
Is your secure test infrastructure secure enough? Attacks based on delay test patterns using transient behavior analysis
PRESENTER: Sergej Meschkov

ABSTRACT. Existing work on securing test infrastructure is based on restricting or encrypting test access to sensitive information, such that secret information can not be accessed publicly. In this work we invalidate this assumption by showing that by having access to (small delay) test results on insensitive (public) outputs, we can still extract secret data. Using real hardware, we have performed attacks using results of delay testing on cryptographic circuits, and were able to retrieve the key with results of just two delay test patterns. The attack is resilient against variations and noise, as well as lower resolution delay testing results.

Seamless Physical Implementation of ASIC Hierarchical Integrated Scan Architecture
PRESENTER: Bambang Suparjo

ABSTRACT. Hierarchical integrated scan provides many benefits for testing large custom ASIC designs. Physical implementation at full chip level however becomes very challenging as the number of blocks and the levels of hierarchy increase. Additionally, maintaining timing constraints at multiple levels of hierarchy can be very resource intensive. This paper presents a novel framework to overcome these challenges using full chip scan architectural innovation. Our data shows that framework provides significant improvements in terms of test coverage and design convergence time without any design quality loss, thus generating cost saving and accelerating time-to-market.

Testability-Aware Low Power Controller Design with Evolutionary Learning

ABSTRACT. XORNet-based low power controller is a popular technique to reduce circuit transitions in scan-based testing. However, existing solutions just randomly form the XORNet for scan chain control, and it may result in sub-optimal solutions without any design guidance. In this paper, we propose a novel testability-aware low power controller with evolutionary learning. The XORNet generated from the proposed genetic algorithm (GA) enables adaptive control for scan chains according to their usages, thereby significantly improving XORNet encoding capacity, reducing the number of failure cases with ATPG and decreasing test data volume.

An automated formal-based approach for reducing Undetected faults in ISO26262 hardware compliant designs

ABSTRACT. The safety demands for developing automotive applications require comprehensive analysis to evaluate potential random hardware failures. Due to the complexity, part of this analysis must be manually performed by experts, resulting in a process that is expensive, time-consuming, and prone to errors. This paper proposes an automated approach to classify faults overlooked by other technologies by identifying nodes that do not disrupt safety-critical functionalities. We validate the methodology on an Automotive CPU, following ISO26262 guidelines. Our approach improves the Diagnostic Coverage by 1.15%, increasing the Single Point Fault Metric (SPFM) to 97.3%, enabling ASIL C compliance without hardware redundancy.

09:30-10:30 Session 5D: Special Session: Accellera FuSa WG: Automation, Interoperability and Traceability in Functional Safety Standardization

An informative session about a new Functional Safety standard being developed by Accellera. We have all the WG leads present to discuss it. 

Organizers: Nir Maor, Qualcomm &  Yervant Zorian, Synopsys

Moderators: Alessandra Nardi, Cadence & Nir Maor, Qualcomm


- Ghani Kanawati, Arm

- Andres Barrilado, NXP

- Meirav Nitzan, Synopsys

- Bala Chavali, AMD  

- Shrenik Mehta, Xilinx   

Location: Zoom Room D
10:30-11:00Coffee Break (Social Time in Gather.Town)
11:00-12:00Supporter/Exhibitor Presentations
12:00-13:00 Session 6A: What's going on with 1687*?
Location: Zoom Room A
Security EDA Extension through P1687.1 and 1687 Callbacks

ABSTRACT. The world of testing has been living a huge transformation pushed by constraints and requirements coming from a large variety of sources and applications. The need for higher accessibility, controllability and reuse led to solutions such as IEEE 1687 or P1687.1. All the while, these same features are raising security concerns. Standards usual approach of relying on Domain-Specific Languages has difficulty in handling such disparate and often conflicting needs, with the risk of a dangerous proliferation of custom and incompatible solutions. In this paper, we show how the usage of Callbacks, defined in P1687.1, can help solve this issue.

Accessing general IEEE Std. 1687 networks via functional ports
PRESENTER: Erik Larsson

ABSTRACT. IEEE Std. 1687 networks are typically accessed via a dedicated test port, like IEEE Std. 1149.1. As not all integrated circuits have a dedicated test port, IEEE Std. P1687.1 explores how functional ports can be used. Challenges are to determine hardware in the component translating information between a functional port and an IEEE Std. 1687 network and to describe a protocol for the data transported over a functional interface. We present a solution to handle general IEEE Std. 1687 networks, which we implemented on an FPGA and evaluated on various benchmarks in respect to data overhead and the area usage.

(Invited) IEEE P1687.1 Data Retargeting and Transfer Procedures for Accessing Internal Cores
PRESENTER: Michael Laisne

ABSTRACT. This paper, reviews the latest topics being discussed by the IEEE 1687.1 working group, including showing how a taxonomy of IJTAG instructions supports the development of callbacks. It discusses how proto buffers can be used to help bridge the gap from a host controller, like an ATE, and to an IJTAG network. The approach leverages concept of RPCs (Remote Procedural Calls) and the integer bit vector (intbv) concept to support communications through interfaces and between subroutines handling retargeting and handling control of the interface. The techniques are applied to several examples, including I2C and IEEE 1149.7-like interface.

12:00-13:00 Session 6B: Analog Testing
Location: Zoom Room B
Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer
PRESENTER: Daisuke Iimori

ABSTRACT. This paper investigates the harmonic distortion measurement of the operational amplifier by applying our proposed summing node method and shows that it can provide low-cost and high-accuracy testing at their mass production shipping stage. Our measurement results show that measurement accuracy as below as -130 dBc is possible without expensive test equipment such as an audio analyzer. We show by theory, simulations and experiments that the measurement accuracy of the summing node method is tolerable for the harmonics of the signal source which provides the sinusoidal input signal to the operational amplifier under test.

Automatic Verification of Mixed-Signal ATE Test Programs using Device Variation
PRESENTER: Franziska Mayer

ABSTRACT. This paper proposes a methodology for automated test program verification for semiconductor test. A formalized test specification is extended by emulated device responses and expected test program results in an abstract format. This allows to create a high number of test sets based on a mutation testing approach without a physical device nor a test system. The results of an offline execution are compared against expected ones leading to a qualified assessment of the test program. The concept is proven by implementation of a special subset for a given test program.

Background Receiver IQ Imbalance Correction for in-Field and Post-Production Testing and Calibration
PRESENTER: Muslum Emir Avci

ABSTRACT. Due to their simplicity, low power consumption and high-performance direct conversion transceivers are used in RF-front ends. Performance of the direct conversion receivers is susceptible to I/Q mismatch. We use an envelope detector to detect combined amplitudes of the I and Q signals and we use this information to iteratively correct for the receiver's IQ imbalance. The proposed method can be used in mission mode in the background to calibrate any deviations in performance. After the receiver's IQ imbalance is corrected, it can be used to measure and compensate for any transmitter IQ imbalance.

12:00-13:00 Session 6C: Automotive FuSa Tolerance
Location: Zoom Room C
Exploiting Application Tolerance for Functional Safety

ABSTRACT. As safety critical systems become more prevalent, there is need to reduce the implementation overhead required to provide safety. Conventional design of such systems does not consider application behaviours, thereby resulting in pessimistic design since the safety provided is towards the worst case behaviour. In this paper, we analyze tolerances during different embedded threads in an application, and propose a new methodology for protection of critical threads. Two new application-based protection schemes are proposed. Experiments on two automotive applications (electric vehicle traction, on-board charger) indicate MIPS savings between 70% and 95% as compared to worst case protection in these applications.

Hierarchical Failure Modeling and Machine Learning Assisted Correction of Subsystem Failures in Autonomous Vehicles

ABSTRACT. Autonomous systems that rely on multiple interacting subsystems require a high degree of reliability and resilience to a wide range of failures in those subsystems. In this work we investigate the effects of electro-mechanical failures in the sensors and actuators of steer-by-wire and brake-by-wire subsystems of autonomous vehicles on subsystem and vehicle level performance. A machine learning assisted correction approach using Gaussian Processes to learn fault dynamics on-line is developed, and its efficacy is demonstrated under a variety of scenarios and fault models at the subsystem and vehicle levels.

Compositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation

ABSTRACT. This paper proposes a formal approach to fault propagation analysis for hardware/software systems. We consider soft errors by single event upsets (SEUs) which corrupt data in hardware registers and examine their effect on the software. Scalability of our approach results from combining an analysis at the binary and hardware level with an analysis of the high-level source code using Abstract Interpretation. Effectiveness and scalability of this method is demonstrated on an industry-oriented software system with over 100.000 lines of code.

12:00-13:00 Session 6D: Special Session: All About Silent Data Corruption in Data Centers
Location: Zoom Room D
Silent Data Corruptions at Scale
Cores that don’t count
A Software Solution for Managing Silicon Defects in Data Centers

ABSTRACT. Finding and removing faulty CPUs from data center fleets is an important task for maintaining the highest levels of quality. There are some rare CPU defects that only become visible when operating at a very large scale. Additionally, some of these defects only manifest as silent data errors which make them particularly difficult to identify. For years, Intel has worked with several large-scale customers developing testing tools to screen CPUs. These software tools help customers find and replace potentially faulty CPUs both in pre-deployment and during periodic fleet maintenance.

Industry awareness of this need for periodic maintenance to find faulty CPUs is rising. Cloud service providers, for example Google and Facebook, have published papers on this topic. To address periodic maintenance needs, Intel has made its tools publicly available, known as the Intel Data Center Diagnostic Tool. The details of this tool, recommendations on how to use it for periodic maintenance, and how it works will be discussed.

13:00-14:00Lunch Break (Social Time in Gather.Town)
14:00-15:00 Session P4: Challenges of 3rd party IPs to achieve Automotive Zero Defect quality and Functional Safety

The advent of autonomous driving as well as the switch towards electric cars are causing a continuous growth of the electronic content in modern vehicles. As a result, automotive semiconductor manufacturers are demanded to meet Zero Defect (ZD) quality level as well as Functional Safety (FuSa) requirements. Testing and stressing to screen out potential early life failures caused by extrinsic defects is crucial to ensure ZD quality. However, screening defects is only as good as the test and stress coverage enabled in the design. Design for ZD needs to be addressed at both IP level and SOC/SIP (system on chip/system in package) level. As the technology feature size keeps scaling down, the design complexity has increased exponentially. Driven by cost and time-to-market considerations, it has become more and more popular for automotive semiconductor suppliers to adopt the off-the-shelf 3rd party IPs on their SOC/SIPs. This, however, poses unique challenges on ZD testing and stressing due to the lack of automotive ZD stress/test requirements built in the 3rd party IPs as well as the lack of the detailed design knowledge of those IPs from the system integration point of view. Adding manufacturing test flow awareness to the DFT/stress guidelines followed by IP providers is not straightforward. Information about how transforming provided fault coverage achievements into actual test coverage is not part of the typical IP utilization guidelines. Consequently we have seen cases in which the 3rd -party IP were not tested or stressed sufficiently resulting in quality issues as well as cases in which the 3rd -party IPs were overstressed and caused qualification failures. Meanwhile, FuSa is usually considered at the system level, not at the IP level. Moreover, for different FuSa integrity levels, we may need different stress testing requirements. How to ensure the 3rd party IP designs meet FuSa requirements while achieving ZD quality in a systemic and holistic way has become a common but important challenge faced by the automotive semiconductor industry. It is important to clearly define the requirements for IP providers before the design starts and make sure they have the effectively access to all necessary inputs regarding to the ZD quality and FuSa objectives. In this panel, experts in this field will exchange their views and discuss possible solutions and remaining challenges on this important topic.

Organizer and Moderator: Chen He (NXP)

Panelists: Davide Appello (ST Microelectronics), Wim Dobbelaere (ON Semiconductor), Fei Su (Intel), Daniel Tille (Infineon), Jody Defazio (Synopsys), John Xu (Xscend Technology)

Location: Zoom Room A