ABSTRACT. This paper describes that the mature ADC testing method with a simple test system using the incoherent sampling and the standard algorithm of windowing and FFT with 4K-point data can measure the SINAD of our target 12-bit SAR ADC accurately by proper setting of the input and sampling frequencies, which is industry-friendly. We show the input sinusoidal signal and sampling clock frequency relationship for accurate testing of the ADC dynamic characteristics with an incoherent sampling method using a flat-top window. We have clarified the measured SINAD accuracy of the input signal frequency dependency for a fixed sampling frequency.

ABSTRACT. High Voltage Stress Test (HVST) is critical for screening out latent defects to ensure quality on automotive semiconductor devices. This paper describes a novel way to adaptively adjust HVST stress voltage based on real-time current measurement to ensure every part is stressed reliably at the highest possible voltage within the tester hardware current limit as well as with equivalent extrinsic defect coverage on FinFET technologies.

ABSTRACT. This paper presents 3.5Gsps MIPI C-PHY analog front end receiver circuit for Automatic Test Equipment. This circuit has two features. First, it is made entirely of off-the-shelf components. Second, it has powerful CTLE to compensate for transmission line loss. Since it does not use ASIC, it is possible to add functions at a low cost and in a short time. In the wafer test environment, the loss between the wafer and the receiving circuit is large. This CTLE can be fine-tuned and effectively eliminate the transmission line loss of the developed equipment.

ABSTRACT. The automotive industry sets high reliability standards for microcontroller (MCUs). To increase reliability, the automotive MCU manufacturers are looking for accurate performance screening. One of these performance screening mechanisms are functional path ring oscillators (RO). In this paper, a scalable and efficient method for creating functional path ring oscillators is presented. Implementation data demonstrate that functional path RO monitors show a significant advantage in area and power consumption over comparable performance screening methods.

ABSTRACT. Wafer map defect pattern recognition provides a visual way for root cause analysis. Specially, recognizing grid, including line and intersection point types, is a challenging problem for process and test engineers. Grid is a repeating defect pattern that appears in multiple wafers, so identifying such patterns helps to trace the root cause of defects for yield ramp up. In this paper, we propose a systematic methodology to search for hidden grid patterns in wafers. Experimental results show the proposed method can achieve 100% prediction accuracy for all grid types, and achieve 96.45% for all nine common wafer defect types.

ABSTRACT. Failing test debug is human-time-intensive, requiring domain experts to develop and execute fact-finding experiments. With the increasing size and complexity of modern circuits it is impossible for these few experts to support all required debug. To overcome this bottleneck to expertise we propose AAA, a rule-based expert system to perform the procedure of an expert performing failure debug, including dynamic creation/application of targeted debug tests, collection of on-tester failure results, and results interpretation for root-cause analysis. We demonstrate the system on industrial chips with scan-chain failures, showing that debug tasks that previously took hours can complete automatically in minutes.

ABSTRACT. Multisite testing tests multiple chips simultaneously. When implemented on a large scale (massive multisite), interference and coupling on the test hardware often affect test sites differently, introducing variations in site measurements. Making a reasonable assumption that each site introduces errors to test measurement, we model each test site’s measurement as a weak nonlinear function of the true chip measurement with systematic errors. We propose an algorithm to solve for these systematic errors using volume test data and calibrate test data. We apply the proposed method to simulated and real test volume data and confirm the accuracy of the method.

ABSTRACT. This paper proposes a DFT-based approach which reduces both shift and capture power during test by splitting the scan chains into segments that ideally only capture when new faults are detected. Unlike our previous work, here extra control bits are inserted in between the segments to determine whether a particular segment will capture. A significant advantage of this approach is that a standard ATPG tool is capable of automatically generating the control bits value without the need for successive post processing or modification for the tool. For the circuits we have studied, up to 37% power reduction can be achieved.

ABSTRACT. Existing work on securing test infrastructure is based on restricting or encrypting test access to sensitive information, such that secret information can not be accessed publicly. In this work we invalidate this assumption by showing that by having access to (small delay) test results on insensitive (public) outputs, we can still extract secret data. Using real hardware, we have performed attacks using results of delay testing on cryptographic circuits, and were able to retrieve the key with results of just two delay test patterns. The attack is resilient against variations and noise, as well as lower resolution delay testing results.

ABSTRACT. Hierarchical integrated scan provides many benefits for testing large custom ASIC designs. Physical implementation at full chip level however becomes very challenging as the number of blocks and the levels of hierarchy increase. Additionally, maintaining timing constraints at multiple levels of hierarchy can be very resource intensive. This paper presents a novel framework to overcome these challenges using full chip scan architectural innovation. Our data shows that framework provides significant improvements in terms of test coverage and design convergence time without any design quality loss, thus generating cost saving and accelerating time-to-market.

ABSTRACT. XORNet-based low power controller is a popular technique to reduce circuit transitions in scan-based testing. However, existing solutions just randomly form the XORNet for scan chain control, and it may result in sub-optimal solutions without any design guidance. In this paper, we propose a novel testability-aware low power controller with evolutionary learning. The XORNet generated from the proposed genetic algorithm (GA) enables adaptive control for scan chains according to their usages, thereby significantly improving XORNet encoding capacity, reducing the number of failure cases with ATPG and decreasing test data volume.

ABSTRACT. The safety demands for developing automotive applications require comprehensive analysis to evaluate potential random hardware failures. Due to the complexity, part of this analysis must be manually performed by experts, resulting in a process that is expensive, time-consuming, and prone to errors. This paper proposes an automated approach to classify faults overlooked by other technologies by identifying nodes that do not disrupt safety-critical functionalities. We validate the methodology on an Automotive CPU, following ISO26262 guidelines. Our approach improves the Diagnostic Coverage by 1.15%, increasing the Single Point Fault Metric (SPFM) to 97.3%, enabling ASIL C compliance without hardware redundancy.

ABSTRACT. The world of testing has been living a huge transformation pushed by constraints and requirements coming from a large variety of sources and applications. The need for higher accessibility, controllability and reuse led to solutions such as IEEE 1687 or P1687.1. All the while, these same features are raising security concerns. Standards usual approach of relying on Domain-Specific Languages has difficulty in handling such disparate and often conflicting needs, with the risk of a dangerous proliferation of custom and incompatible solutions. In this paper, we show how the usage of Callbacks, defined in P1687.1, can help solve this issue.

ABSTRACT. IEEE Std. 1687 networks are typically accessed via a dedicated test port, like IEEE Std. 1149.1. As not all integrated circuits have a dedicated test port, IEEE Std. P1687.1 explores how functional ports can be used. Challenges are to determine hardware in the component translating information between a functional port and an IEEE Std. 1687 network and to describe a protocol for the data transported over a functional interface. We present a solution to handle general IEEE Std. 1687 networks, which we implemented on an FPGA and evaluated on various benchmarks in respect to data overhead and the area usage.

ABSTRACT. This paper, reviews the latest topics being discussed by the IEEE 1687.1 working group, including showing how a taxonomy of IJTAG instructions supports the development of callbacks. It discusses how proto buffers can be used to help bridge the gap from a host controller, like an ATE, and to an IJTAG network. The approach leverages concept of RPCs (Remote Procedural Calls) and the integer bit vector (intbv) concept to support communications through interfaces and between subroutines handling retargeting and handling control of the interface. The techniques are applied to several examples, including I2C and IEEE 1149.7-like interface.

ABSTRACT. This paper investigates the harmonic distortion measurement of the operational amplifier by applying our proposed summing node method and shows that it can provide low-cost and high-accuracy testing at their mass production shipping stage. Our measurement results show that measurement accuracy as below as -130 dBc is possible without expensive test equipment such as an audio analyzer. We show by theory, simulations and experiments that the measurement accuracy of the summing node method is tolerable for the harmonics of the signal source which provides the sinusoidal input signal to the operational amplifier under test.

ABSTRACT. This paper proposes a methodology for automated test program verification for semiconductor test. A formalized test specification is extended by emulated device responses and expected test program results in an abstract format. This allows to create a high number of test sets based on a mutation testing approach without a physical device nor a test system. The results of an offline execution are compared against expected ones leading to a qualified assessment of the test program. The concept is proven by implementation of a special subset for a given test program.

ABSTRACT. Due to their simplicity, low power consumption and high-performance direct conversion transceivers are used in RF-front ends. Performance of the direct conversion receivers is susceptible to I/Q mismatch. We use an envelope detector to detect combined amplitudes of the I and Q signals and we use this information to iteratively correct for the receiver's IQ imbalance. The proposed method can be used in mission mode in the background to calibrate any deviations in performance. After the receiver's IQ imbalance is corrected, it can be used to measure and compensate for any transmitter IQ imbalance.

ABSTRACT. As safety critical systems become more prevalent, there is need to reduce the implementation overhead required to provide safety. Conventional design of such systems does not consider application behaviours, thereby resulting in pessimistic design since the safety provided is towards the worst case behaviour. In this paper, we analyze tolerances during different embedded threads in an application, and propose a new methodology for protection of critical threads. Two new application-based protection schemes are proposed. Experiments on two automotive applications (electric vehicle traction, on-board charger) indicate MIPS savings between 70% and 95% as compared to worst case protection in these applications.

ABSTRACT. Autonomous systems that rely on multiple interacting subsystems require a high degree of reliability and resilience to a wide range of failures in those subsystems. In this work we investigate the effects of electro-mechanical failures in the sensors and actuators of steer-by-wire and brake-by-wire subsystems of autonomous vehicles on subsystem and vehicle level performance. A machine learning assisted correction approach using Gaussian Processes to learn fault dynamics on-line is developed, and its efficacy is demonstrated under a variety of scenarios and fault models at the subsystem and vehicle levels.

ABSTRACT. This paper proposes a formal approach to fault propagation analysis for hardware/software systems. We consider soft errors by single event upsets (SEUs) which corrupt data in hardware registers and examine their effect on the software. Scalability of our approach results from combining an analysis at the binary and hardware level with an analysis of the high-level source code using Abstract Interpretation. Effectiveness and scalability of this method is demonstrated on an industry-oriented software system with over 100.000 lines of code.

ABSTRACT. Finding and removing faulty CPUs from data center fleets is an important task for maintaining the highest levels of quality. There are some rare CPU defects that only become visible when operating at a very large scale. Additionally, some of these defects only manifest as silent data errors which make them particularly difficult to identify. For years, Intel has worked with several large-scale customers developing testing tools to screen CPUs. These software tools help customers find and replace potentially faulty CPUs both in pre-deployment and during periodic fleet maintenance.

Industry awareness of this need for periodic maintenance to find faulty CPUs is rising. Cloud service providers, for example Google and Facebook, have published papers on this topic. To address periodic maintenance needs, Intel has made its tools publicly available, known as the Intel Data Center Diagnostic Tool. The details of this tool, recommendations on how to use it for periodic maintenance, and how it works will be discussed.