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09:00-09:30Coffee Break (Social Time in Gather.Town)
09:30-10:30 Session 3A: Security Hardware
Location: Zoom Room A
Impeccable Circuits III

ABSTRACT. As a recent fault-injection attack, SIFA defeats most of the known countermeasures. Although error-correcting codes have been shown effective against SIFA, they mainly require a large redundancy to correct a few bits. In this work, we propose a hybrid construction with the ability to detect and correct injected faults at the same time. We provide a general implementation methodology which guarantees the correction of up to $\mathbfit{t_c}$-bit faults and the detection of at most $\mathbfit{t_d}$ faulty bits. Exhaustive evaluation of our constructions, by the open-source fault diagnostic tool VerFI, indicates the success of our designs in achieving the desired goals.

A BIST-based Dynamic Obfuscation Scheme for Resilience against Removal and Oracle-guided Attacks
PRESENTER: Jonti Talukdar

ABSTRACT. BISTLock is a recently proposed logic locking technique that integrates a barrier FSM with the BIST controller. We demonstrate BISTLock’s vulnerability to removal attacks and develop countermeasures to make it resilient against removal and Oracle-guided attacks. Removal resilience is achieved through an input-signal scrambler. We demonstrate the scrambler’s vulnerability to SAT attack and present a reconfigurable LFSR-based dynamic authenticator that achieves SAT-resilience. We present security analysis against Oracle-free attacks like BMC-based sequential SAT and FSM deobfuscation attack. We evaluate the security strength of the proposed solution and show that hardware overhead is low for a broad set of benchmark circuits.

LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment
PRESENTER: M Sazadur Rahman

ABSTRACT. Logic locking is a promising solution to protect ICs against piracy and tampering. The manufacturing test of the logic-locked chip is challenging as the unlocking key is secret. The testing and activation processes of logic-locked chips follow tests after activation or test before activation. We first evaluate exiting test methods and propose LL-ATPG, a logic-locking-aware test method applying a set of valet keys based on a target test coverage. LL-ATPG achieves high test coverage without sharing the key. We also perform security analysis of LL-ATPG experimentally demonstrate that sharing the valet keys with the foundry keeps the security intact.

09:30-10:30 Session 3B: Wafer Map Classification II
Location: Zoom Room B
Triplet Convolutional Networks for Classifying Mixed-Type WBM Patterns with Noisy Labels
PRESENTER: Chenwei Liu

ABSTRACT. Wafer Bin Maps (WBM) frequently show various spatial failure patterns useful for identifying the root causes of yield issues. It is challenging to classify the failure patterns accurately, especially when there are mixed types on the same wafer. Here we propose a weakly supervised learning approach and use triplet CNN models to classify mixed-type failure patterns in WBMs. We train the models based on a real product dataset with only single-label annotations and demonstrate that such models could mitigate the imbalanced class distribution and learn efficiently from noisy labels to achieve superior performances over binary CNN models.

Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling

ABSTRACT. Previous studies on wafer map defect pattern recognition are based on supervised machine learning, where labeled wafer maps are used to train a model for automatic classification. However, there may exist misclassification in the labeled data, which makes it difficult to establish an accurate model. Furthermore, some defect patterns may not be defined. We propose a semi-supervised framework to deal with these problems. The approach is validated with TSMC 811K database, in which we are able to define four new defect pattern types. All defect types can be recognized with high accuracy.

MINiature Interactive Offset Networks (MINIONs) for Wafer Map Classification

ABSTRACT. We present a novel approach called MINiature Interactive Offset Networks (or MINIONs). We use wafer map classification as an application example. A Minion is trained with a specially-designed one-shot learning scheme. A collection of Minions can be used to patch a master model. Experiment results are provided to explain the potential areas Minions can help and unique benefits of the approach.

09:30-10:30 Session 3C: Special Session: Current Development in Test Standards

An update on a few of the test standards currently being developed or updated. Discussion that standards need to evolve to meet the changing needs of the industries that rely on them.

Location: Zoom Room C
Revisions to IEEE Std 1500, Standard Testability Method for Embedded Core-based Integrated Circuits
IEEE P1687.1: The Trouble with Transforms
Assisting board level connectivity test with IEEE Std 1581
09:30-10:30 Session 3D: ITC-India 2021 Top 3 Papers
Location: Zoom Room D
Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis (best paper award, ITC-India 2021)
PRESENTER: Aravinda Acharya

ABSTRACT. The test of digital circuits has benefitted greatly from the adoption of logical fault models and automatic test pattern generation (ATPG) tools targeting them. The cyclic process of defects in newer technology nodes being increasingly missed out by gross fault models and newer fault models being developed to better target them in silicon has continued, and EDA tools have evolved to provide new automation capabilities. This paper presents silicon results on one of Texas Instruments’ new safety critical products which show unique defect detection with patterns targeting newer fault models like small delay defects (SDD) and cell aware faults (CAF), and RAM Sequential (RAM-S) ATPG patterns for memory faults. The net defective parts per million (DPPM) recovered using these methods is 72. Based on these results, recommendations for coverage targets and the order in which these faults must be targeted are provided. The unique silicon fall-out data presented in this paper provides a strategy for very low (zero) DPPM test of digital systems-on-chips (SoCs) in advanced technology nodes.

Addressing High Speed Memory Interface Test Quality Gaps in Shared Bus Architecture (1st honorable mention paper award, ITC-India 2021)
PRESENTER: Wilson Pradeep

ABSTRACT. Recent trends in high performance SoCs (System-on-Chips) indicate a significant growth in memory content causing memory paths to be amongst the most critical paths in the designs. Hence, high quality memory interface tests are crucial in achieving low DPPM (defective parts per million) and better screening of parts. Shared bus interface is a typical memory architecture used in complex processor cores to enable memory testing along its true functional access path. In spite of that, certain gaps exist which limits covering all functional interfaces to memories in its entirety. In this paper, we propose a novel methodology to strategically identify specific high speed memory interfaces with test quality gaps and tactically target them through structural scan based tests along the longest path to enable screen for marginal defects. The proposed method deploys a composite slack based test method to achieve high test quality at a minimal test cost impact. Experimental results on a large design indicate significant reduction (67%) in the target fault set, which resulted in 65% reduction in test vectors (71% test time reduction) using the proposed schemes as compared to baseline methods used for structural memory sequential test.

A Novel Method to measure PLL Bandwidth in a 5G RF transceiver (2nd honorable mention paper award, ITC-India 2021)
PRESENTER: Pradeep Nair

ABSTRACT. Integrated PLLs are, nowadays, a part of all high-performance RF SoCs. This is required due to increasing system bandwidth requirement with every generation of wireless transceivers. The analog front-end converters (ADC and DACs) need to be clocked at higher clock rate. Some transceiver architectures involve analog mixers which also involve high frequency clock generation. Integrated On-Chip PLLs are needed for sampling clock or mixer clock generation for these systems. PLL uses a feedback control loop to lock the phase of the internal voltage-controlled oscillator with an incoming low frequency reference clock. The bandwidth of the loop filter used in the PLL is important to ensure the noise performance of PLL. Measuring the PLL bandwidth is not easy without extra DFT blocks and dedicated test points. If the RF transceiver has multiple analog PLLs, this can be difficult. This paper proposes a non-intrusive method to measure PLL bandwidth in RF transceivers.

10:30-11:00Coffee Break (Social Time in Gather.Town)
11:00-12:00Supporter/Exhibitor Presentations
12:00-13:00 Session 4A: Secure and Trusted Microelectronics
Location: Zoom Room A
Characterizing Corruptibility of Logic Locks using ATPG

ABSTRACT. The outsourcing of portions of the design chain has led to concern regarding the security of fabricated ICs. To mitigate these concerns, one method developed is logic locking. The development of different logic locking methods has influenced research in security evaluations, typically uncovering a secret key. In this paper, we propose that using the corruptibility of incorrect keys is an important metric. To measure corruptibility of incorrect keys on large circuits, we describe an ATPG-based method. Results from applying the method to various circuits demonstrate that this method is effective at measuring corruptibility for different locks applied to large circuits.

SymbA: Symbolic Execution at C-level for Hardware Trojan Activation
PRESENTER: Arash Vafaei

ABSTRACT. The state-of-the-art approaches to generate tests to activate Hardware Trojans. suffer from a lack of completeness and scalability. In this paper, we propose using Symbolic execution at the C/C++ level to activate malicious functionality hidden in RTL designs. Our approach is based on mapping RTL design to C-level and leveraging the existing powerful symbolic execution engines to generate tests. We map back the generated tests to RTL and check if the hidden Trojans have been activated. We show the efficiency of our proposed method by applying it to Trust-Hub benchmarks (e.g., AES).

(Invited) Security and Provisioning of Automotive IC’s through Test and Safety

ABSTRACT. Modern vehicles are increasingly-connected devices with growing volumes of electronic systems. This systemic complexity means that even an average vehicle design will include over 150 Electronic Control Unit (ECU)s which control not just infotainment and communications, but powertrain, safety and driving systems which all depend on an increasing volume and complexity of electronics. This means around 200 million lines of code. Automotive software and electronics is expanding at a CAGR of 7%, and automotive sales are expected to reach US$3,800 billion in the next decade, split approximately 50-50 between hardware and software & services, McKinsey & Company Automotive software and electronics 2030

To ensure the correct and safe operation of these complex systems requires not only functional safety checks for reliability issues caused by silicon defects and aging, but also functional monitoring to ensure functional safety, safety of the intended function and security are all addressed. Ensuring that chips are not compromised in manufacturing, in the supply chain, or during field use can be enabled by a Root of Trust (RoT) and other layered security mechanisms inside the chip. Cars designed this year, on the road perhaps in the year 2025, will need to have systems which stay up to date and which have to continue to be upgraded well into the 2030s. With a continued support for OTA for an expected minimum of 15 years.”

12:00-13:00 Session 4B: Failure Diagnosis
Location: Zoom Room B
Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization
PRESENTER: Cheng-Sian Kuo

ABSTRACT. Volume diagnosis and debug play a key role in identifying systematic test failures caused by manufacturing defectivity, design marginality, and test overkill. However, diagnosis tools often suffer from poor diagnosis resolution. In this paper, we propose techniques to improve diagnosis resolution by test failure clustering and reorganization. The effectiveness of our techniques is demonstrated on two industrial designs in cutting-edge process nodes and verified by targeted analysis and testing. The number of suspects is reduced by 3.1x and 575.2x on average. The proposed techniques can be implemented using existing commercial diagnosis tools with runtime overheads below 1%.

Relevant Signals and Devices for Failure Analysis of Analog and Mixed-signal Circuits

ABSTRACT. Finding critical nodes and devices inside a circuit is important to have a reliable and safe circuit. It is also a necessary information to successfully solve a failure analysis. This is a difficult task when dealing with analog and mixed signal circuits for safety applications. For complex designs, the list of signals that influences a selected output is not easy to be deduced. This paper proposes a solution to meet these needs. It is a method that is potentially opened to a broader application domain than failure analysis. The obtained results are encouraging and show the advantages of such approach.

Open-short Normalization Method for a Quick Defect Identification in Branched Traces with High-resolution Time-domain Reflectometry

ABSTRACT. Time-domain-reflectometry(TDR) utilizing electro-optical-sampling has a superior resolution and comprehensible impulse waveform, leading to a quick identification of the defect over a single trace. However, it is still challenging to identify a defect in multiple-branched trace with complex TDR waveforms. A defect unit TDR waveform consists of defect-dependent-reflection(DDR) contributed by the defect branch and defect-independent-reflection(DIR) contributed by other good branches. This work proposed an open-short-normalization(OSN) method to separate DIR and DDR from the defect unit TDR waveform. The defect can be easily identified from DDR like a single trace. The proposed method has been verified with both simulations and measurement results.

12:00-13:00 Session 4C: Test Enhancements
Location: Zoom Room C
On Reduction of Deterministic Test Pattern Sets
PRESENTER: Janusz Rajski

ABSTRACT. Test compaction and test data compression are key components of the post-production test as they reduce pattern counts, the resultant test data volume, test time, and the cost of testing. The paper describes a method to reduce the number of ATPG-produced test patterns to deliver compact test sets. It is working with a meaningful representation of test patterns using external and internal necessary assignments to determine small groups of potentially compatible faults. These faults are subsequently retargeted by the SAT-based ATPG producing a single test pattern for the entire group, thus making the resultant test set smaller in size.

Multi-Transition Fault Model (MTFM) ATPG patterns towards achieving 0 DPPB on AUTOMOTIVE designs
PRESENTER: Saidapet Ramesh

ABSTRACT. We detail a new ATPG fault model developed and deployed in production based of analysis of multiple test escapes that has also proven to be cost effective in reducing DPPB on automotive designs. MTFM based input stimuli comparison was completed on set of library cells between MTFM and traditional Cell-Aware UDFM based patterns and, it was confirmed that only MTFM patterns produced the required multi-transitions through the inputs of the targeted cell instances in multiple designs. Additionally, silicon feedback from MTFM unique failures helped address a systematic process issue in a NXP design contributing to increased design quality of design.

Analyzing and Mitigating Sensing Failures in Spintronic-based Computing in Memory
PRESENTER: Mahta Mayahinia

ABSTRACT. Computation in Memory (CiM) promises the efficiency improvement of data-intensive applications. STT-MRAM, as one of the front-runners in emerging resistive non-volatile memories, is a suitable candidate for the CiM realization. The smaller on/off ratio of resistance states makes CiM implementation challenging in this technology. This is exacerbated with asymmetrical process and temperature variations of the resistance states of Magnetic Tunnel Junction and CMOS components, resulting in erroneous CiM operations. Here, we perform a technology-aware statistical failure analysis of CiM operation and design optimal reference circuitry for CiM sensing to minimize the failure rate with respect to process and temperature variations.

12:00-13:00 Session 4D: ET1: Memory Testing Embedded Tutorial

This embedded tutorial is divided into three modules addressing various aspects of memory BIST. Modern chips can contain over a Gigabit of memory distributed over thousands of macros. These memories need to be thoroughly tested and repaired at manufacturing time and in-system and in increasing number of applications. The first module provides a comprehensive checklist of requirements for engineers responsible for the implementation and verification of memory BIST. Memory repair has become a necessary condition to obtain acceptable yields in advanced technologies. The second module explores the impact of memory repair on area and techniques to reduce this impact. Emerging memory technologies introduce new challenges for memory BIST. The third module introduces some of them such as fault modeling, repair and trimming related to embedded MRAM.

Location: Zoom Room D
Memory BIST requirements
Memory repair
Built-in self-test functions to mitigate eMRAM test challenges
13:00-14:00Lunch Break (Social Time in Gather.Town)
14:00-15:00 Session P3: Talk to the TTSC (Test Technology Standard Committee)

Rather than a traditional panel, this will be an interactive session in which the audience can ask questions of the Test Technology Standards Committee members, and even make requests and provide feedback and guidance. Likewise, the TTSC members will survey the audience.

Possible topics include:

• Do we have holes in any of our test standards?

• Do we have any idea how widely-used our standards are?

• How do we gauge adoption rates?

• How do we get feedback on the technical aspects of standards?

• Where should we use one standard instead of another? How do they fit together?

• Should there be an architecture board at the TTSC level to help make sure that things fit together?

• Can we create one unifying language for all the TTSC standards?

• Should we do a better job of promoting standards to encourage adoption?

• Should the TTSC take an active role in creating and maintaining examples? Do we need an application engineer per standard? Or is this the job of the EDA companies?

• How should a standard be supported? Can we keep the e-mail reflectors active and staffed?

• Is security something that we should tackle in a standard?

• What do the stakeholders and users and volunteers in the standards community want from TTSC, and what can TTSC do better?

Organizer: Mike Ricchetti

Moderator: Jeff Rearick

Panelists: Erik Jan Marinissen (IMEC), Adam Cron (Synopsys), Heiko Ehrenberg (Goepel USA), Yervant Zorian (Synopsys)

Location: Zoom Room A
14:00-15:30 Session Poster: Poster Session

Note all poster videos and authors are available for the full session time. Poster videos are available for viewing throughout the conference.

Location: Gather.Town
Understanding Tool Synthesis Behavior and Safe Finite State Machine Design

ABSTRACT. High-reliability design requires understanding synthesis tool behavior and best practices. Detection and protection against illegal states and transitions is important for critical Finite State Machines (FSMs) within high reliability applications. Single Event Upsets (SEUs) probability is increasing with decreasing circuit dimensions and voltage [1]. SEU handling must be analyzed post optimization to ensure designed protections are still functional. In this work the default behavior of three synthesis tools interacting with high reliability FSMs is discussed. Post-synthesis netlists of test FSMs are analyzed for optimization induced changes that affect reliability during a SEU. Best practices are proposed to curtail aggressive optimizers.

Generalized Insider Attack Detection Implementation using NetFlow Data for Distributed Test Range Networks
PRESENTER: Yash Samtani

ABSTRACT. Insider Attack Detection is a critical and challenging problem due to the lack of visibility into live networks and a lack of a standard feature set to distinguish between different attacks. Our approach is centered on using network data to identify attacks. Our work builds on unsupervised machine learning techniques such as One-Class SVM and bi-clustering as weak indicators of insider network attacks. We combine these techniques to limit the number of false positives to an acceptable level required for real-world deployments and we present a prototype implementation in Python and results using actual data sets.

FR4 could be better than Tachyon-100G for post-silicon validation on LVDS signaling

ABSTRACT. Post-silicon validation on LVDS signaling could be done on bench setup with PCB specially designed for the test device. The material selection for test board is crucial to ensure that the real performance of the silicon can be validated. FR4 is the common and low cost material while Tachyon-100G is used for high speed PCB. This paper presents the LVDS validation result tested at 3.2Gbps with comparison of FR4 and Tachyon-100G material. The validation results show that FR4 stripline could be better than Tachyon-100G coated microstrip.

Defect-Directed Stress Testing Using I-PAT Inline Defect Inspection Results

ABSTRACT. Inline defect screening methods are becoming increasingly common—especially for automotive applications. In addition to the base application of scrapping die with high levels of inline defectivity, there are many other potential applications in which this data can be used to inform downstream die disposition decisions. In this paper, we present case studies in which inline defect data is used to direct targeted stress testing (i.e., burn-in) at the die level.

Layout Informed Multiple Bit Upset Hardening of Finite State Machines

ABSTRACT. The efficiency of high-reliability design implementations can be improved by carefully considering post synthesis and layout induced risks. Single Event Upsets (SEUs) probability is increasing with decreasing circuit dimensions and voltage [1]. Multiple Bit Upset (MBU) risk, an increasing concern with modern node density, presents new mitigation tradeoffs which can be informed by the layout. In this work, Hamming 3 encoding for SEU protection is combined with targeted layout changes to reduce risk and impact of MBUs in critical registers without incurring additional encoding overhead.

Power-Aware ATPG Using Sign-Off Models

ABSTRACT. Power-aware ATPG has been a staple of the IC manufacturing community for many years. Relying on weighting functions to drive pattern generation has served the community well to help compose pattern sets that did not cause IR-drop during pattern application, lowering device yield. But larger reticle sizes, on-chip variation, and a focus on yield has led to more advanced methodologies. This poster illuminates a promising automation developed with MediaTek which combines the sign-off models from PrimePower with the fast calculation algorithms of TestMAX(TM) ATPG to generate fewer patterns with higher coverage which don’t exceed the IR-drop limits.

In-Field Embedded Sensing & PVT Monitoring for Increased Device Power and Performance Optimization

ABSTRACT. Embedded in-chip sensors and PVT monitors allow chip developers to not only test and understand the dynamic conditions of their devices during the design phase but also during chip production, system bring up and ultimately once the device is deployed in the field. This real time sensing and monitoring is a key component of the latest silicon lifecycle management platforms.

Jitter Injection with pre- and post- emphasis circuits

ABSTRACT. This work describes a way to inject jitter into the test signal stream of a SerDes. We take advantage of an existing circuit which natively move the edges of the Tx signal edges directly - the pre-emphasis and post-emphasis circuits. This side-step the difficult traditional methods of power noise or clock phase selection. The additional circuits (DFT) are all digital logic and can be synthesized. Both random and periodic jitter can be inserted with some small changes in the logic control to the emphasis circuits. We will also show some selective eye diagram plots to illustrate the results.

A Novel Fault Grading Technique to Establish RTL-ATPG Top-Off Coverage
PRESENTER: Pawini Mahajan

ABSTRACT. Performing test activities earlier in the design and product life-cycles (or shift-left) has become an industry standard. This poster will discuss a unique methodology of synthesis technology used in conjunction with functional fault grading simulation to shift verification left. This approach moves the fault-simulation process earlier in the design flow. Fault-simulating functional patterns on RTL, a correspondence to post-ATPG functional coverage is established, allowing the end-user to achieve a consistent and repeatable correlation between RTL and ATPG coverage numbers. This methodology was further evaluated on multiple designs and the flow showed a very high coverage prediction accuracy for Intel designs

Unified Test Flow for DFT Power, Performance & Area Optimization
PRESENTER: Surya Duggirala

ABSTRACT. The increasing amount of the DFT logic, needed to meet the testability goals of advanced integrated circuits (ICs), has a significant impact on ICs’ power, performance, and area (PPA). These designs require a new paradigm where DFT logic is tightly coupled to physical aware optimization and implementation to achieve an optimal PPA. This poster shows a test flow for such optimizations of the DFT logic and its cumulative PPA benefit on several industry designs.

A Multi-Threaded Single-Pass Diagnosis of Scan Chain Failures
PRESENTER: Emil Gizdarski

ABSTRACT. A runtime speedup is a key focus of improving diagnosis technology. This poster describes single-pass chain diagnosis algorithm that selects dynamically filing patterns and performs good machine simulation for all defective scan chains. As a result, the selected failing patterns are simulated once (single-pass diagnosis) and the pattern selection minimizes the number of potential defect locations after each simulation pass. The experimental results confirm that the proposed chain diagnosis algorithm increases the volume diagnosis throughput and consistently improves the quality of results vs a baseline algorithm. An average speedup was between 20X and 63X for six designs.

High Bandwidth Current Sourcing with the Howland Current Source

ABSTRACT. Semiconductor test continues to grow in complexity – requiring more instrument resources and increased test time. Certain devices like LED drivers are pushing the boundaries of tester capabilities – therefore, driving the need for new innovations. By implementing simple DIB circuitry, we can enhance the ETS-800 instruments and achieve a HI-Bandwidth current source with rise/fall times as low as 30nS. The current source has programmable amplitudes and rise/fall times – making it very versatile. Discussed in this paper is an overview of the circuit design elements, critical design parameters, and different test cases where this circuit may be applied.

Practical Methods to Test MIPI C-Phy Data Interfaces

ABSTRACT. MIPI C-Phy is an unusual interface. It is constructed of sets of 3 wire, 3 level trios encoding data. The receiving device mixes and matches the single ended wires to create an apparent 4 level at each of 3 differential receivers. It is different enough from usual non-return to zero binary data that usual ATE digital instrumentation does not readily support the standard nor comprehensively test the physical layer interface. This poster will present some practical principles for testing the receiver interface, some suggestions for supporting DFT, and some simple scalable circuits to provide at speed manufacturing test.

Utilizing IEEE Std 1687 for board level test
PRESENTER: Heiko Ehrenberg

ABSTRACT. This poster discusses the utilization of IEEE Std 1687 for board level test. We will point out a few specific ambiguities in the current version of IEEE Std 1687 that may result in different interpretation by various stakeholders (EDA tool vendor, test equipment tool vendor, test engineer / end user), potentially limiting the use of the standard for board level applications. This poster will elaborate on three examples of ambiguities, while advocating for issues such as these to be addressed in a potentially upcoming revision of IEEE Std. 1687.