ABSTRACT. The impact of electrical stress on the effects of total ionizing dose (TID) on graphene nano-disc non-volatile memory (GND-NVM) devices is investigated by X-ray irradiation with doses ranging from 50 to 1000 krad (Si). The electrical characteristics of the devices are measured at each dose step and are compared to those before X-ray exposure. Applying non-zero gate stress during irradiation significantly accelerates the degradation process, and the device fails with an unusable memory window at a TID dose of 500 krad (Si). The electric field in the surrounding oxides plays a key role in the observed degradation.

ABSTRACT. Spin-transfer torque (STT)-MRAM requires yield-aware design for hybrid magnetic-CMOS integration. In this paper, a novel cycle-sensing margin enhancement (CSME) scheme with pMOS assisted voltage-type sense amplifier (p-VSA) is proposed to alleviate imperfect process induced performance fluctuations. With iterated charging-discharging through non-volatile data path and reference path, read margin can be significantly improved thanks to enlarged sensing window. Simulation is performed using MTJ compact model and TSMC 28-nm process. Results show that ~14.1% read yield is realized at 50% tunnel magnetoresistance ratio (TMR), with 0.6V supply voltage comparing to conventional VSA.

ABSTRACT. This paper proposes a novel methodology to design high reliable STT-MRAM, with self-activated built-in-self-test (BIST) against aging/temperature-induced degradation. During sensing operation, Tunnelling magnetoresistance (TMR) is monitored, and real-time BIST is activated prior to permanent damage in Magnetic tunnel junction (MTJ) stack. To evaluate the feasibility of the test scheme, the proposed technique was involved in MRAM array implementation using 28-nm CMOS and 40-nm MTJ. HSPICE MOS Reliability Analysis (MOSRA) is used to evaluate the amount of electrical stress to the actual device aging degradation. Compared with previous periodical BIST method, the proposed self-triggered BIST saves ~31.1% cumulative power consumption over 12 years. And the proposed technique can improve reliability in the wear-out failure period.

ABSTRACT. The goal of this work is to demonstrate the feasibility and challenges with monitoring parameter stability of power semiconductors that are soldered into application relevant stress test hardware. This paper provides an overview of the test system developed for accelerated stress testing under application relevant test conditions. The authors provide an insight into the challenges associated with monitoring parameter stability within such a test system and describe the current solution. The general conclusion is that the presented system is capable to correctly monitoring device parameter stabilities and is capable of stressing SiC MOSFETs with accelerated application relevant test conditions.

ABSTRACT. To accurately determine the reliability of SRAMs, we propose a method to estimate the wearout parameters of FEOL TDDB using on-line data collected during operations. Errors in estimating lifetime model parameters are determined as a function of time, which are based on the available failure sample size. Systematic errors are also computed due to uncertainty in estimation of temperature and supply voltage during operations, as well as uncertainty in process parameters.

ABSTRACT. This paper focuses on the degradation at the wire bond contact with the metalized pad, and precisely its evolution with the power module aging. The goal is to highlight and understand the structural mechanisms occurring during the initiation and propagation of the cracks at the interface between the wire and metallization. In order to do so, accelerated power cycling tests with specific characterizations are carried out on special power modules. In addition, analysis of the interface wire-metallization are done with a numerical microscope and the EBSD (Electron Back-Scattered Diffraction) technique. As a result, an attempt to correlate the evolution of the degradation with that of the granular microstructure of the aluminium constituting the wire and metallization is proposed.

ABSTRACT. Photoemission associated with avalanche breakdown current of insulated gate bipolar transistor (IGBT) was observed using a multi-anode photomultiplier tube (PMT) with high time resolution of 20 ns. As PMT can detect very weak light, we could observe the photoemission even under applying a single pulse bias condition. The increase / decrease and movement of the light emission from the current filament were observed. It was also found that it changed every time the pulse was applied.

ABSTRACT. In this paper, we propose to study the thermal mapping evolution of the Insulated gate bipolar transistor (IGBT) emitter metallization after aging by thermoreflectance. Thermoreflectance measurements were done in static regime before and after aging by DC power cycling. The aim of this study is to observe the change in thermal behaviour at the cell level due to power cycling aging. Preliminary results indicate that pixel-by-pixel calibration eliminates artefact in reflectivity images and should allow a thermal calibration independently of the topography and chemical change of the metallization after cycling.

ABSTRACT. Attention has been paid to the next-generation IGBT toward CMOS compatible wafer processes, which can be driven by a 5-V logic level due to its low threshold gate voltage. This low threshold voltage makes the so-called shoot-through phenomena severer. This paper presents shoot-through protection for an inverter consisting of the next-generation IGBTs with gate impedance reduction, which reveals the criterion of the gate impedance with taking parasitic parameters of the inverter into account.

ABSTRACT. The main objective of this paper is to demonstrate the implementation of different dynamic stress test methods within a unified stress test apparatus by retaining most of the functional modules constant and merely change the DUT (Device Under Test) for a variety of power devices and stress patterns. A prototype has been constructed which is capable of implementing SC (Short Circuit) and UIS (Unclamped Inductive Switching), as well as DP (Double Pulse) testing for stressing power semiconductor devices of different voltage and current classes. Last but not least, a protection circuit has been incorporated to safely turn-off the power circuit in case of DUT failure.

ABSTRACT. In this paper, some issues are solved that are encountered if using the high-energy gamma radiation for the non-invasive characterization of carrier multiplication in commercial, packaged SiC power devices under pre-breakdown conditions. For this scope the soft gamma emission of Am241 (59.9 keV) is exploited, which provides higher signal generation and a more efficient collimation of the sensing beam than in the Co60 and Cs137 radioactive gamma sources used in a previous work. Carrier multiplication factors are measured in two different SiC power MOSFETs under different bias conditions and compared to the values obtained from the high-energy sources. Literature failure rate data for single event burnout (terrestrial cosmic radiation) as measured by neutron irradiation are correlated to the multiplication factors as measured by the Am241 source. Finally, preliminary directions are issued to use of the multiplication factor as an indicator to define the bias derating factor for the devices under operation conditions

ABSTRACT. Ga2O3 is an emerging ultra-wide-bandgap semiconductor material offering superior power material limits over Si, SiC, and GaN as well as the availability of large-diameter wafers growing from its own melt. However, Ga2O3 device performance may be limited by the relatively poor thermal conductivity of the material.

In this paper, we investigate the behavior of Ga2O3 Schottky diodes in the condition of forward current surge to explore their electro-thermal ruggedness and the related thermal management. An analytical electro-thermal device model is calibrated with experimental devices and TCAD simulations. Then this device model is incorporated into a SPICE electro-thermal network model, which is used to simulate the device temperature rise during the surge transient, considering various device and packaging configurations (i.e. various chip thicknesses and chip orientations).

It is found that providing heat is removed from the junction side, a Ga2O3 Schottky diode offers a robustness to surge current exceeding that of a SiC Schottky diode. The low thermal conductivity of Ga2O3 is found to be overcome by the enhanced heat extraction from junction-side cooling as well as the the intrinsically small temperature dependence of the on-resistance (and conduction loss) of Ga2O3 devices.

ABSTRACT. A non-invasive temperature sensing method for high-voltage SiC MOSFET chips based on the measurement of light emission during reverse conduction is proposed. The method is based on a fast, inexpensive, simple circuit. The effectiveness of the circuit has been confirmed by the analysis of the transient light emission of intrinsic body diode in a commercial SiC power module.

ABSTRACT. This paper proposes the detailed analysis of the short-circuit failure mechanism of a particular class of silicon carbide (SiC) power MOSFETs, exhibiting a safe fail-to-open-circuit (also named soft) type signature. The results based on extensive experimental testing, including both functional and structural characterisation of the transistors, specifically devised to bring along gradual degradation and progressive damage accumulation. It is shown that the soft failure feature is associated with degradation and eventual partial shorting of the gate-source structure, Moreover, partial recovery is also observed on degraded components, which can be forced and to some extent controlled by applying specific biasing in off-line conditions, making it a new realistic option for deployment in the application to yield enhanced system level robustness and hopping-home operational mode capability, of great importance in a number of reliability critical domains, such as transportation and energy distribution.

ABSTRACT. "A class of SiC power MOSFETs have recently been found to feature a fail-to-open failure mode, with the device going into permanent automatic shut-down mode. Such behavior is extremely interesting for the application. In the frequent case of power converters designed with parallel connected devices or multi-chip power modules, a fail-to-open implies loss of a single device, but does not compromise the possibility to still operate the system, even if at reduced power levels (hopping home modality). More recently, it has also been shown that in the case of progressive moderate damage accumulation, the degradation of the device characteristics can be recovered to a stable state by ad-hoc biasing of the device itself. This talk will review the degradation and failure mechanisms leading to fail-to-open signature, will present evidence of stable device recovery capability and present ideas and solutions to make use of such feature in the application. The results are substantiated by extensive functional and structural device characterization"

ABSTRACT. In this work a new concept of liquid cold plate for high power press-pack assemblies is investigated. In industrial applications it is very important to reduce the volume and weight of the device-heatsink stack, in order to improve reliability and availability of the whole system. The potential of aluminum additive manufacturing technology is investigated by means of coupled thermal fluid-dynamic 3D modelling in order to get the best trade-off between thickness, thermal performance, and pressure drop. Careful tuning of the numerical model was conducted by means of thermal characterization of a prototype with a test bench properly built. The numerical model was exploited to explore different solutions for the cold plate internal layout, such as with classical coils, deformed coils, or specific textures impossible with standard mechanical machining. Early results are shown to demonstrate the usefulness of our coupled thermal fluid-dynamic approach. Mechanical analysis was taken into account as well, and will be shown in the full paper.

ABSTRACT. In this paper, an experimental and numerical study of the electrical ruggedness of double-sided cooled power modules is presented. In particular, the analyses are focused on the role of the spacing between substrates, which are commonly kept distant to avoid electrical failures. To this aim, many samples of such modules were manufactured and tested. FEM electrostatic simulations were performed in COMSOL Multiphysics to provide an explanation of the counterintuitive experimental findings.

ABSTRACT. The electrical contact resistance (ECR) of connectors fluctuates periodically under vibration stress. However, a theoretical model used to explain the dynamic characteristics of ECR has not been fully proposed. The dynamic characteristics of ECR are presented after an analysis of the measured results. Moreover, according to the Greenwood-Williamson model for elastic contact and the equivalent spring model for random rough surfaces, the change in the contact pressure of electrical connectors during vibration is studied. On this basis, combining with the Holm electrical contact theory, a dynamic model of ECR under vibration conditions is established. The model can theoretically explain the phenomena of ECR found in the experiments. A good correlation between experimental and predicted ECR fluctuation is achieved.

ABSTRACT. The aim of this study is to gain a better understanding of the behaviour of sintered silver layers for e.g. power electronic applications in corrosive environments. It explicitly deals with the influence of corrosion products on the mechanical properties using Nanoindentation measurements. In addition to these measurements, analytical investigations and porosity analyses are performed. Existing studies mainly deal with the investigation of unaged sintered silver layers or the influence of thermomechanical ageing on the mechanical properties. In contrast, this study focuses on the investigation of the influence of moisture on the mechanical properties of sintered silver. The results show that an increased Young’s modulus can be detected by Nanoindentation measurements on corrosion-stressed sintered silver. In addition, increased indentation hardness is also determined. Besides the already known influences on the Young's modulus, a significant influence on the corrosion pattern of the sintered silver layers can be shown. The results are discussed with regard to a filled pore system of the samples.

ABSTRACT. This study deals with the reliability of a new power embedded PCB (printed circuit board) concept highly integrated into an electrical machine for aeronautical and automotive applications. The first part describes the assembly topology and presents the main stages of module manufacturing using the silver sintering connection and the pre-impregnated composite fibers lamination. A second part shows the results of electrical and mechanical tests realized on this module. The purpose is to validate the design of a new assembly technology which offers all the reliability conditions that are the manufacturing time optimization, the reduction of the process steps, the module functionality and the feasibility.

ABSTRACT. Thermal management is a key point of power converters development because it affects their performance defining heat flow and temperature cycling. Even if cooling technologies for electronics have been a research topic since the birth of power electronics, in the last decade the number of publications related to this field has grown significantly. This is because thermal management, with the power density increasing and the high reliability required by many applications, cannot be the same of old systems. Then, here it will be presented an overview of cooling techniques for power electronics and the numerical modeling related to thermal management problems. It will be shown different numerical analysis based on multiphysics Finite Element Analysis and compact thermal models, such as the Foster and Cauer networks, which can be useful for SPICE-like electro-thermal simulations. The aim is to show how multiphysics simulations can be used for the cooling system design or for reliability studies.

ABSTRACT. The elucidation of core structure of Shockley partial dislocations arising from the dissociation of a-type dislocations in GaN heterostructures, and the study of their behaviour, under electron beam irradiation were the aims of this work. Aberration-corrected high resolution transmission electron microscopy (HRTEM) observations, geometrical phase analysis, image simulations, and density functional theory (DFT) calculations were employed to reveal the dislocation core configurations. Direct visualization of bright atomic columns in the dislocation cores was achieved under optimum imaging conditions allowing for the determination of the core structures. The influence of e-beam irradiation on the partial dislocation mobility in correlation to its core structure was explicitly investigated for a shrinking reaction leading to the merging of a pair of 30o partial dislocations. The role of point defects in the promotion of the re-formation of the perfect dislocation from the pair of partials was considered. Finally, the impact of this reaction on device performance was considered.

ABSTRACT. Carrier distributions in the floating gate and channel structures with sizes <10 [nm] of 3D Flash memory cells were clearly measured by using scanning nonlinear dielectric microscopy (SNDM). Using super-sharp diamond tips with radius of <5 nm to achieve the supreme spatial resolution, we successfully obtained SNDM signals of floating gate in high contrast to the background. We deduced the minimum spatial resolution and confirmed that our SNDM exhibits the spatial resolution as good as < 1.9 [nm]. Furthermore, we seized a clear evidence that the diffusion length differences of the n-type impurity among the channels are < 21 [nm]. These mean that we successfully established an exceptionally effective method for the device performance optimization and the device failure analysis.

ABSTRACT. Circuit Edit (CE) techniques have been used for debug, characterization and prototyping, etc. in the IC industry. CE jobs have become more complex to accomplish since the adaption of FinFET technology. Backside Si trenching in part of CE process is required to have the highest success rate because once punched through Si trench floor, the IC would lose functionality. Therefore, it needs reliable and quantitative end-pointing technique. The coaxial FIB column technology [1] allows to obtain optical image simultaneously, so optical interference fringes can be sued to estimate remaining of Si thickness, to monitor planarity of trench floor and to obtain trenching end-point. We introduce reliable end-pointing technique on backside Si trenching.

ABSTRACT. This paper discusses Cu-filled Through Silicon Via (TSV) failure analysis cases where known FA methods were used in an alternative way. Results are shown using magnetic field imaging (MFI) on a cross-sectioned chip to detect a liner breakdown position, and MFI and Light Induced Capacitance Alteration (LICA) to detect opens in TSV daisy chains.

ABSTRACT. The goal of this work is to propose a new flow that integrates the analog and mixed signal simulation of the circuits to reproduce the EMMI, as support for the fault localization process. We will explore the emission typologies of the transistors focusing the attention on the DMOS structure. The first experimental results show the benefits of this approach.

ABSTRACT. The present paper studies the use of isopropyl alcohol and fluorocarbon liquids as coupling fluids for acoustic microscopy non-destructive testing on electronic flight components, for which sometimes the standard coupling liquid water should be avoided in order to minimize sample contamination. The ultrasound velocities of three different fluorocarbon liquids are measured, and comparative failure analysis images on various electronics components are obtained by using five different coupling liquids.

ABSTRACT. To accurately study positive bias temperature instability (PBTI) in nanoscale SiON nMOS transistors we make use of the time-dependent defect spectroscopy (TDDS) and examine the device performance degradation at the single-defect level. Contrary to what is visible in large-area devices, our investigations clearly reveal charge trapping at both electron and hole traps contribute to the overall drift of the threshold voltage in these devices. Even though only electron trapping is typically considered for PBTI we observe that hole traps account for around 20% of the total threshold voltage drift. To evaluate the impact of single-defects on the device performance we characterize the charge trapping kinetics of a number of defects, which can be explained employing a two-state defect model. In our approach we consider charge trapping due to defect/channel and defect/poly-gate interactions for the defects. From the extracted trap levels and trap depths we conclude that hole traps reside in the middle of the insulator while electron traps are located closer to the SiON/Si interface. Finally, the extracted trap parameters are fully consistent with defect candidates from DFT calculations.

ABSTRACT. Abstract - In this work, we propose a reliability analysis targeting the evaluation of the suitability of a Phase-Change Memory (PCM) device for Storage Class Memory applications. Thanks to the analysis of programming and endurance characteristics in single devices and 4kb arrays we compare two different GeTe and GeSbTe (αGST) based PCM. The evolution of the phase-change material along cycling is triggered by the analysis of subthreshold characteristics and analytical equations based on experimental data for the description of electrical parameters evolution are given. An extrapolation method to evaluate endurance at more than 10^9 cycles required for SCM is described and applied, showing the intrinsic high endurance capability and suitability for SCM applications of αGST wrt GeTe.

ABSTRACT. P- and N- channel Extended Drain MOSFETs (EDMOS) are analyzed through its sensitivity to Hot-Carrier (HC) degradation using accelerated lifetime technique. We have improved the extraction of series-resistance (dRSD) with a 2nd order mobility modeling applied to HC degradation as a function of stressing VGS from VGS= 0 to VGmax. This allows to determine the worst-case of lifetime dependence in relation to the damage in the drift zone where breakdown sensitivity is found to be intimately bound up with the hot-hole (HH) injection efficiency in N-EDMOS while P-EDMOS exhibits a larger security margin.

ABSTRACT. The single event upset (SEU) for monolithic 3-D (M3D) 6T SRAM with different channel sizes was investigated based on a 22 nm fully-depleted silicon-on-insulator (FD-SOI) technology over a temperature range of 210 K to 390 K. Compared with planar SRAM, M3D SRAM exhibits higher SEU sensitivity and increasing the transistor size does not work in mitigating the SEU in M3D. It is demonstrated that the SEU sensitivity of M3D 6T SRAM increases with temperature after the incident of 127I while it decreases after the striking of 209Bi. The reason can primarily be explained by the different influence ranges of striking heavy ions, which affects the ionized charge transport.

ABSTRACT. The increased number of transistors associated with the reduced distance from the transistors and the metal layers raises the maximum chip temperature in the metal lines in each new technology. The high temperature of the chip accelerates the electromigration, increase the resistance of the metal lines, and as a consequence, affect the circuit performance and reliability. The temperature of a block in a chip depends on its power consumption, as also on the power density of the adjacent blocks. Consequently, the floorplan for a given chip can affect the temperature of the chip considerably. In this work, we propose a methodology to evaluate the critical blocks in an integrated circuit based on the temperature and evaluate circuits designed in 45 nm technology. The evaluated circuits have blocks with the temperature above 350 K, and a strategical floorplan is required, as the elevated temperature increases the number of critical lines of the adjacent blocks. The methodology allows the chip floorplanning based on the temperature effects in the resistance increase of the lines due to electromigration. The reduction of the probability of the blocks to failure, and then operates below the maximum temperature supported by the lines can guarantee the circuit reliability.

ABSTRACT. The successive oxide failure statistics theory that arises from the clustering model is used for modelling the ordered time-to-breakdown distributions of Al2O3/HfO2-based nanolaminates. This gate dielectric stack in MIS structures is intended to combine a high injection barrier material (Al2O3) with a high-K material (HfO2). This report demonstrates that the theory of uncorrelated events succesfully describes the breakdown statistics up to the order 15th and allows identifying the origin of the deviation from the standard Weibull model occurring at the high percentiles in the large spread exhibited by the initial leakage current.

ABSTRACT. Aiming at the inaccurate problems of lifetime prediction and reliability evaluation of 3D TLC NAND flash memory, a method to evaluate the remaining lifetime and the reliability of flash memory based on the threshold voltage distribution is proposed. In order to analyze the impact on Program/Erase (P/E) cycles on the flash memory from the perspective of voltage distribution, a complete distribution curve of threshold voltage is drawn from the construction of a reasonable mathematical model. The P/E cycles has always been regarded as an important indicator to evaluate the reliability and remaining lifetime of flash memory. Currently, most evaluations of flash memory reliability and lifetime expectancy are based on the relationship between the P/E cycles and the raw bit error rate. The bit error distribution of TLC flash memory is not uniform, and there is a clear centralized distribution phenomenon, which will easily exceed the controller's error correction capability, and then affect the reliability of the flash memory. Therefore, it is not accurate to analyze the reliability of the flash memory only based on the bit error rate. Analyzing the reliability and lifetime expectancy of flash memory from the perspective of threshold voltage is a more reliable and more essential method, however, there is almost no literature to do this research. In order to analyze the impact on P/E cycles on 3D TLC NAND flash memory from the perspective of threshold voltage distribution, two methods to draw the threshold voltage distribution curve and compare them are given below. First, we obtain the origin test data from our hardware-software co-design experimental platform for 3D NAND flash. Fig. 1 shows a photograph of our 3D NAND flash experimental platform. This experimental platform primarily consists of the processor (Zynq) and a NAND flash array. We select MT29F256G08EBHAF, which is a 3D TLC NAND flash from Micron Inc.. In the first method, the read offset function of the flash memory is used to control 7 read reference voltages so that the "voltage window" of the 8 cell states of the flash memory is controlled.Therefore, the threshold voltage distribution functions of all states of the TLC flash are obtained. Then, a complete distribution model of threshold voltage is drawn through a series of operations such as misalignment, model fitting, and state merging(see Fig. 2). In the second method, by virtue of the large amount of obtained flash memory data, the data status of the cells that have read errors are counted (see Fig. 3). In order to calculate an overlapping area of the adjacent status, the counts of jump direction of the error bits is given. Finally, a reasonable distribution model for statistic is fitted (see Fig. 4). Two methods of drawing the threshold voltage distribution are investigated. A completed distribution of the threshold voltage in almost all voltage ranges is obtained in the first method. In the second method, a smaller amount of calculation is done compared to the first method. While the distribution curve can accurately restore the overlapping area of adjacent status. After plotting the initial distribution of threshold voltage, the continuous P/E operations on the flash memory are performed. At 100, 500, 1000, 2000, 5000, and 10,000 P/E cycles, these two methods are used to draw the distribution curve of threshold voltage. The distribution curve of threshold voltage for 100~10,000 P/E cycles is drawn by the read offset method of 3D TLC NAND flash memory (see Fig. 5(a)). Three observations are presented from this figure. (1) The threshold voltage gradually shifts to the left as the number of P/E cycles increases. (2) The divergence of the threshold voltage distribution increases. (3) Bit errors mostly occur in P3 and P4 states. The overlapping area method was used to process the same data and draw a distribution curve (see Fig. 5(b)). Investigating the Figure 5, the same conclusions are drawn as Figure. 5(a). Combining these two methods, the P/E cycles-overlap area conversion formula is obtained. According to this formula, the lifetime prediction of the flash memory can be performed. And by comparing the overlapping area of adjacent areas, the strength of the error correction algorithm required for the corresponding page can be obtained. Compared with the conventional used curve of P/E cycles-error rate, it reflects the most concentrated part of the flash memory error rate and makes lifetime prediction more accurate.

ABSTRACT. In this paper, we are concerned with the reliability models and analysis methods for the case where catastrophic and degradation failure modes are considered simultaneously. First, the existing degradation models and analysis methods are reviewed and classified. In particular, the existing methods for analyzing degradation data are classified into the “horizontal axis” and “vertical axis” methods. Second, based on the above degradation models and analysis methods, a systematic procedure for simultaneously analyzing catastrophic failure times and degradation measurement data are presented. Finally, using the data in Huang and Askin [1], comparative analysis results are presented with respect to the direction of analysis (i.e., horizontal versus vertical)

ABSTRACT. This paper is intended to propose a reliability evaluation method for products with high-reliability, long-life, small samples and multi-performance degradation. The Wiener process is used to model the degradation of a single performance parameter of the product to obtain its reliability evaluation model, since this can effectively describe the randomness of the product performance degradation process. Afterward, the Copula function is used to model the degradation of multiple performance parameters of the product, and a comprehensive determination method of the Copula function is proposed which can more accurately and effectively describe the coupled competition relationship of multi-performance degradation. Finally, the reliability evaluation of an insulated gate bipolar transistor is carried out, and the evaluation results are compared with the evaluation results of a single performance parameter, multiple independent performance parameters, and the actual case. The results show that the method proposed is more accurate and more applicable than traditional methods.

ABSTRACT. The accuracy of accelerated lifetime tests may vary due to the choice of test conditions, which presents a problem in interpreting results. Furthermore, testing is generally performed on test structures which are simplified compared to circuits and systems. To better understand actual usage conditions, we use 14nm FinFET ring oscillator circuits instead as the test vehicle for accelerated testing, focused on detecting front-end time dependent dielectric breakdown. We investigate factors for minimizing errors in lifetime estimation, such as effects of sample size at various test points for different testing times and numbers of stages.

ABSTRACT. Abstract –The life-cycle reliability of high-power DC electromagnetic devices due to multi-source heterogeneous uncer-tainties in the design, manufacturing, loads, degradation and cumulative damages has become increasingly prominent, life-cycle reliability optimization has attracted extensive attention. The design optimization strategy based on reliability, which combines the static/time-independent hypothesis and random theory, is inapplicable to life-cycle design optimiza-tion. Therefore, a time-dependent uncertainty analysis and life-cycle quality reliability optimization method are proposed in this study. Based on the information entropy transformation method, the fuzzy uncertainty is transformed into a proba-bility density function of equivalent random variables, and intervals for the random variables are determined in the stand-ard normal space. In this way, the heterogeneous uncertainty is unified as an interval type. Moreover, the time-dependent characteristics of the uncertainty parameters are transformed into a time-dependent of the characteristics through ellip-soidal model process. A life-cycle expression method based on an orthonormal basis is proposed to form a life-cycle time-dependent non-probabilistic convex model process. Therefore, the analytical expression of out-crossing rate in which there are many non-probabilistic convex model process parameters are derived and the corresponding upper and lower bounds of out-crossing rate can be obtained. Then, a life-cycle reliability design optimization model is constructed and the optimal solution is determined from intelligence algorithm. The effectiveness of proposed method was verified by a high-power DC electromagnetic relay in renewable energy systems.

ABSTRACT. With the improvement of manufacturing technology and the use of multi-level technology, the amount of charge stored in a flash memory cell decreases, the number of bits stored in each cell increases, the threshold voltage window becomes smaller. Therefore, it is more vulnerable to external interference to cause the overlap of threshold voltages between adjacent states, which makes it difficult to determine the logical value of cell, resulting in the decline of NAND flash memory reliability. Exploring and modelling the threshold voltage distribution of NAND flash and its changes due to various factors can help us to understand how the raw bit error occurs, and design an efficient mechanism to improve the reliability of flash memory. In this paper, we obtain the origin test data from our hardware-software co-design experimental platform for 3D NAND flash. Fig. 1 shows a photograph of our 3D NAND flash experimental platform. This experimental platform primarily consists of the processor (Zynq) and a NAND flash array. We select MT29F256G08EBHAF, which is a 3D TLC NAND flash from Micron Inc.. The experimental flash chip provided the READ OFFSET function which can offset the read reference voltage to obtain the threshold voltage distribution functions of each state. After that, a complete threshold voltage distribution can be drawn through misalignment and state merging. Based on the platform, we tested the advantages and disadvantages of two statistical methods of threshold voltage, and then used the better one to explore the threshold voltage distribution when programming different test sets into the block. 1. TLC flash has 8 storage states with a read reference voltage between two adjacent states, as shown in Fig. 2. In this paper, we call the pages affected by the offset read reference voltage as the affected pages. It can be seen that no matter what data is written, such as the sequence of full 0 or full 1 bits (see Fig. 3), or the random sequence in Fig. 4, the threshold voltage distribution obtained by only counting the bits error of affected page is the same as that obtained by counting the bits error of a group of shared pages. While only counting the affected page can save two thirds of the time. In our experiment, if only the bits error of affected pages were counted, the platform would cost 662021658 μs, while 1986083873 μs is needed for the all state statistics. 2. Due to the severe inter-cell interference in NAND flash, writing different test sets will lead to different threshold voltage distributions. When cells on the same byte line are written to the same data but cells on adjacent byte lines are written differently, the flip rate between P3 state and P4 state is the highest. Figure 5 shows the threshold voltage distribution when the cell state of adjacent word line is fixed, while Figure 6 shows the cell state of adjacent word line when it is random. It can be seen that when there is only interference between the word lines, most errors are caused by the LSB (Least Significant Bit) flip. When cells on adjacent bit lines are programmed into different data, and cells on the same bit line are written into the same one, it can be observed in Fig. 7 that the threshold voltage distribution of each state is more concentrated than when the cells in a word line store the same data. When the cells on adjacent word lines and adjacent bit lines are written with different data, the threshold voltage distributions of the three storage states whose LSB bit stores ‘1’ are the same when different data is written into the adjacent word lines. And the threshold voltage distribution of the four states with the LSB bit of ‘0’ shifts to the right, so that their threshold voltages are almost within the voltage window separated by the read reference voltage, thereby reducing the error rate. To sum up, this paper puts forward a statistical method of threshold voltage distribution that only counts the bits error of affected page, which can shorten the statistical time by two thirds while ensuring the accuracy. Using this method, we explore the threshold voltage distribution of three different data sets. And finally find that when interference mainly comes from adjacent word lines, the LSB flip will occur. When there is programming interference between the adjacent bit lines of the same word line, the threshold voltage distribution of each state will be more concentrated.. When programming interference exists between the adjacent word lines and the adjacent bit lines, the threshold voltage distribution of the cells with the LSB of ‘0’will shift to the right.

ABSTRACT. A novel accelerated test method has been developed and applied to estimate the lifetime of system-level electronic devices that bear more than one potential failure mechanisms. Firstly, thermal cyclic tests with conditions of temperature extremums and cyclic impact stress are designed to stimulate multiple failures simultaneously. Then, improvements are made in several aspects such as the lifetime distribution of the product, underlying life-stress relationship, and the temperature dependence of the basic acceleration model. Afterward, a comparison of the acceleration model between the proposed and traditional method is conducted by simulation, the results indicate that the proposed model has an advantage in reflecting the failure mechanisms which are sensitive to the low-temperature condition. Finally, real accelerated tests are employed on the custom-circuit samples and the data analysis shows that our method can effectively stimulate multiple failure mechanisms of electronic devices while ensuring the accuracy of the reliability and lifetime assessment.

ABSTRACT. This paper proposes a new scheme to improve the reliability and throughput of ultralow-voltage static random access memory (SRAM). The proposed scheme utilizes an error detecting sense amplifier (ED-SA) to constraint SRAM access timing, which combines timing error detection and correction. ED-SA applies different threshold transistors into the input terminals and regulates input offsets (Voffset) to the different polarity. By this way, the swing of BLs will be enhanced by one of the input offsets and its output will judge the other’s correctness. Simulation results in TSMC 28nm CMOS process design kits show that the proposed scheme has a better reliability and achieves 2.49x throughput improvement compared with conventional ultralow voltage SRAMs.

ABSTRACT. NAND flash memory is widely employed for its inherent advantages, such as high storage density, high reliability, low power consumption, and shock resistance. 3D NAND flash technology brings some new reliability challenges due to the inter-layer differences caused by the stacking process. The reliability community has made significant efforts to study flash memory management algorithms to reduce the reliability loss of storage media. In view of this, it is essential to develop an efficient and accurate experimental platform for NAND flash memory management algorithms. In order to obtain the complete endurance test data of the flash memory chip and study the change of the relevant physical quantities in the lifetime cycle of the flash memory, this research designs a experimental platform that supports multiple packages and various types of NAND flash memory chips, conducts reliability index collection, and studies a newly discovered reliability problem of 3D NAND Flash memory. We obtain the original test data from our experimental platform for 3D NAND flash memory. Figure 1 shows a photograph of our 3D NAND flash experimental platform. The FPGA controller model used in this hardware platform is EP4CE15E22C8, which is an Altera FPGA. The selected NAND flash memory chip is MT29F64G08CBCGB, which is a 3D MLC NAND flash from Micron Inc. E2PROM is utilized to record experimental information. 100M Ethernet interface is used to communicate between the hardware platform and the host. The host interactive interface is built on LabVIEW. We find that performing continuous read operations on an idle 3D NAND flash does not get a stable number of error bits, which show a clear difference from the situation of 2D NAND flash. There will be a significant decrease in the number of error bits retrieved after the first read, and then it will gradually stabilize (as shown in Fig. 2). Therefore, it is inappropriate to consider that the data obtained by performing only one read operation is valid. We study the characteristics and countermeasures of this phenomenon from the following three aspects. First, we find that the drop in the number of error bits occurred a few seconds after the first read operation. After performing the first read on an idle flash and wait for 0, 10, 30, and 60 seconds, we find that the number of error bits requires fewer reads to stabilize (as shown in Fig. 3). In view of this, the measures we have taken to deal with this phenomenon are to perform the first read operation and wait for a few seconds before thinking that the read data is reliable, or perform enough reads operation until the number of error bits obtained is stable. Second, if continuous block reads are performed immediately after the program operation, the read data will be unstable (as shown in Fig. 4).The number of error bits is also lower than that retrieved when the read data is stable. It takes a few minutes for reading data to be stable. In addition, a significant decrease in the number of error bits is also reported after the first read even in this case. Third, to study the effect of P/E cycles on this phenomenon,we obtain 40 sets of Raw Bit Error Rate (RBER) from continuous block reads after different P/E cycles, ranging from 100 to 10,000 (as shown in Fig.5). We find that within all the lifetime of the flash memory this phenomenon exists, and more P/E cycles leads to longer time for the data to stabilize after the first read. Through the above, we also measure the endurance of the chip. The relationship between the RBER and P/E cycles is given in Figure 6. The RBER range is from the level of 10-5 to 10-4. The reliable endurance limit is 10,000 P/E cycles, which is 5 times the endurance mentioned in the chip datasheet. In addition, there is a significant increase in RBER at the end of chip lifetime. Figure 7 shows the distribution of the number of error bits per page of an ordinary block after P/E cycles operation. The shaded area in the figure indicates the number of error bits of the block. 16 pages at each end are SLC pages, which have fewer error bits. The error bits are mainly distributed on the shared pages, and more error bits are concentrated at both ends of shared pages. We also test the effect of P/E cycles on the standard deviation of error bits on per page (as shown in Fig. 8). There are nine sets of data, varying from 100 to 8000 P/E cycles. It can be observed that with the increase of the of P/E cycles, the standard deviation of error bits on per page also increases. There is also a significant dispersion standard increase at the end of the chip lifetime.

ABSTRACT. This paper proposes a new method of investigating the effect of void or fracture in FBGA solder ball on the DDR4 data signal rise time and inter-symbol interference (ISI), by loading the data line with a capacitor. A void or fracture in solder ball increases its capacitance which effects the data signal rise time and increases ISI. For measuring ISI large patterns of 1’s or 0’s followed by a changing bit are used. However in in-field systems it is not possible to run large patterns of 1’s or 0’s. So the data line is loaded with a 0.2pF capacitive load on a UDIMM test card to mimic the increased capacitance due to FBGA solder ball void defect of height 0.2 mm and cross sectional area of 0.045 mm2. The loaded line shows increase in rise time of 16 ps. For loaded line the data eye opening is 0.077 UI lesser. This decrease in data eye means more ISI and it will cause increase in intermittent errors.

ABSTRACT. Stability is an important performance indicator for SnO2 gas sensor and affected by temperature. Commercial SnO2 gas sensors are stored at environment temperature but operating at a temperature above 200 °C heated by a strip heater under a DC power supply. The degradation behaviors during storage were not identified and the differences of the degradation processes between storage and operation stages need to be further understood. This paper investigated degradation of SnO2 sensors under elevated environmental temperature and heating voltage conditions to interpret sensor instability.

ABSTRACT. The significance of this paper is to emphasize wafer scale electrochemical plating process optimizations to demonstrate yield-limiting defects reduction. A multiple process enhancement has been implemented to reduce metal “stress –induced” voids, crater defects, Cu mound, as well as other killer defects. The troubleshooting is involving thermal anneal conditions with the modifications of in-situ anneal to integrated helium anneal by demonstrating capability of ramp rates during heating and cooling stages. Result shows a significant defects reduction and reveals the dependence of anneal soak time particularly for types of defects. Due to this integration of concerns, we further investigate the adoption of integrated diffuser to quantify the best degree of uniformity and high resistivity to enhance an even current distribution on the wafer. The results show that uniformity of the deposited film has been improved significantly with an increasing trend with anolyte lifetime.

ABSTRACT. Counterfeit electronics pose reliability risks and severe harms. The failures of systems that use counterfeits can cause safety and security problems. Many factors contribute: lack of carefulness on the part of buyers, obsolescence, lower prices, costly inspection procedures, absence of origin verification tools. Two case studies are proposed to add a piece of information in this context. They add evidence regarding the capillary penetration of the counterfeit devices. It should contribute to arise some concerns.

ABSTRACT. Goal of the work is a closed loop analysis where FA results are being used in inspection and review steps to improve product yield. Additional rule check is proposed at inline inspection and review step using potential failing patterns from FA. A subset of, machine learning (ML) with image processing and pattern search are used to find the unique patterns of defects by making the machine to build a library (training data) of all failing design structures observed during FA.

ABSTRACT. Light emitting diodes (LEDs) exhibit different degradation physics under different environmental conditions of humidity, temperature and electrical loading, leading to complex degradation models – a common behavior with several other electronic devices. While most researches focus on degradation under active use, degradation models in storage are often not well established. Large fleet storage of components, in the absence of a degradation model, require laborious continuous inspections despite the preservation under similar environmental conditions. Leveraging on training data from other LEDs within the fleet, stored under similar conditions, this study investigates the utility of multi-output Gaussian Process Regression (MOGPR) with limited test data, to model the complex degradation curve of LEDs in storage, as a proxy for electronic components. We further explore the choice of detrending means and training data sets, to enhance the prediction of degradation curves and residual storage life (RSL). Additional training data sets are observed to give diminishing returns for prediction accuracy.

ABSTRACT. This paper focuses on the thermal loading of the novel quasi Z source inverter based wind power generation system. The lifetime of the wind power converter is strongly influenced by the thermal behaviour of the power devices and their mission profile. For the unique boost modulations of quasi Z source grid-connected inverter, an electro-thermal model is rebuilt to calculate the semiconductor junction temperature. And a simulation platform is developed in Simulink environment to analyse the electro-thermal dynamics of the system by using different modulation strategies and analysing different wind-load conditions. The results show that power loss in both positive and negative half output cycle will prevent the decline of junction temperature in semiconductor devices. For segment boost modulation, variable wind speed can reduce the temperature fluctuation due to the increasing loss in negative half output cycle.

ABSTRACT. This paper proposes a hybrid anti-radiation method to enhance the reliability of Field Programmable Gate Array (FPGA), which is being applied more and more in the commercial small satellite. The method utilizes the advantages of Error Detection And Correction (EDAC) and Triple Modular Redundancy (TMR). Different bus control units are improved by different anti-radiation techniques. For finite state machine, dual-port block random access memory and EDAC are utilized. Hamming code is used to enhance First In First Output unit. For the simple control register, TMR is applied to improve its anti-radiation. This hybrid method can avoid the accumulated error of TMR and reduce the complexity of system. Experimental results show that the proposed method can correct 1-bit error and detect 2-bit error effectively.

ABSTRACT. This paper provides a pin assignment optimization in logic gates to improve in-orbit soft-error rate. Signal probability is used to assign the lowest probability to the most sensitive input combination of the circuit. An optimized cell netlist can achieve from 5% to 35% reduction on the in-orbit Single-Event Transient (SET) rate.

ABSTRACT. The single event effect (SEE) experiment towards a pulse width modulator (PWM) within the DC/DC converter was carried out by Ta+ ions (LET =83.53 MeV•cm2/mg) so as to reveal the single-event induced failure mechanisms. In order to figure out the perturbation and its propagation, an additional experiment of a standalone PWM illustrated two modes that possible address the operation failure in DC/DC converter including the low-level output error and the high-level one. Matlab model reveals the relationship between the SEE in PWM and subsequent SET in DC/DC converter.

ABSTRACT. An application-specific Single-Event Transient (SET) characterization based on the signal probability is proposed to optimize the Triple-Modular Redundancy (TMR) block insertion methodologies. Results show that the SET cross-section of complex-gate architectures presents low input dependence while for the NOR/NAND based architectures a higher dependence is observed due to logical masking effects. Additionally, different from the other architectures, the NAND voter has shown a reduction on the SET rate as the signal probability is increased.

ABSTRACT. In this paper, a fault injection campaign is performed in order to emulate the radiation-induced effects on the configuration memory of AP-SoC Zynq 7000, specifically targeting the interconnection module implemented on the programmable logic. This Interconnection Module is crucial for a wide range of applications and mitigation techniques such as hardware-accelerated designs, Dynamic Partial Reconfiguration or Triple Modular Redundancy, especially if they aim to meet high performance and high bandwidth. The fault injection results have been analyzed and classified accordingly with the effect observed on the processor-system side in terms of availability and fault model affecting data computed by the IP Cores implemented on the programable logic of the SoC.

ABSTRACT. System-on-Chip (SoC) devices can be composed of low-power multicore processors combined with a small graphics accelerator (or GPU) which offers a trade-off between computational capacity and low-power consumption. In this work we use the LLFI-GPU fault injection tool on one of these devices to compare the sensitivity to soft errors of two different CUDA versions of matrix multiplication benchmark. Specifically, we perform fault injection campaigns on a Jetson TK1 development kit, a board equipped with a SoC including an NVIDIA "Kepler" Graphics Processing Unit (GPU). We evaluate the effect of modifying the size of the problem and also the thread-block size on the behaviour of the algorithms. Our results show that the block version of the matrix multiplication benchmark that leverages the shared memory of the GPU is not only faster than the element-wise version, but it is also much more resilient to soft errors. We also use the cuda-gdb debugger to analyze the main causes of the crashes in the code due to soft errors. Our experiments show that most of the errors are due to accesses to invalid positions of the different memories of the GPU, which causes that the block version suffers a higher percentage of this kind of errors.

ABSTRACT. Abstract –FinFET technology compared with planar have an increased sensitivity to single-event latch-up. TCAD simulation demonstrates that the reduction in thickness of shallow trench isolation (STI) and nMOS-to-pMOS lateral spacing will reduce the holding voltage, critical charge and increase the current gain of parasitic CMOS Silicon Controlled Rectifier (SCR). Through circuit analysis, it found that the change of parasitic vertical and horizontal resistance is mainly responsible for aforementioned phenomena. In addition, we found that the common protective measures such as guard rings spacing and epitaxial substrate become increasingly difficult. Based on the current preventive methods, we think that appropriate increasing the width of guard rings or increasing the doping depth of guard rings will improve protection from Single-Event Latch-up (SEL). Moreover, we discuss the feasibility of our methods and verify the effectiveness by TCAD simulation.

ABSTRACT. The downscaling of feature sizes increases the susceptibility to Single Event Effects in integrated circuits. As a manner to mitigate soft errors, solutions incur significant performance and area penalties. This paper proposes a discussion about two methods to evaluate gate susceptibility considering Single Event Transient faults at the gate layout level. The results show the need for fast and accurate methods to evaluate logic gates susceptibility to make it possible to evaluate the most reliable option.