ABSTRACT. The charges in wide bandgap Gallium Nitride (GaN) High Electron Mobility Transistors (HEMT) can be identified by means of various methods such as electrical transient, time or frequency domain pulsed characterization, or noise spectroscopy methods, usually performed at different temperatures to extract activation energies. These traps can be neutralized or activated with electrical or thermal conditions over a lifetime. Therefore, the distinction between harmful traps (with consequences on performances) and harmless traps (without impact on electrical behaviour) must be performed. In this paper, devices stressed by HTOL (High Temperature Operating Life) and HTRB (High Temperature Reverse Bias) are characterized by time domain electrical techniques (transient and pulsed), and with low frequency noise (LFN) tools. By performing characterizations on the gate and on the drain accesses, it is also possible to target the drain current sensitivity IDS to specific regions of the transistor. Many papers are available concerning the identification of traps, some offer cross-analyses of the defects, and develop a fine analysis of their correlation with the electrical behaviour of transistors before and after the application of a stress. The proposed case study tracks the traps or charges in the different zones of the transistor, and makes correlations with static or transient evolutions of IDS.

ABSTRACT. This paper describes the test plan and the main results achieved by UMS during the space evaluation program of its second generation 0.5µm GaN RF power bar technology, so called GH50-20. The technology has successfully passed a space evaluation program. The space evaluation tests results are summarised: A life time higher than 5E+06 hrs @ 200°C is found, SEE, TID and DD radiation hardness safe area were defined, and failure rate below 8 FIT @ 200°C was determined . The results also include demonstration of representative integrated circuits up to 130 W RF power level when operated in L-band in continuous wave (CW) mode.

ABSTRACT. In this contribution, the presence of trap states in self-switching diodes based on AlGaN/GaN has been identified by means of an AC characterization between 75 kHz to 30 MHz in a wide temperature range, from 70 K to 300 K. Measurements allow us to determine two different characteristic energies of the traps, 12 meV and 61 meV. The impact of the trapping effects on microwave detection at zero-bias has been analyzed in the same temperature range, the measured responsivity showing an unusual enhancement and a frequency roll-off at low temperatures.

ABSTRACT. An adaptive bias strategy is proposed to harden fully integrated CMOS RF power amplifiers against time-dependent parametric degradation due to hot carrier injection. PA transistor DC current is compared to a reference using an operational transconductance amplifier that provides an adaptive gate DC voltage to the PA transistor as its threshold voltage increases due to stress. Based on degradation modeling obtained from experimental accelerated aging of a transistor and a RF PA implemented on a 130 nm technology, time dependent simulation results of the adaptive bias show that the proposed circuit effectively compensates for the threshold voltage increase of the main transistor.

ABSTRACT. The degradation mechanisms of AlGaN/GaN HEMTs adopting Fe and C co-doping, with high and low carbon doping concentration was investigated by means of hot-electron step stress and 24 hours’ stress tests. Firstly, DC and EL characterization at room temperature are summarized, then the parametric evolution during hot-electron step stress tests at the semi-on state were compared, the assumption for the degradation mechanism is that hot-electrons activated the pre-existing traps in the buffer, attenuate the electric field in the gate drain access region and damaging the gate contact, the parametric evolution during constant stress at (-2 V, 25 V) is discussed. The results further is in accordance with the assumption, proving that the degradation mechanism is hot-electron related.

ABSTRACT. This paper presents a novel discontinuous space vector modulation (SVM) strategy to reduce the thermal stress of three phase impedance source inverters (ISI). By exploiting the switch clamping mechanism and proper arrangement of the shoot-though (ST) states, the proposed strategy functions to optimize the thermal performance and improve the reliability of ISI. The feasibility of the proposed strategy has been benchmarked by simulation and experiment. More analysis will be provided in the final paper.

ABSTRACT. System-level reliability of the wind power converter has an essential effect on the operation performance and lifespan of a wind turbine system. In this paper, a wind turbine equipped with a 2 MW direct-drive permanent-magnet synchronous generator (PMSG) serves as a case study. Considering the maximum stator current limitation of the PMSG, several multiple-converter structures and their reliability block diagrams (RBDs) are constructed for the machine side converter (MSC). To investigate the reliability influence caused by the amount of semiconductor components and the current for each components, structures with four and five bridges in parallel are both configured. Reliability evaluation between two major parallel structures, namely, bridges in parallel and converters in parallel are also compared. A detailed discussion regarding the system reliability cumulative distribution function (CDF) is presented, which could serve as reference for further MSC structure design.

ABSTRACT. Abstract –A power converter with effective fault-diagnosis and fault-tolerant control can improve the reliability of switched reluctance motor drive system (SRD). At present, there are many research results on single power switch fault. In view of the multi-switches faults caused by the harsh operational environments and repetitive duty cycles, this paper presents a flexible fault-tolerant topology with fault-diagnosis, fault-tolerant control strategy for diverse open-circuit faults occurring in the SRD under different working conditions, and the common H-bridge has been selected as the fault-tolerant topology. When the SRD is subjected to open-circuit faults, the fault-diagnosis can be achieved by detecting the characteristic of the real-time phase currents, and then the faulty switches can be replaced automatically by the corresponding reverse ones to sustain the driving operation with further optimized output torque.

ABSTRACT. In this paper, a comprehensive analysis, considering the real-field mission profile and influence from PV panel configuration is provided. The results show that with the increase of number of PV strings from 160 to 200 in an 800MW inverter, the daily average full-power duration could also increase from less than 1 hour to almost 3 hours, that making better cost-efficiency. While the lifetime of inverter, which is characterized by IGBT operation lifetime, decreases from 40 years to 20 years.

ABSTRACT. Photovoltaic (PV) power systems have been rapidly installed worldwide in recent years. It is believed that PV power plants will operate stably for more than 25 years. However, PV modules can fail unexpectedly. In this paper, we have diagnosed a 10-year-old power plant using a drone with an infra-red (IR) camera and recorded current-voltage (I-V) and electroluminescence (EL) measurements. The ~1-MW plant, comprising two different PV modules—of 200 and 220 W—showed various failure modes, and approximately 59% of PV module failures caused an output loss. An inverter with a serious loss is expected to degrade to an extent exceeding its annual degradation rate in PV strings above 40%. As a result, the power loss was quantitatively estimated considering hotspots, bypass diode failure, and the degradation rate. The capacity of the current PV system was evaluated to be 88.3% and 93.2% for the two types of PV modules.

ABSTRACT. To predict the life of solder joints under temperature cycling and electric coupling condition, this paper proposes a Physics of Failure (PoF) model based on the continuum damage mechanics (CDM). Firstly, considering the effect of current on solder’s mechanical properties, the current-affected constitutive models of plastic fatigue and creep are constructed. Then, based on the mechanism of energy dissipation, a unified creep-plasticity damage evolution law is deduced, and the nonlinear accumulation damage model is developed. Choosing electric resistance as the indirect damage variable measurement, the thermal-electric coupling PoF model is finally established by substituting the current-affected constitutive models into the damage evolution model. A thermal-electric coupling test is carried out to verify the accuracy of PoF model. The experimental results confirm that the proposed PoF model can effectively predict the life of solder joints under temperature cycling and electric coupling condition.

ABSTRACT. Relatively little is known about the influence of manufacture parameters distribution on the reliability of electrical connectors under fretting conditions. In order to investigate the fretting wear lifetime of electrical connectors, an estimation model is proposed. The theoretical model of normal contact force for connector is established. Then, the initial model of electrical connectors is constructed utilizing the Monte Carlo sampling method and the distribution of normal contact forces is analyzed. In addition, the corresponding fretting wear lifetime is calculated based on the estimation model, and then its distribution type and distributing parameters are obtained. Finally, the reliability assessment method of electrical connectors is completed.

ABSTRACT. This paper presents a novel loading evaluation procedure to be used for IGBT power cycling. The method is a combination of experimental life tests and finite element analysis digital twin. It was validated and predicted the life-time with 2.77% error, compared to the 8.78% error of the reference.

ABSTRACT. Abstract – It remains a great challenge to investigate time-dependent reliability-based design optimization (TRBDO) problems, owing to the high computational cost of time-dependent reliability analysis, and the difficulties to model. To address these issues, ADE-T-PCE, a methodology incorporating an adaptive differential evolution (ADE) algorithm and an enhanced instantaneous time-dependent polynomial chaos expansions (T-PCE) is proposed. In the proposed method, the universal polynomial chaos expression (PCE) method was improved based on time-domain extension and principal component selection partial least squares, the life-cycle reliability model of time-dependent PCE is formed. Once the time-dependent model is built, time-dependent reliability can be computed conveniently. Consequently, dynamic niche Pareto optimal solution selection strategy, particle variations and and optimal solution screening strategy, number and strategy of particle variation for the differential evolution algorithm were proposed to meet demands for multi-object time-dependent reliability design optimization. The effectiveness of proposed method was verified by an electromagnetic relay in electric vehicles coupled with multiple degeneration factors in this study.

ABSTRACT. This paper presents a design strategy to reduce the impact of process variations and soft error susceptibility in FinFET circuits. The mitigation is provided by connecting a Schmitt Trigger in the gate output. The improvements in power and delay variability can reach up to 32.6% and 42.1%, respectively, with logic cells almost immune to soft error even at the near-threshold regime. When compared with other circuit-level approaches such as sleep transistor, decoupling cells, and transistor reordering, on average, the Schmitt Trigger technique is at least 6%, 8%, and 10.5% more robust to process variability, respectively.

ABSTRACT. Automotive environment generates vibration and temperature fluctuation, which reduces the life of electronic boards. In this paper, vibration tests are performed continuously throughout thermal cycling to investigate the combined effect of temperature and vibration on the SAC305 solder of Quad Flat No-lead (QFN) terminals pads bonded on Printed Circuit Board (PCB). Experimental results imply that the number of combined cycles affects the PCB responses. Fifty thermal cycles combined with fatigue random vibration test has been carried out on 100 QFN terminal pads solder. Statistical evaluation of the solder fatigue showed that cracking has started in 68% of them. On the other hand, an accurate numerical model for simultaneous combined thermal cycling and vibration simulation is developed and validated by experiments.

ABSTRACT. PCB-Embedding technology in an established approach for the miniaturization of electronic systems and modules. Silver sintering, which is a reliable alternative to Lead-Free Bonding, is used to assemble the embedded power components in the PCB. Thermal cycles [−25°C/+125°C] have highlighted degradations in the die attach solder. The shear strength of dice decreases from 4 MPa before cycling to 2 MPa at 1040 cycles. The junction temperature has drifted during cycling especially at high temperatures. Simulations have shown that the maximal stresses are in the preg materials. This suggests cracks of the preg during the experiments. Simulations showed also a concentration of plastic stresses on the die attaches. The accumulation of stresses increases during ageing. The presented methodology of thermal cycling simulation represents a good way to estimate the lifetime of Embedded PCB.

ABSTRACT. Mechanical bending fatigue experiments were conducted on large area Pb-rich and SnSb-based model solder joints consisting of Cu-strip/solder/DCB substrates. Experimental lifetime curves in the range between 105 and 108 loading cycles at room and elevated temperature showed an improved fatigue resistance for SnSb alloys. Crack length as a function of loading cycles (da/dN) was determined for selected samples to study the cyclic degradation behaviour of the solder layer. Crack initiation and propagation in the joints was modelled on the basis of a damage accumulation rule considering the strain rate and temperature dependency of the solder alloy. Application of the FEM model to large area solder joints allowed calculation of the incremental advancement of the crack front, determination of the crack growth rate (da/dN) and prediction of lifetime under a given loading condition.

ABSTRACT. In this publication, the influence of wire material properties (2N/4N) and plasma pre-treatment on the wire-bond strength is investigated, comparing the wire pull force capability and analysing the cross sections of the Au/Al bonds after High Temperature Storage Life (HTSL, 150°C), Temperature Cycling (TC, -65°C – 150 °C) and unbiased Humidity Accelerated Stress Test (uHAST, 130°C/85%RH). Furthermore, it will be shown how learning cycles can be accelerated by using elevated test temperatures (HTSL, 250°C). The effect of plasma treatment on 2N and 4N wires will also be discussed. Major impact factors on wire-bonding reliability are bond pad thickness, pad opening and the corresponding Aluminium splash in dependence on the bond parameters settings with and without plasma treatment prior to wire bonding.

ABSTRACT. Accelerated life test (ALT) is widely used to predict life of solder joints nowadays, and how to shorten the test time and improve the precise of evaluation is one of the most important issues. Based on statistical results of field failure for solder joints, improved ALT under combined thermal cycling and vibration loading conditions was designed and carried out. This paper presents a modified Engelmaier fatigue model to predict life of solder joints, by taking into account field failure data and ALT testing data. The results show that test time of improved ALT is more shorter than conventional one , and the result of remaining life prediction based on modified Engelmaier fatigue model becomes more precise due to improving life model and increasing information.

ABSTRACT. The goal of this paper is to investigate the stability of CdTe solar cells exposed to high temperature storage. Several cells, having different thickness of copper in the contacts and of CdTe absorber were investigated. The results, obtained through combined EQE, dark and light IV, and photovoltage decay, indicate that the Cu metal contact plays a role in the degradation of the solar cells, and provide detailed insight on the related processes.

ABSTRACT. The aim of this work is to study the degradation processes in high power InGaN semiconductor lasers, by means of electrical, optical, spectral and capacitance deep-level transient spectroscopy measurements. The devices were submitted to two different stress experiments, (i) a constant current stress at 1.5 A at 45 °C, and (ii) a temperature/bias step stress at 1 A and increasing temperature. Results demonstrated: (i) two different mechanisms that change the drive voltage, one due to the activation of Mg and one ascribed to the generation of point defects; (ii) a parasitic peak is present in the emission spectra, ascribed to the recombination in a second quantum well (QW); (iii) redistribution of charge takes place during the temperature step stress.

ABSTRACT. We investigate the degradation of InGaN-GaN MQW solar cells under optical and electrical stress. We submitted the devices to high temperature, high optical power stress and we found that, under optical stress, the devices show a moderate decrease in open-circuit voltage, possibly due to creation of defect-related shunt paths. This degradation is partially recovered after room temperature storage. The stronger decrease of open-circuit voltage under electrical stress at high current suggests a role of carrier flow in the degradation.

ABSTRACT. In this work we propose a new sensor concept to evaluate the degradation of PV arrays due to soiling. It is based on the I-V curve analysis coupled with an artificial vision inspection of a reference PV module to quantify and identify the type of dirt. Considering the use of this approach in the automatic scheduling of maintenance interventions in smartgrids, we developed a Simulink model of a DC nanogrid to test different control strategies. Here, early results are shown to demonstrate the effective-ness of the sensor.

ABSTRACT. This paper focuses on the crack problem of silicon photovoltaic（PV） modules. In order to extract the fault characteristics of the cracked PV modules, we investigate and collect the cracked PV modules in several large PV power plants. The I-V characteristics of the cracked PV modules are tested. The test results show that the I-V curves of the cracked PV modules show a convex function step, and the reason for the I-V characteristics of the cracked PV module is analysed. A method for online diagnosis of PV module crack through I-V curve is proposed.

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ABSTRACT. UMOSFET on-resistances have been dramatically improved in recent decades with the miniaturization of cell size by innovations in the fabrication process. However, with miniaturization, failure in the gate oxide, large deviations in the threshold voltage and reductions in avalanche capability have emerged as design problems for mass production. In particular, rises in the gate threshold voltage can cause significant damage to the yield in MOSFET mass production. Threshold voltage rises have appeared with the introduction of a trench source contact. The source contact trench and MOS gate trench are fabricated next to each other with a narrow silicon mesa region, and the voltage rises appear when the silicon mesa width becomes narrower than 80 nm. So far, it appears that the P+ layer dopant in the contact sidewall diffuses toward the gate oxide and the channel doping increases, which causes the rise in the threshold voltage Vth. We analyzed the distribution of Vth at the wafer level/shot level and found for the first time that the rise in Vth is caused by the punch-through effect from the channel depletion layer to the contact P+ layer, and thus, sidewall dopant diffusion will not affect the rise in Vth. We established an analytical model for the rise in Vth and validated the model by comparing it with UMOSFET production data. Our model showed that for the field plate type UMOSFET with a shorter gate contact length, not only is there a rise in Vth, but also it is difficult to control Vth using the conventional channel implantation method.

ABSTRACT. A new silicate glass passivation was studied on Metal-Dielectrics-Semiconductor structures to characterize the reliability performances of TRIAC devices. The presence of mobile ions was identified in the glass affecting the reliability performances. The addition of a semi-insulating passivation layer turns out to drastically improve the reliability performances of TRIAC devices.

ABSTRACT. In this paper, the online aging monitoring system of IGBTs is built and its thermal circuit is carefully designed. A detailed error analysis is conducted on the measurement system, which shows a decent uncertainty of the precursors obtained. Based on the test results, a novel machine learning technique, i.e. recurrent neural networks (RNN) using long short-term memory (LSTM) units, is introduced to predict the remaining lifetime prediction and outperforms the typical extended Kalman filter (EKF).

ABSTRACT. We discuss the impact of the non-uniformity in interface defect distribution at a SiO2/SiC interface on the field effect mobility of SiC metal oxide semiconductor field effect transistors. By device simulation based on interface defect distribution experimentally observed by local deep level transient spectroscopy, we show that interface defect distribution containing smaller features gives higher impact on the field effect mobility.

ABSTRACT. This paper aims to identify and distinguish multiple failure modes of SiC planar MOSFETs under different SC conditions, based on the transient temperature estimation of two key zones, i.e. the JFET region and the source Al layer adjacent to the upper side of gate dielectric. A multi-layer thermal model is proposed to reproduce the temperature profile, and it has been validated at wide DC bus voltages (from 200 to 800 V). The model is also able to predict the failures using normal SC turn-off waveforms.

ABSTRACT. Previous research showed that Si devices could sustain a large number of Short Circuit (SC) events, as long as the energy dissipated during SC remains slightly below a given threshold (the so-called critical energy). In this paper, we show that this is not necessarily true for SiC MOSFETs, which can only withstand a few such SC events. This low robustness to repetitive short-circuit events is related to the gate degradation due to the cumulative carrier injection and leakage currents in the oxide. To ensure safe operation over a large number of SC events, we introduce a new parameter: the “repetitive critical energy”, which corresponds to a SC energy low enough to avoid excessive temperature increase and so to limit the transient gate leakage current during SC events. Below this repetitive SC energy value, the SiC device is able to sustain a large number (more than 1000) of SC events.

ABSTRACT. This paper investigates the crosstalk-induced spontaneous switchings and gate bouncing as continuous cycles of turn-on and turn-off transients as a key reliability bottleneck in SiC and GaN cascode power devices. The paper will present a wide range of measurements to describe the severity of unwanted switching cycles in presence of snappy turn-off current off a free-wheeling diode which results in a negative gate voltage induced by the source inductance of the cascode packaged devices. This is shown to lead to positive feedback loop, thermal runaway and eventual failure. Modelling is performed which confirms the theory described to explain the root cause of the continued oscillatory transients and comparisons are made with standalone SiC power MOSFETs.

ABSTRACT. In this paper the ruggedness of stand-alone and cascode SiC JFETs is evaluated under single and repetitive unclamped inductive switching (UIS). The impact of the JFET gate resistance, avalanche current and temperature are evaluated. The results show that the avalanche characteristics are strongly affected by the peak avalanche current and the JFET gate resistance, due to the significant gate leakage current that results from impact ionisation. This gate leakage current plays a fundamental role on the reduced performance under repetitive UIS of cascode SiC JFETs compared with stand-alone SiC JFETs.

ABSTRACT. This paper discusses whether short-circuit capability of multi-chip SiC-MOSFET power modules is affected by stray-inductance imbalance between the chips. Experimental power modules equipped with commercial 1.2-kV, 19-A SiC-MOSFET chips are designed and fabricated in three different internal layouts, and then short-circuit capability of the power modules was measured. The experimental results show that the significant effect of stray-inductance imbalance can be seen only for 20 ns after the short-circuit event start. As a result, this paper reveals that multi-chip power module design doesn’t need to pay attention to imbalance of stray inductance from the perspective of the short-circuit robustness.

ABSTRACT. This paper investigates the effect of short-circuit degradation on the remaining useful lifetime of SiC MOSFETs. A different number of repetitive short-circuit events have been introduced into the accelerated power cycling tests to assess the impact. The experimental results indicate a gate degradation with the increasing number of short-circuit repetitions, which leads to higher conduction loss and earlier failure. This hypothesis has been validated by performing lock-in thermography, scanning electron microscopy and focused ion beam.

ABSTRACT. The aim of this work is to study the catastrophic and gradual degradation of H-terminated diamond MESFETs. They are able to withstand high power densities before failure, but are still affected by a bias-dependent degradation. The main degradation modes are an increase in ON-resistance and threshold voltage, and are caused by the higher concentration of a 0.3 eV deep level. Electroluminescence measurements confirm the increase in electron scattering, and highlight a progressive reduction in peak electric field in the device under test, possibly due to a virtual field plate effect.

ABSTRACT. This paper investigates the characteristic fluctuation of E-mode GaN-HEMTs, especially focusing under reverse current conduction. The experimental results exhibit that the energy stress of reverse current conduction is relatively higher than that of forward current conduction. After forward and reverse stress, gate threshold voltages were slightly shifted to positive and negative, respectively, which indicates different degradation mechanisms in each case. On the other hand, on-resistances were increased with time duration in the both stress conditions.

ABSTRACT. Abstract – In this paper, a normally-off high voltage GaN HFETs based on the Polarization Super Junction (PSJ) concept has been presented. In this new device, threshold voltage can be controlled by adjusting the etching depth of the recessed region with remaining on-resistance characteristics. The threshold voltage of E-mode device increased to 2 V while the threshold voltage for experimental D-mode structure was about -4 V. The challenge of achieving high breakdown voltage (BV) with minimum on-resistance has been addressed by the lateral scaling of recessed region to achieve an improved figure of merit (FOM). The specific on-resistance of the proposed E-mode PSJ HFET is maintained low while the BV of the device increases to 800V from 560V of the D-mode PSJ HFET with the same dimensional parameters.

ABSTRACT. Junction temperature fluctuations of power modules in electric vehicles (EV) have a significant impact on system reliability. This paper aims to estimate the junction temperature of IGBT modules with direct coolant for permanent magnet synchronous motors (PMSM) under complex boundary conditions. The advantage of the thermal network proposed in this article is that it does not require any temperature sensor except the built-in negative thermal coefficient (NTC) thermistor. Finally, the good accuracy of this model is demonstrated by a series of experiments considering complicated boundary conditions and multiple working conditions.

ABSTRACT. Abstract – The reliability of switched reluctance drive system (SRD) can be improved by an effective thermal management strategy, when SRD is exposed to harsh environment and anything could happen throughout the life time. In order to avoid overtemperature fault of power converter, there are generally two methods: derating and switching frequency reduction. However, the derating methods will lead to insufficient power and even affect the safety of SRD. An active thermal management strategy for SRD with minimizing current sampling delay is proposed in this paper, which can ensure that the temperature of power converter will not exceed the maximum allowable temperature under any working condition by adjusting switching frequency. In the proposed strategy, the sampling method can ensure that the output performance of SRD at low switching frequency is not poorer than that of traditional sampling method at normal switching frequency by optimizing the sampling point.

ABSTRACT. In this paper, based on the harmonic problem appearing in the voltage, it is proposed to apply the repetitive control with equivalent input disturbance (EID) in the diode clamp type three-level inverter to obtain a smooth and stable output voltage waveform. The effectiveness of the control method is verified. The results show that this combined control method can effectively suppress the periodic and non-periodic disturbances in the system and improve the reliability of the whole system.

ABSTRACT. In this paper, different reliability simulation approaches of an improved DC current flow controller (CFC) integrated voltage-sourced converter (VSC) based DC grids are investigated with the following contributions: (1) In order to achieve bidirectional power flow control and fault current blocking capability, an improved DC CFC topology with a set of reversed switches is proposed to enhance the controllable path and control margins; (2) Two different reliability simulation approaches of the improved DC CFC integrated meshed multi-terminal DC (M2TDC) grid are analysed. In Approach I, the VSCs and their AC sides are modelled without simplification. In Approach II, the VSCs and their AC sides are represented by ideal DC voltage/current sources to simplify the system modelling; (3) Synthesizing the merits of both approaches while avoiding the deficiencies, a hybrid reliability simulation approach is proposed with high efficiency of simulation while maintaining the accuracy; (4) In order to further enhance the simulation efficiency, a different reliability simulation approach of the ideal DC current source, namely improved ideal DC current source, is proposed. Simulation systems are established in PSCAD/EMTDC for verification.

ABSTRACT. Aging and malfunction of devices with great power has been the main cause of the grid system’s collapse and failure. Being frequently used in the grid system, the failure of SST has a great impact on the energy-saving and normal operation of the network system. Moreover, the main switching element of SST is IGBT of welding type which is also the most fragile part. We firstly introduce the structure and basic function of SST. Then we can conclude the main cause of the converter’s internal fault in SST from the phenomenon of uneven current flow in simple paralleled IGBT models. Analyze the changing trend of equivalent resistance of single-phase SST under short-circuit or open-circuit condition, taking the numbers of IGBT in failure mode and the fault type as variables. External electrical parameters of SST change with the failure condition of internal IGBT devices, therefore, voltage and current values will change due to the variation of equivalent resistance. So, propose that the collector-emitter voltage can be used to characterize SST’s fault conditions, then establish the simulation model of SST and set different failure circumstances to verify the hypothesis in the simulation process. Eventually, the conclusion can be drawn as follows: the collector-emitter voltage as well as VM which is the voltage of the transformer’s primary side in SST can be used to characterize the failure condition of SST’s internal converter.

ABSTRACT. This paper proposes a gate drive circuit for the current balancing of parallel-connected SiC-JFETs under avalanche mode. For a semiconductor DC circuit breaker, the power devices have to be connected in parallel to reduce the on-resistance and increase the limitation of current rating. In addition, it is reported that the SiC-JFET is suitable power devices from the view point of both conduction loss and degradation characteristics. This paper analyzes the behavior of current unbalance, and then designed the gate voltage and gate resistance in a gate drive circuit. The gate drive circuit can achieve the current balance equalization of parallel-connected SiC-JFETs under avalanche mode. The validity of the proposed gate drive circuit is verified by the experiment that uses 1.2~kV SiC-JFETs for a 400~V system.

ABSTRACT. To analyse the reliability of negative resistance converter traction power system (NRC-TPS), this paper discusses the short-circuit and open-circuit faults of its components. NRC-TPS is adopted to mitigate rail potential and stray current for the urban rail transit. The simulation results show that NRC-TPS can still mitigate rail potential and stray current at most faults. NRC-TPS is reliable for the urban rail transit to solve rail potential and stray current issues.

ABSTRACT. In order to improve the reliability of Modular Multilevel Converters (MMC), the unexpected modes which will lead to unintended outcomes should be identified. In this paper, the unexpected modes of semi-full-bridge (SFB) submodule are detected through superposition of passive components on different switching states according to the operation principles. Then, further analysis on triggered conditions and effect of unexpected modes is helpful to avoid potential threat on MMC, which is also an effective way to protect the normal operation of MMC.

ABSTRACT. Herein, a method for condition monitoring of the gate oxide degradation for SiC MOSFETs is presented. To identify gate oxide degradation in SiC MOSFETs, a high-temperature gate bias (HTGB) test, which is an accelerated aging test, is usually performed. This paper proposes an advanced HTGB test. The test is suitable for developing a condition monitoring circuit because the test can accelerate the device aging under switching conditions. Using the test results, the parameter shifts of gate threshold voltage and gate capacitance are demonstrated, and condition monitoring technique is considered.

ABSTRACT. In this paper, a stability analysis method based on Floquet theory is firstly proposed to provide an effective stability analysis method for paralleled LLC resonant converter system. Firstly, the time-domain model of a paralleled LLC resonant converter system is established, then, the stable range of the paralleled LLC resonant converter system can be determined by analysing the eigenvalues of the state transfer matrix based on Floquet theory, which is obtained from the established time-domain model. Finally, a two-stage paralleled LLC resonant converter system controlled by average current mode is taken as an example, the correctness and effectiveness of the proposed stability analysis method based on Floquet Theory is verified by simulation. The proposed stability analysis method can avoid the complex derivation of transfer function and impedance in frequency domain analysis methods.

ABSTRACT. This paper investigates characteristics and reliability of SiC power devices used for a start-up method based on multiple short-circuits. A planar-gate and trench-gate SiC-MOSFETs and SiC-JFET employed in a practical power converter are are tested under the start-up method using multiple short-circuits more than 10000 cycles. The experimental results exhibit only the planar-gate SiC-MOSFET can survive the 10000 cycle short-circuit tests with slight degradation under a testing condition. As a result, this paper reveals the planar-gate SiC-MOSFET is suitable for the start-up method due to its characteristic.

ABSTRACT. In this paper the effects of various parameters on the behavior of SiC converters are investigated. SiC devices have many advantages over Si ones; However, they yearn for an increase in their reliability, which can be achieved either by design enhancement or improvement of their corresponding condition monitoring approaches. The goal here is to replace costly and time-consuming physical experiments with simulations. For the sake of simplicity, we have chosen a buck converter as the testing unit. However, the same approach can be implemented for the other converters. Among the parameters we have investigated are the bond wires, MOSFET parameters, capacitors, and inductors. For these parameters, we have studied how their statistical distributions reproduce the statistical distribution of outputs and also obtained the sensitivities of outputs to them.