A Single-Trap Study of PBTI in SiON nMOS Transistors

EasyChair Preprint 4312

Abstract

To accurately study positive bias temperature instability (PBTI) in nanoscale SiON nMOS transistors we make use of the time-dependent defect spectroscopy (TDDS) and examine the device performance degradation at the single-defect level. Contrary to what is visible in large-area devices, our investigations clearly reveal charge trapping at both electron and hole traps contribute to the overall drift of the threshold voltage in these devices. Even though only electron trapping is typically considered for PBTI we observe that hole traps account for around 20% of the total threshold voltage drift. To evaluate the impact of single-defects on the device performance we characterize the charge trapping kinetics of a number of defects, which can be explained employing a two-state defect model. In our approach we consider charge trapping due to defect/channel and defect/poly-gate interactions for the defects. From the extracted trap levels and trap depths we conclude that hole traps reside in the middle of the insulator while electron traps are located closer to the SiON/Si interface. Finally, the extracted trap parameters are fully consistent with defect candidates from DFT calculations.

Keyphrases: BTI, Electron trap, NMOS, Single-defects, Trap level, charge trapping, hole trap, planar n channel mosfet, trap position

@booklet{EasyChair:4312,
  author    = {Michael Waltl and Bernhard Stampfer and Gerhard Rzepa and Ben Kaczer and Tibor Grasser},
  title     = {A Single-Trap Study of PBTI in SiON nMOS Transistors},
  howpublished = {EasyChair Preprint 4312},
  year      = {EasyChair, 2020}}