Days: Monday, September 26th Tuesday, September 27th Wednesday, September 28th Thursday, September 29th
View this program: with abstractssession overviewtalk overview
- Panel 1 (Monday): “An Industry-wide Dialog on Chiplets and Heterogeneous Integration”
- Format: three short presentations then an interactive dialog with the audience
- Goal: gather feedback on the HIR roadmap projections and about current and future test standards
- Presentation topics:
- Chiplet trends and drivers (Jeff)
- UCIe (Yervant)
- HIR (Dave Armstrong or Marc Hutner)
- Dialog (guided by Phil Nigh)
- Dialog with the audience topics:
- Are the HIR projections sensible? [e.g. compression ratios]
- What should the test community contribute to UCIe?
- Are the existing HIR-related standards (1838, 1149.10, etc.) sufficient? If not, what infrastructure needs more work (e.g. the details of the FPP in 1838)?
- Does there need to be a new scan test standard for chiplets which otherwise only have short-reach I/Os that can’t drive a tester channel?
- Will hybrid-bonding and other fine-pitch 3D integration techniques be forever beyond the reach of probe access at wafer sort? If so, what will we do instead?
- If self-test in the field becomes a universal part of chip lifecycle management, what does that mean for the ATE companies?
- What are the test roadblocks to the vision of Lego-like integration of chiplets from a wide variety of silicon providers?
View this program: with abstractssession overviewtalk overview
See ITC home page for more information:
14:00 | PEPR: Pseudo-Exhaustive Physical Region Testing PRESENTER: R. D. Blanton |
14:30 | Error Model- A New Way of Doing Fault Simulation PRESENTER: Nirmal Saxena |
15:00 | Using Custom Fault Modelling to Improve Understanding of Silicon Failures PRESENTER: Subhadip Kundu |
14:00 | DeepTPI: Test Point Insertion with Deep Reinforcement Learning PRESENTER: Zhengyuan Shi |
14:30 | Efficient and Robust Resistive Open Defect Detection based on Unsupervised Deep Learning PRESENTER: Yiwen Liao |
15:00 | RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement PRESENTER: Xiaopeng Zhang |
14:00 | Scaling physically aware logic diagnosis to complex high volume 7nm server processors PRESENTER: Bharath Nandakumar |
14:30 | Diagnosing Double Faulty Chains through Failing Bit Separation PRESENTER: Bing-Han Hsieh |
15:00 | Transient Fault Pruning for Effective Candidate Reduction in Functional Debugging PRESENTER: Jing-Jia Liou |
14:00 | Next Generation Design For Testability, Debug and Reliability Using Formal Techniques PRESENTER: Sebastian Huhn |
14:30 | Testing of Analog Circuits using Statistical and Machine Learning Techniques PRESENTER: Supriyo Srimani |
15:00 | AI-Driven Assurance of Hardware IP against Reverse Engineering Attacks PRESENTER: Prabuddha Chakraborty |
Title: Dedicated to Remembering Late Test Giants
Organizer/Moderator: Yervant Zorian, Synopsys
- “Wojciech Maly Memorial”, Anne Meixner; Phil Nigh, Broadcoam
- “Tom W Williams Memorial”, Ray Mercer; Subhasish Mitra, Stanford U
- “Dhiraj K Pradhan Memorial”, Adit Sing, Auburn U; Sandeep Gupta, USC
Title:
Are last century’s test techniques suitable for 21st century Silent Errors?
Organizer(s):
- Dr. Sreejit Chakravarty, Intel Corporation, sreejit.chakravarty@intel.com
- Prof. Subhasish Mitra, Stanford University, USA; subh@stanford.edu
Abstract:
Undetected errors produced by computing systems, also called silent errors, have major consequences ranging from loss of data and services to financial and productivity losses, or even loss of human life. Silent errors produced by computing hardware have been recently identified as a highly critical challenge in several articles by Google, Meta, and New York Times.
The existing HVM test paradigm is falling short. And the test community is helping port the HVM test paradigm to InField Testing to cover for HVM escapes and aging related failures. In this panel, we discuss on whether this is the right approach or if there is a need for a paradigm shift for HVM and InField testing. Several unanswered questions will be touched upon by the panelist. Should we rely on structural, functional, or quasi functional tests? Are HVM fault models like stuck-at etc. the right fault models around which to develop and evaluate the test content to be used for infield testing? Is there a need to rethink how we develop and evaluate online protection schemes like array ECC etc.? How can academia step in to help us select and develop the new paradigm? What kind of infrastructure support do we need from CAD vendors? We are also looking forward to the audience raising additional questions during this discussion.
Panelists
- Rama Govindaraju, Google, USA [10 Minutes]
- Harish Dixit, Facebook, USA [10 Minutes]
- Pradeep Bose, IBM, USA [10 Minutes]
- Subhasish Mitra [5 minutes]
- Sreejit Chakravarty [5 minutes]
- One more TBD
16:00 | Neural Fault Analysis for SAT-based ATPG PRESENTER: Hui-Ling Zhen |
16:30 | Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method PRESENTER: Ya-Chi Cheng |
17:00 | Fault Resilience Techniques for Flash Memory of DNN Accelerators PRESENTER: Shyue-Kung Lu |
16:00 | Automatic Structural Test Generation for Analog Circuits using Neural Twins PRESENTER: Arjun Chaudhuri |
16:30 | DEFCON: Defect Acceleration through Content Optimization PRESENTER: Suriyaprakash Natarajan |
17:00 | Low Capture Power At-Speed Test with Local Hot Spot Analysis to Reduce Over-Test PRESENTER: Ankush Srivastava |
16:00 | A Multi-level Approach to Evaluate the Impact of GPU Permanent Faults on CNN's Reliability PRESENTER: Josie Esteban Rodriguez Condia |
16:30 | Accelerating RRAM Testing with Low-cost Computation-in-Memory based DFT PRESENTER: Abhairaj Singh |
17:00 | Compact Functional Test Generation for Memristive Deep Learning Implementations Using Approximate Gradient Ranking PRESENTER: Soyed Tuhin Ahmed |
Special Session on SLM
Title: “Experiences in Silicon Lifecycle Management”
Moderator: Mehdi
Organizer: Yervant Zorian, Synopsys
Presenters:
- "In-Field System Debug and Silicon Life Cycle Management of Compute Systems”, Sankarn Menon, Rolf Kuehnis and Rakesh Kandula, Intel
- “Sensor Aware Production Testing”, Firooz Massoudi, Ash Patel, Karen Darbinian, Yervant Zorian, Synopsys
- “Empowering Secure and Reliable BIST Solution for Automotive SOCs”, Madhu Sudhana Julapati, Qualcomm
View this program: with abstractssession overviewtalk overview
11:00 | RTL-FSMx: Fast and Accurate Finite State Machine Extraction at the RTL for Security Applications PRESENTER: Rasheed Kibria |
11:30 | TAMED: Transitional Approaches for LFI Resilient State Machine Encoding PRESENTER: Muhtadi Choudhury |
12:00 | Reliability Study of 14 nm Scan Chains and Its Application to Hardware Security PRESENTER: Peilin Song |
11:00 | Language Driven Analytics for Failure Pattern Feedforward and Feedback PRESENTER: Yueling Zeng |
11:30 | Wafer Map Defect Classification Based on the Fusion of Pattern and Pixel Information PRESENTER: Yiwen Liao |
12:00 | WXAI: Wafer Defect Pattern Classification with Explainable Rule Based Decision Tree Methodology PRESENTER: Ken Chau-Cheung Cheng |
12:15 | Yield-Enhanced Probing Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test PRESENTER: Nadun Sinhabahu |
11:00 | Fault Diagnosis for Resistive Random-Access Memory and Monolithic Inter-tier Vias in Monolithic 3D Integration PRESENTER: Shao-Chun Hung |
11:30 | Fault Modeling and Testing of Memristor-Based Spiking Neural Networks PRESENTER: Kuan-Wei Hou |
12:00 | Fault-coverage Maximizing March Tests for Memory Testing PRESENTER: Sandeep Gupta |
12:15 | Enhanced Data Pattern to Detect Defects in Flash Memory Address Decoder PRESENTER: Weng Joe Soh |
Compute-In Memory (CIM) or In-Memory Computing (ICM) is receiving a lot of attention and traction in recent years for many application including Artificial Intelligence (AI) Deep Learning (DL) ones. CIM combines the power of large data storage and concurrent computation in one module thus achieving significant reduction computation energy. Memories used to realize CIM allows not only for data-storage, but also for the execution of logical and arithmetic operations.
Different memory architectures and technologies are being investigated for CIM, including CMOS traditional ones such as SRAM as well as emerging non-volatile ones such as RRAMs. Combining the data-storage memory capability with logic and arithmetic operations introduces significant testing challenges. New fault models and test approaches are needed to enable the use the CIM in silicon products.
The sessions first introduce CIM concept including its the potential applications and different implementation flavors. Then the session covers the testing of SRAM based and RRAM based CIM.
11:00 | In-Memory Computing: History, Overview, Current and Future Directions (abstract) |
11:30 | Testing Computation-in-Memory Architectures Based on Memristive Devices (abstract) |
12:00 | Fully Digital Compute In Memory Design and Test challenges (abstract) |
11:00 | Application of Sampling in Industrial Analog Defect Simulation PRESENTER: Michael Durr |
11:30 | Challenges for High Volume Testing of Embedded IO Interfaces in Disaggregated Microprocessor Products PRESENTER: Esteban J. Garita-Rodríguez |
12:00 | New R&R Methodology in Semiconductor Manufacturing Electrical Testing PRESENTER: Fabio Brembilla |
14:30 | Modeling Challenge Covariances and Design Dependency for Efficient Attacks on Strong PUFs PRESENTER: Hongfei Wang |
15:00 | ADWIL: A Zero-Overhead Analog Device Watermarking Using Inherent IP Features PRESENTER: Upoma Das |
15:30 | Circuit-to-Circuit Attacks in SoCs via Trojan-Infected IEEE 1687 Test Infrastructure PRESENTER: Michele Portolan |
15:45 | Hardware Root of Trust for SSN-based DFT Ecosystems PRESENTER: Janusz Rajski |
14:30 | Functional In-Field Self-Test for Deep Learning Accelerators in Automotive Applications PRESENTER: Yi He |
15:00 | Defect-Directed Stress Testing Based on Inline Inspection Results PRESENTER: Chen He |
15:30 | The impact of on-chip training to adversarial attacks in Memristive Crossbar Arrays PRESENTER: Bijay Raj Paudel |
15:45 | RIBoNN: Designing Robust In-Memory Binary Neural Network Accelerators PRESENTER: Shamik Kundu |
14:30 | Configurable BISR Chain For Fast Repair Data Loading PRESENTER: Wei Zou |
15:00 | Efficient Built-In Self-Repair Techniques with Fine-Grained Redundancy Mechanisms for NAND Flash Memories PRESENTER: Shyue-Kung Lu |
15:30 | Analyzing the Electromigration Challenges of Computation in Resistive Memories PRESENTER: Mehdi Tahoori |
15:45 | DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs PRESENTER: Ze-Wei Pan |
14:30 | An innovative Strategy to Quickly Grade Functional Test Programs PRESENTER: Paolo Bernardi |
15:00 | A Practical Online Error Detection Method for Functional Safety Using Three-Site Implications PRESENTER: Kazuya Ioki |
15:30 | PPA Optimization of Testpoints in Automotive Designs PRESENTER: Brian Foutz |
14:30 | Accurate Failure Rate Prediction Based on Gaussian Process Using WAT Data PRESENTER: Makoto Eiki |
14:45 | 4.5Gsps MIPI D-PHY Receiver Circuit for Automatic Test Equipment PRESENTER: Seongkwan Lee |
15:00 | Optimization of Tests for Managing Silicon Defects in Data Centers PRESENTER: David Lerner |
15:15 | Improving structural coverage of functional tests with checkpoint signature computation PRESENTER: Benjamin Niewenhuis |
15:30 | Zero Trust Approach to IC Manufacturing and Testing PRESENTER: Brian Buras |
15:45 | Virtual Prototyping: Closing the digital gap between product requirements and post-Si verification & validation PRESENTER: Thomas Nirmaier |
16:30 | Latest Cybersecurity regulations, certifications and labeling trends (abstract) |
17:00 | GlobalPlatform: 20 years of Security evaluation on secure components (abstract) |
17:30 | Hardware Security in Internet Connected Platforms and Certification (abstract) |
16:30 | ML-Assisted Bug Emulation Experiments for Post-Silicon Multi-Debug of AMS Circuits PRESENTER: Jun-Yang Lei |
17:00 | A Path Selection Flow for Functional Path Ring Oscillators using Physical Design Data PRESENTER: Tobias Kilian |
17:30 | IEEE P1687.1: Extending the Network Boundaries for Test PRESENTER: Martin Keim |
16:30 | The Importance and Demand Market of SiC Substrate Defect Testing (abstract) |
17:00 | Validation of SPICE models for commercial SiC MOSFETs (abstract) |
17:30 | Practical Design Experiences on a Multi-Voltage-Level Motor Driver System using a Power Inverter (abstract) |
16:30 | Efficient Low Cost Alternative Testing of Analog Crossbar Arrays for Deep Neural Networks PRESENTER: Kwondo Ma |
16:45 | Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing PRESENTER: Kushagra Bhatheja |
17:00 | Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing PRESENTER: Praise Farayola |
17:15 | Transforming an n-Detection Test Set into a Test Set for a Variety of Fault Models |
17:30 | Improvements in the Automated IC Socket Pin Defect Detection PRESENTER: Vijayakumar Thangamariappan |
17:45 | GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs (abstract) PRESENTER: Susmita Sur-Kolay |
View this program: with abstractssession overviewtalk overview
TTTC-PhD Award Presentation
10:30 | Qubit fluctuations in quantum systems (abstract) |
11:15 | Introduction to Quantum Circuit Testing (from test engineers’ perspective) (abstract) |
10:30 | Scan-Based Test Chip Design with XOR-based C-testable Functional Blocks PRESENTER: Duo-Yao Kang |
11:00 | Industry Evaluation of Reversible Scan Chain Diagnosis PRESENTER: Soumya Mittal |
11:30 | A Comprehensive Learning-Based Flow for Cell-Aware Model Generation PRESENTER: Pierre d'Hondt |
11:45 | Runtime Fault Diagnostics for GPU Tensor Cores PRESENTER: Saurabh Hukerikar |
Special Session (on Chiplet)
Title: “Road to Chiplets: UCIe”
Presenters:
- Debendra Das Sharma, Intel
- Yervant Zorian, Synopsys
- Klaus-Dieter Hillinges, Mikael Braun, Advantest
10:30 | Unsupervised Learning-based Early Anomaly Detection in AMS Circuits of Automotive SoCs PRESENTER: Ayush Arunachalam |
11:00 | Just-Enough Stress Test for Infant-Mortality Screening Using Speed Binning (abstract) PRESENTER: Shi-Yu Huang |
11:30 | Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65 nm CMOS Technologies PRESENTER: Pin-Tang Wang |
10:30 | Probeless DfT Scheme for Testing 20k I/Os of an Automotive Micro-LED Headlamp Driver IC PRESENTER: Hans Martin von Staudt |
11:00 | Reusing IEEE 1687-Compatible Instruments and Sub-Networks over a System Bus PRESENTER: Erik Larsson |
11:30 | Multi-die Parallel Test Fabric for Scalability and Pattern Reusability PRESENTER: Arani Sinha |
13:30 | Compression-Aware ATPG PRESENTER: Xing Wang |
14:00 | DIST: Deterministic In-System Test with X-masking PRESENTER: Janusz Rajski |
14:30 | Test Generation for an Iterative Design Flow with RTL Changes PRESENTER: Jerin Joe |
13:30 | Understand VDDmin Failures for Improved Testing of Timing Marginalities |
14:00 | ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption PRESENTER: Wei-Chen Lin |
14:30 | Comprehensive Power-Aware ATPG methodology for complex low-power Designs PRESENTER: Likith Kumar Manchukonda |
Organizer: Nir Maor, Qualcomm
Moderator: Yervant Zorian, Synopsys
Panelists
- Sohrab Aftabjahani, Intel
- Luca Di Mauro, Arm
- Joytika Athavale, Nvidia
- Nir Maor, Qualcomm
- Jason M Fung, Intel
- Meirav Nitzan, Synopsys
The three top-ranked papers of ITC-India 2022 will be presented in this session.
- Best Paper Award: TSV BIST Repair : Design-for-Test Challenges and Emerging Solution for 3D Stacked IC’s
- Authors: Akkapolu Sankararao, Vaishnavi G and Malige Sandya Rani
- Author Email IDs: Sankararao.Akkapolu@amd.com; VAISHNAVI.G@amd.com; SandyaRani.Malige@amd.com
- Honorable Mention Paper 1 - Selective Multiple Capture Test (SMART) XLBIST
- Authors: Peter Wohl, John Waicukauski, Anushree Bhat, Vijay Kumar K S and Rajit Karmakar
- Author Email IDs: wohl@synopsys.com; johnwaic@synopsys.com, anushrb@synopsys.com, vijak@synopsys.com, rajitk@synopsys.com
- Honorable Mention Paper 2 - Transfer-Matrix Abstractions to Analyze the Effect of Manufacturing Variations in Silicon Photonic Circuits - Honorable Paper 2
- Authors: Pratishtha Agnihotri, Priyank Kalla and Steve Blair
- Author Email IDs: pratishtha.agnihotri@utah.edu, kalla@ece.utah.edu, blair@ece.utah.edu
13:30 | TSV BIST Repair: Design-For-Test Challenges and Emerging Solution for 3D Stacked IC’s (abstract) PRESENTER: Sankararao Akkapolu |
14:00 | Selective Multiple Capture Test (SMART) XLBIST (abstract) PRESENTER: Peter Wohl |
14:30 | Transfer-Matrix Abstractions to Analyze the Effect of Manufacturing Variations in Silicon Photonic Circuits (abstract) PRESENTER: Pratishtha Agnihotri |