• Panel 1 (Monday): “An Industry-wide Dialog on Chiplets and Heterogeneous Integration”
  • Format: three short presentations then an interactive dialog with the audience
  • Goal: gather feedback on the HIR roadmap projections and about current and future test standards
  • Presentation topics:
    • Chiplet trends and drivers (Jeff)
    • UCIe (Yervant)
    • HIR (Dave Armstrong or Marc Hutner)
    • Dialog (guided by Phil Nigh)
  • Dialog with the audience topics:
    • Are the HIR projections sensible?  [e.g. compression ratios]
    • What should the test community contribute to UCIe?
    • Are the existing HIR-related standards (1838, 1149.10, etc.) sufficient?  If not, what infrastructure needs more work (e.g. the details of the FPP in 1838)?
    • Does there need to be a new scan test standard for chiplets which otherwise only have short-reach I/Os that can’t drive a tester channel?
    • Will hybrid-bonding and other fine-pitch 3D integration techniques be forever beyond the reach of probe access at wafer sort?  If so, what will we do instead?
    • If self-test in the field becomes a universal part of chip lifecycle management, what does that mean for the ATE companies?
    • What are the test roadblocks to the vision of Lego-like integration of chiplets from a wide variety of silicon providers?

See ITC home page for more information:

http://www.itctestweek.org/2022-keynote-talks/

Title: Dedicated to Remembering Late Test Giants

Organizer/Moderator: Yervant Zorian, Synopsys

• “Wojciech Maly Memorial”, Anne Meixner; Phil Nigh, Broadcoam
• “Tom W Williams Memorial”, Ray Mercer; Subhasish Mitra, Stanford U
• “Dhiraj K Pradhan Memorial”, Adit Sing, Auburn U; Sandeep Gupta, USC

Title:

Are last century’s test techniques suitable for 21^st century Silent Errors?

Organizer(s):

• Dr. Sreejit Chakravarty, Intel Corporation, sreejit.chakravarty@intel.com
• Prof. Subhasish Mitra, Stanford University, USA; subh@stanford.edu

Abstract:

Undetected errors produced by computing systems, also called silent errors, have major consequences ranging from loss of data and services to financial and productivity losses, or even loss of human life. Silent errors produced by computing hardware have been recently identified as a highly critical challenge in several articles by Google, Meta, and New York Times.

The existing HVM test paradigm is falling short. And the test community is helping port the HVM test paradigm to InField Testing to cover for HVM escapes and aging related failures. In this panel, we discuss on whether this is the right approach or if there is a need for a paradigm shift for HVM and InField testing. Several unanswered questions will be touched upon by the panelist. Should we rely on structural, functional, or quasi functional tests? Are HVM fault models like stuck-at etc. the right fault models around which to develop and evaluate the test content to be used for infield testing? Is there a need to rethink how we develop and evaluate online protection schemes like array ECC etc.?  How can academia step in to help us select and develop the new paradigm? What kind of infrastructure support do we need from CAD vendors? We are also looking forward to the audience raising additional questions during this discussion.

Panelists

• Rama Govindaraju, Google, USA [10 Minutes]
• Harish Dixit, Facebook, USA [10 Minutes]
• Pradeep Bose, IBM, USA [10 Minutes]
• Subhasish Mitra [5 minutes]
• Sreejit Chakravarty [5 minutes]
• One more TBD

  Special Session on SLM

                Title: “Experiences in Silicon Lifecycle Management”

                Moderator: Mehdi

                Organizer: Yervant Zorian, Synopsys

                Presenters:

• "In-Field System Debug and Silicon Life Cycle Management of Compute Systems”, Sankarn Menon, Rolf Kuehnis and Rakesh Kandula, Intel
• “Sensor Aware Production Testing”, Firooz Massoudi, Ash Patel, Karen Darbinian, Yervant Zorian, Synopsys
• “Empowering Secure and Reliable BIST Solution for Automotive SOCs”, Madhu Sudhana Julapati, Qualcomm

See

http://www.itctestweek.org/2022-keynote-talks/

See: http://www.itctestweek.org/2022-keynote-talks/

TTTC-PhD Award Presentation

See:

http://www.itctestweek.org/2022-keynote-talks/

     Special Session (on Chiplet)

              Title:  “Road to Chiplets: UCIe”

              Presenters:

-          Debendra Das Sharma, Intel

-          Yervant Zorian, Synopsys

-          Klaus-Dieter Hillinges, Mikael Braun, Advantest 

  Organizer: Nir Maor, Qualcomm

                    Moderator: Yervant Zorian, Synopsys

Panelists

• Sohrab Aftabjahani, Intel
• Luca Di Mauro, Arm
• Joytika Athavale, Nvidia
• Nir Maor, Qualcomm
• Jason M Fung, Intel
• Meirav Nitzan, Synopsys