ITC 2022: INTERNATIONAL TEST CONFERENCE 2022
PROGRAM FOR THURSDAY, SEPTEMBER 29TH
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09:00-09:10 Session Award: Award Presentation

TTTC-PhD Award Presentation

Chair:
Yervant Zorian (Synopsys, United States)
10:30-12:00 Session A6: Special Session on Test of Quantum Circuits
Chair:
James Li (National Taiwan University, Taiwan)
10:30
Malcolm Carroll (IBM, United States)
Qubit fluctuations in quantum systems

ABSTRACT. To be filled in.

11:15
James Li (National Taiwan University, Taiwan)
Introduction to Quantum Circuit Testing (from test engineers’ perspective)

ABSTRACT. In this talk, we will first introduce basic concepts about QC from test engineers’ perspective. Then, we will introduce error, noise, and faults for quantum circuits. Finally, we will introduce a new test generation technique for quantum circuits.

10:30-12:00 Session B6: Scan-Based Learning and Diagnosis
Chair:
Wu-Tung Cheng (Siemens EDA, United States)
10:30
Yan-Fu Chen (Dept. EE, National Cheng Kung University, Tainan, Taiwan, Taiwan)
Duo-Yao Kang (Dept. EE, National Cheng Kung University, Tainan, Taiwan, Taiwan)
Kuen-Jong Lee (Dept. EE, National Cheng Kung University, Tainan, Taiwan, Taiwan)
Scan-Based Test Chip Design with XOR-based C-testable Functional Blocks
PRESENTER: Duo-Yao Kang
11:00
Soumya Mittal (Qualcomm, United States)
Szczepan Urban (Siemens EDA, Poland)
Kun Young Chung (Qualcomm, United States)
Jakub Janicki (Siemens EDA, Poland)
Wu-Tung Cheng (Siemens EDA, United States)
Martin Parley (Qualcomm, United States)
Manish Sharma (Siemens EDA, United States)
Shaun Nicholson (Qualcomm, United States)
Industry Evaluation of Reversible Scan Chain Diagnosis
PRESENTER: Soumya Mittal
11:30
Pierre d'Hondt (LIRMM / STMicroelectronics, France)
Aymen Ladhar (STMicroelectronics, France)
Patrick Girard (LIRMM, France)
Arnaud Virazel (LIRMM, France)
A Comprehensive Learning-Based Flow for Cell-Aware Model Generation
PRESENTER: Pierre d'Hondt
11:45
Saurabh Hukerikar (NVIDIA, United States)
Nirmal Saxena (NVIDIA, United States)
Runtime Fault Diagnostics for GPU Tensor Cores
10:30-12:00 Session C6: Special Session on Chiplet Integration

     Special Session (on Chiplet)

              Title:  “Road to Chiplets: UCIe”

              Presenters:

-          Debendra Das Sharma, Intel

-          Yervant Zorian, Synopsys

-          Klaus-Dieter Hillinges, Mikael Braun, Advantest 

Chair:
Yervant Zorian (Synopsys, United States)
10:30-12:00 Session D6: Automotive II
Chair:
Chen He (NXP, United States)
10:30
Ayush Arunachalam (University of Texas at Dallas, United States)
Athulya Kizhakkayil (University of Texas at Dallas, United States)
Shamik Kundu (University of Texas at Dallas, United States)
Arnab Raha (Intel Corporation, United States)
Suvadeep Banerjee (Intel Corporation, United States)
Xiankun Jin (NXP Semiconductors, United States)
Fei Su (Intel Corporation, United States)
Kanad Basu (University of Texas at Dallas, United States)
Unsupervised Learning-based Early Anomaly Detection in AMS Circuits of Automotive SoCs
11:00
Chen-Lin Tsai (National Tsing Hua University, Taiwan)
Shi-Yu Huang (National Tsing Hua University, Taiwan)
Just-Enough Stress Test for Infant-Mortality Screening Using Speed Binning
PRESENTER: Shi-Yu Huang

ABSTRACT. Stress test has become increasingly more important to support reliability screening for safety-critical ICs. However, the amount of stress time that needs to be applied to an IC product is not only hard-to-decide but also too time-consuming. This paper formulates a Just-Enough Stress Test (JEST) method so that the stress time can be dramatically reduced without missing out the weak devices with infant mortality tendency. Experimental results on examples based on previously proposed failure time model in the literature indicate that the stress test time could be slashed significantly by an order of magnitude.

11:30
Ming-Hsien Hsiao (National Yang Ming Chiao Tung University, Taiwan)
Pin-Tang Wang (National Yang Ming Chiao Tung University, Taiwan)
Chia-Wei Liang (National Yang Ming Chiao Tung University, Taiwan)
Hung-Pin Wen (National Yang Ming Chiao Tung University, Taiwan)
Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65 nm CMOS Technologies
PRESENTER: Pin-Tang Wang
10:30-12:00 Session E6: Industrial Practices III
Chair:
Ke Peng (ARM, United States)
10:30
Hans Martin von Staudt (Dialog Semiconductor, A Renesas Company, Germany)
Luai Elnawawy (Dialog Semiconductor, A Renesas Company, Germany)
Sarah Wang (Dialog Semiconductor, A Renesas Company, United States)
Larry Ping (Dialog Semiconductor, A Renesas Company, United States)
Jung Woo Choi (Dialog Semiconductor, A Renesas Company, United States)
Probeless DfT Scheme for Testing 20k I/Os of an Automotive Micro-LED Headlamp Driver IC
11:00
Farrokh Ghani Zadegan (Ericsson, Sweden)
Zilin Zhang (Ericsson, Sweden)
Kim Petersén (Ericsson, Sweden)
Erik Larsson (Lund University, Sweden)
Reusing IEEE 1687-Compatible Instruments and Sub-Networks over a System Bus
PRESENTER: Erik Larsson
11:30
Arani Sinha (Intel, United States)
Yonsang Cho (Intel, United States)
Jon Easter (Intel, United States)
Meizel V. Leiva Rojas (Intel, Costa Rica)
Multi-die Parallel Test Fabric for Scalability and Pattern Reusability
PRESENTER: Arani Sinha
13:30-15:00 Session A7: Test Generation
Chair:
Shyue-Kung Lu (National Taiwan University of Science and Technology, Taiwan)
13:30
Xing Wang (University of Chinese Academy of Sciences, Academy of mathematics and Systems Science, China)
Zezhong Wang (HiSilicon Technologies Co., Ltd., China)
Naixing Wang (HiSilicon Technologies Co., Ltd., China)
Weiwei Zhang (HiSilicon Technologies Co., Ltd., China)
Yu Huang (HiSilicon Technologies Co., Ltd., China)
Compression-Aware ATPG
PRESENTER: Xing Wang
14:00
Jerzy Tyszer (Poznan University of Technology, Poland)
Grzegorz Mrugalski (Siemens Digital Industries Software, Poland)
Janusz Rajski (Siemens Digital Industries Software, United States)
Bartosz Wlodarczak (Poznan University of Technology, Poland)
DIST: Deterministic In-System Test with X-masking
PRESENTER: Janusz Rajski
14:30
Jerin Joe (Purdue University, United States)
Nilanjan Mukherjee (Siemens Digital Industries Software, United States)
Irith Pomeranz (Purdue University, United States)
Janusz Rajski (Siemens Digital Industries Software, United States)
Test Generation for an Iterative Design Flow with RTL Changes
PRESENTER: Jerin Joe
13:30-15:00 Session B7: Low-Power and Test
Chair:
Charles H.-P. Wen (National Chiao Tung University, Taiwan)
13:30
Adit Singh (Auburn University, United States)
Understand VDDmin Failures for Improved Testing of Timing Marginalities
14:00
Wei-Chen Lin (National Taiwan University, Taiwan)
Chun Chen (National Taiwan University, Taiwan)
Chao-Ho Hsieh (National Taiwan University, Taiwan)
James Chien-Mo Li (National Taiwan University, Taiwan)
Eric Jia-Wei Fang (MediaTek Inc., Taiwan)
Sung S.-Y. Hsueh (MediaTek inc., Taiwan)
ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
PRESENTER: Wei-Chen Lin
14:30
Likith Kumar Manchukonda (Synopsys Inc, United States)
Elddie Tsai (Synopsys Inc, Taiwan)
Khader Abdel-Hafez (Synopsys Inc, United States)
Michael Dsouza (Synopsys Inc., United States)
Karthikeyan Natarajan (Synopsys Inc, United States)
Smith Lai (MediaTek, Taiwan)
Wenhao Hsueh (MediaTek, United States)
Comprehensive Power-Aware ATPG methodology for complex low-power Designs
13:30-15:00 Session D7: Panel 4: Automotive

  Organizer: Nir Maor, Qualcomm

                    Moderator: Yervant Zorian, Synopsys

Panelists

  • Sohrab Aftabjahani, Intel
  • Luca Di Mauro, Arm
  • Joytika Athavale, Nvidia
  • Nir Maor, Qualcomm
  • Jason M Fung, Intel
  • Meirav Nitzan, Synopsys 
Chair:
Yervant Zorian (Synopsys, United States)
13:30-15:00 Session E7: Industrial Practices from ITC India

The three top-ranked papers of ITC-India 2022 will be presented in this session.

Chair:
Peter Wohl (Synopsys, United States)
13:30
Sankararao Akkapolu (AMD INDIA PRIVATE LIMITED, BENGALURU, India)
Vaishnavi G (AMD INDIA PRIVATE LIMITED, BENGALURU, India)
Sandya Rani Malige (AMD INDIA PRIVATE LIMITED, BENGALURU, India)
TSV BIST Repair: Design-For-Test Challenges and Emerging Solution for 3D Stacked IC’s

ABSTRACT. The efficient methodology to increase the yield and performance of 3D Stacked Integrated Circuits (3D SICs) using TSV BIST Repair mechanism addressed in this paper. The complete analysis of the proposed TSV BIST repair methodology shows significant improvement of 14.5% yield and test cost by detecting all eminent defective chips.

14:00
Peter Wohl (Synopsys, United States)
John Waicukauski (Synopsys, United States)
Vijay Kumar K S (Synopsys, India)
Anushree Bhat (Synopsys, India)
Rajit Karmakar (Synopsys, India)
Selective Multiple Capture Test (SMART) XLBIST
PRESENTER: Peter Wohl

ABSTRACT. Logic BIST (LBIST) is increasingly deployed to realize test cost reduction and silicon life-cycle management. X-tolerant LBIST (XLBIST) expanded applicability to almost any design in the presence of unknown (X) values. We introduce ATPG-driven multiple capture-clock selection which greatly increases XLBIST coverage per pattern.

14:30
Pratishtha Agnihotri (The University of Utah, United States)
Priyank Kalla (The University of Utah, United States)
Steve Blair (The University of Utah, United States)
Transfer-Matrix Abstractions to Analyze the Effect of Manufacturing Variations in Silicon Photonic Circuits

ABSTRACT. This paper describes a methodology and abstraction models to evaluate the effect of variations in the dimensions of waveguides, spacing, and modulation parameters on Si-photonic circuits. The method is validated by experiments performed on conventional SOI waveguide-based devices and circuits.