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TTTC-PhD Award Presentation
10:30 | Scan-Based Test Chip Design with XOR-based C-testable Functional Blocks PRESENTER: Duo-Yao Kang |
11:00 | Industry Evaluation of Reversible Scan Chain Diagnosis PRESENTER: Soumya Mittal |
11:30 | A Comprehensive Learning-Based Flow for Cell-Aware Model Generation PRESENTER: Pierre d'Hondt |
11:45 | Runtime Fault Diagnostics for GPU Tensor Cores PRESENTER: Saurabh Hukerikar |
Special Session (on Chiplet)
Title: “Road to Chiplets: UCIe”
Presenters:
- Debendra Das Sharma, Intel
- Yervant Zorian, Synopsys
- Klaus-Dieter Hillinges, Mikael Braun, Advantest
10:30 | Unsupervised Learning-based Early Anomaly Detection in AMS Circuits of Automotive SoCs PRESENTER: Ayush Arunachalam |
11:00 | Just-Enough Stress Test for Infant-Mortality Screening Using Speed Binning PRESENTER: Shi-Yu Huang ABSTRACT. Stress test has become increasingly more important to support reliability screening for safety-critical ICs. However, the amount of stress time that needs to be applied to an IC product is not only hard-to-decide but also too time-consuming. This paper formulates a Just-Enough Stress Test (JEST) method so that the stress time can be dramatically reduced without missing out the weak devices with infant mortality tendency. Experimental results on examples based on previously proposed failure time model in the literature indicate that the stress test time could be slashed significantly by an order of magnitude. |
11:30 | Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65 nm CMOS Technologies PRESENTER: Pin-Tang Wang |
10:30 | Probeless DfT Scheme for Testing 20k I/Os of an Automotive Micro-LED Headlamp Driver IC PRESENTER: Hans Martin von Staudt |
11:00 | Reusing IEEE 1687-Compatible Instruments and Sub-Networks over a System Bus PRESENTER: Erik Larsson |
11:30 | Multi-die Parallel Test Fabric for Scalability and Pattern Reusability PRESENTER: Arani Sinha |
13:30 | Compression-Aware ATPG PRESENTER: Xing Wang |
14:00 | DIST: Deterministic In-System Test with X-masking PRESENTER: Janusz Rajski |
14:30 | Test Generation for an Iterative Design Flow with RTL Changes PRESENTER: Jerin Joe |
13:30 | Understand VDDmin Failures for Improved Testing of Timing Marginalities |
14:00 | ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption PRESENTER: Wei-Chen Lin |
14:30 | Comprehensive Power-Aware ATPG methodology for complex low-power Designs PRESENTER: Likith Kumar Manchukonda |
Organizer: Nir Maor, Qualcomm
Moderator: Yervant Zorian, Synopsys
Panelists
- Sohrab Aftabjahani, Intel
- Luca Di Mauro, Arm
- Joytika Athavale, Nvidia
- Nir Maor, Qualcomm
- Jason M Fung, Intel
- Meirav Nitzan, Synopsys
The three top-ranked papers of ITC-India 2022 will be presented in this session.
- Best Paper Award: TSV BIST Repair : Design-for-Test Challenges and Emerging Solution for 3D Stacked IC’s
- Authors: Akkapolu Sankararao, Vaishnavi G and Malige Sandya Rani
- Author Email IDs: Sankararao.Akkapolu@amd.com; VAISHNAVI.G@amd.com; SandyaRani.Malige@amd.com
- Honorable Mention Paper 1 - Selective Multiple Capture Test (SMART) XLBIST
- Authors: Peter Wohl, John Waicukauski, Anushree Bhat, Vijay Kumar K S and Rajit Karmakar
- Author Email IDs: wohl@synopsys.com; johnwaic@synopsys.com, anushrb@synopsys.com, vijak@synopsys.com, rajitk@synopsys.com
- Honorable Mention Paper 2 - Transfer-Matrix Abstractions to Analyze the Effect of Manufacturing Variations in Silicon Photonic Circuits - Honorable Paper 2
- Authors: Pratishtha Agnihotri, Priyank Kalla and Steve Blair
- Author Email IDs: pratishtha.agnihotri@utah.edu, kalla@ece.utah.edu, blair@ece.utah.edu
13:30 | TSV BIST Repair: Design-For-Test Challenges and Emerging Solution for 3D Stacked IC’s PRESENTER: Sankararao Akkapolu ABSTRACT. The efficient methodology to increase the yield and performance of 3D Stacked Integrated Circuits (3D SICs) using TSV BIST Repair mechanism addressed in this paper. The complete analysis of the proposed TSV BIST repair methodology shows significant improvement of 14.5% yield and test cost by detecting all eminent defective chips. |
14:00 | Selective Multiple Capture Test (SMART) XLBIST PRESENTER: Peter Wohl ABSTRACT. Logic BIST (LBIST) is increasingly deployed to realize test cost reduction and silicon life-cycle management. X-tolerant LBIST (XLBIST) expanded applicability to almost any design in the presence of unknown (X) values. We introduce ATPG-driven multiple capture-clock selection which greatly increases XLBIST coverage per pattern. |
14:30 | Transfer-Matrix Abstractions to Analyze the Effect of Manufacturing Variations in Silicon Photonic Circuits PRESENTER: Pratishtha Agnihotri ABSTRACT. This paper describes a methodology and abstraction models to evaluate the effect of variations in the dimensions of waveguides, spacing, and modulation parameters on Si-photonic circuits. The method is validated by experiments performed on conventional SOI waveguide-based devices and circuits. |