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11:00-12:30 Session A3: HW Security I
Jennifer Dworak (Southern Methodist University, United States)
Rasheed Kibria (University of Florida, United States)
M Sazadur Rahman (University of Florida, United States)
Farimah Farahmandi (University of Florida, United States)
Mark Tehranipoor (University of Florida, United States)
RTL-FSMx: Fast and Accurate Finite State Machine Extraction at the RTL for Security Applications
PRESENTER: Rasheed Kibria
Muhtadi Choudhury (University of Florida, United States)
Minyan Gao (University of Florida, United States)
Shahin Tajik (Worcester Polytechnic Institute, United States)
Domenic Forte (University of Florida, United States)
TAMED: Transitional Approaches for LFI Resilient State Machine Encoding
Franco Stellari (IBM, United States)
Peilin Song (IBM, United States)
Reliability Study of 14 nm Scan Chains and Its Application to Hardware Security
PRESENTER: Peilin Song
11:00-12:30 Session B3: Latest on Wafer Map Analytics
James Li (National Taiwan University, Taiwan)
Min Jian Yang (University of California Santa Barbara, United States)
Yueling Zeng (University of California Santa Barbara, United States)
Li-C. Wang (UCSB, United States)
Language Driven Analytics for Failure Pattern Feedforward and Feedback
PRESENTER: Yueling Zeng
Yiwen Liao (University of Stuttgart, Germany)
Raphaël Latty (Advantest Europe GmbH, Germany)
Paul R. Genssler (University of Stuttgart, Germany)
Hussam Amrouch (University of Stuttgart, Germany)
Bin Yang (University of Stuttgart, Germany)
Wafer Map Defect Classification Based on the Fusion of Pattern and Pixel Information
Ken Chau-Cheung Cheng (NXP Semiconductors Taiwan Ltd., Taiwan)
Katherine Shu-Min Li (National Sun Yat-Sen University, Taiwan)
Sying-Jyan Wang (National Chung Hsing University, Taiwan)
Andrew Yi-Ann Huang (NXP Semiconductors Taiwan Ltd., Taiwan)
Chen-Shiun Lee (NXP Semiconductors Taiwan Ltd., Taiwan)
Leon Li-Yang Chen (NXP Semiconductors Taiwan Ltd., Taiwan)
Peter Yi-Yu Liao (NXP Semiconductors Taiwan Ltd., Taiwan)
Nova Cheng-Yen Tsai (NXP Semiconductors Taiwan Ltd., Taiwan)
WXAI: Wafer Defect Pattern Classification with Explainable Rule Based Decision Tree Methodology
Nadun Sinhabahu (NXP Semiconductors Taiwan Ltd., Taiwan)
Katherine Shu-Min Li (National Sun Yat-Sen University, Taiwan)
Jian Rui Wang (NXP Semiconductors Taiwan Ltd., Taiwan)
Jian-De Li (National Chung Hsing University, Taiwan)
Sying-Jyan Wang (National Chung Hsing University, Taiwan)
Yield-Enhanced Probing Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test
PRESENTER: Nadun Sinhabahu
11:00-12:30 Session C3: Memory Test/Diagnosis
Shyue-Kung Lu (National Taiwan University of Science and Technology, Taiwan)
Shao-Chun Hung (Duke University, United States)
Arjun Chaudhuri (Duke University, United States)
Sanmitra Banerjee (Duke University, United States)
Krishnendu Chakrabarty (Duke University, United States)
Fault Diagnosis for Resistive Random-Access Memory and Monolithic Inter-tier Vias in Monolithic 3D Integration
PRESENTER: Shao-Chun Hung
Kuan-Wei Hou (National Tsing Hua University, Taiwan)
Hsueh-Hung Cheng (National Tsing Hua University, Taiwan)
Chi Tung (National Tsing Hua University, Taiwan)
Cheng-Wen Wu (National Tsing Hua University, Taiwan)
Juin-Ming Lu (Industrial Technology Research Institute, Taiwan)
Fault Modeling and Testing of Memristor-Based Spiking Neural Networks
Ryan Feng (University of Southern California, United States)
Yunkun Lin (University of Southern California, United States)
Yunfei Lou (University of Southern California, United States)
Lei Gao (University of Southern California, United States)
Vaibhav Gera (University of Southern California, United States)
Boxuan Li (University of Southern California, United States)
Vennela Chowdary Nekkanti (University of Southern California, United States)
Aditya Rajendra Pharande (University of Southern California, United States)
Kunal Sheth (University of Southern California, United States)
Meghana Thommondru (University of Southern California, United States)
Guizhong Ye (University of Southern California, United States)
Sandeep Gupta (University of Southern California, United States)
Fault-coverage Maximizing March Tests for Memory Testing
PRESENTER: Sandeep Gupta
Weng Joe Soh (NXP Semiconductors, Malaysia)
Chen He (NXP Semiconductors, United States)
Enhanced Data Pattern to Detect Defects in Flash Memory Address Decoder
11:00-12:30 Session D3: Special Session on Compute-In-Memory

Compute-In Memory (CIM) or In-Memory Computing (ICM) is receiving a lot of attention and traction in recent years for many application including Artificial Intelligence (AI) Deep Learning (DL) ones. CIM combines the power of large data storage and concurrent computation in one module thus achieving significant reduction computation energy.  Memories used to realize CIM allows not only for data-storage, but also for the execution of logical and arithmetic operations.  

Different memory architectures and technologies are being investigated for CIM, including CMOS traditional ones such as SRAM as well as emerging non-volatile ones such as RRAMs.  Combining the data-storage memory capability with logic and arithmetic operations introduces significant testing challenges. New fault models and test approaches are needed to enable the use the CIM in silicon products.

The sessions first introduce CIM concept including its the potential applications and different implementation flavors. Then the session covers the testing of SRAM based and RRAM based CIM.

Saman Adham (TSMC, Canada)
Narish Shanhbag (UIUC, United States)
In-Memory Computing: History, Overview, Current and Future Directions

ABSTRACT. In-memory computing (IMC) has become an active area of research in the circuits community. IMC addresses the energy and latency costs of memory accesses that dominate when processing AI workloads. It does so by transforming the conventional memory read access into one that computes AI functions of data by employing analog computations. As a result, IMC chips have demonstrated > 100X reduction in the energy-delay product over equivalent von Neumann architectures at ISO-accuracy. However, today, bank-level IMC designs have matured and efficiency gains have stagnated. This talk will provide a historical overview of the technology, describe current trends, and identify future opportunities and challenges in deploying IMCs in emerging applications.

Said Hamdioui (Delft University of Technology, The Netherlands, Netherlands)
Testing Computation-in-Memory Architectures Based on Memristive Devices

ABSTRACT. Testing of RRAM based CIM devices is fundamentally different from testing traditional memories. Non-volatile memories used to realize CIM concepts allows not only for data-storage (i.e., memory configuration), but also for the execution of logical and arithmetic operations (i.e., computing configuration). Therefore, not only significant design changes are needed in memory array and/or in the peripheral circuits, but also new fault models and test approaches are needed. Moreover, RRAM based CIM makes use of non-linear non-volatile devices making the defect modeling with traditional linear resistor inappropriate for such device defects. Hence, even the way of doing defect modeling has to change. This talk discusses testing for RRAM based CIM and highlights the test challenges and how testing CIM dies is different from the traditional way of testing logic and memory. Methods for defect modeling, fault modeling, and test development will be discussed. The talk demonstrates that unique faults can occur in the CIM die while in the computation configuration, and that these faults cannot be detected by just testing the CIM die in the memory configuration. Moreover, it shows that testing the CIM die in the computation configuration reduces the overall test time while improving the outgoing product quality.

Saman Adham (TSMC, Taiwan)
Fully Digital Compute In Memory Design and Test challenges

ABSTRACT. Computing-in-memory (CIM) is being widely explored to minimize power consumption in data movement and multiply-and-accumulate (MAC) for edge-AI devices. Although most prior work focuses on analog-based CIM (ACIM) to leverage the BL charge/discharge operation, the lack of accuracy caused by transistor variation and the ADC is a concern. In contrast, a digital-based CIM (DCIM) approach realizes enough accuracy and flexibility for various input and weight bit widths while also benefiting from technology scaling. This presentation provides an overview of SRAM based DCIM macro using 1R1W bit-cell and cascaded adders. The DCIM macro can realize simultaneous MAC + write operations and wide range dynamic voltage-frequency. A programmable BIST based test solution is designed and implemented for the DCIM macro. Special features were designed in the BIST engine to enable DCIM macro performance and power characterization. Fault simulation shows the BIST achieved > 99% test coverage. The BIST test results were validate on a test chip.

11:00-12:30 Session E3: Industrial Practices I
Phil Nigh (Broadcom, United States)
Mayukh Bhattacharya (Synopsys, United States)
Beatrice Solignac (Synopsys, France)
Michael Durr (Synopsys, United States)
Application of Sampling in Industrial Analog Defect Simulation
PRESENTER: Michael Durr
Esteban J. Garita-Rodríguez (Intel, Costa Rica)
Renato Rimolo-Donadio (Intel, Costa Rica)
Rafael Zamora-Salazar (Intel, Costa Rica)
Challenges for High Volume Testing of Embedded IO Interfaces in Disaggregated Microprocessor Products
Alberto Pagani (STMicroelectronics, Italy)
Fabio Brembilla (STMicroelectronics, Italy)
New R&R Methodology in Semiconductor Manufacturing Electrical Testing
PRESENTER: Fabio Brembilla
12:30-14:30Posters Presented on Exhibit Floor (During Lunch Hours)
14:30-16:00 Session A4: HW Security II
Peilin Song (IBM, United States)
Hongfei Wang (Huazhong University of Science and Technology, China)
Wei Liu (Huazhong University of Science and Technology, China)
Hai Jin (Huazhong University of Science and Technology, China)
Yu Chen (Huazhong University of Science and Technology, China)
Wenjie Cai (Huazhong University of Science and Technology, China)
Modeling Challenge Covariances and Design Dependency for Efficient Attacks on Strong PUFs
PRESENTER: Hongfei Wang
Upoma Das (University of Florida, United States)
Md Rafid Muttaki (University of Florida, United States)
Mark M. Tehranipoor (University of Florida, United States)
Farimah Farahmandi (University of Florida, United States)
ADWIL: A Zero-Overhead Analog Device Watermarking Using Inherent IP Features
Michele Portolan (TIMA, France)
Antonios Pavlidis (Sorbonne Université LIP6, France)
Giorgio Di Natale (CNRS, France)
Eric Faehn (ST Microelectronics, France)
Haralampos Stratigopoulos (Sorbonne Université LIP6, France)
Circuit-to-Circuit Attacks in SoCs via Trojan-Infected IEEE 1687 Test Infrastructure
PRESENTER: Michele Portolan
Jerzy Tyszer (Poznan University of Technology, Poland)
Janusz Rajski (Siemens Digital Industries Software, United States)
Maciej Trawka (Siemens Digital Industries Software, Poland)
Bartosz Włodarczak (Poznan University of Technology, Poland)
Hardware Root of Trust for SSN-based DFT Ecosystems
PRESENTER: Janusz Rajski
14:30-16:00 Session B4: Test of HW Accelerators II
Sandeep Gupta (University of Southern California, United States)
Takumi Uezono (Hitachi, Japan)
Yi He (University of Chicago, United States)
Yanjing Li (University of Chicago, United States)
Functional In-Field Self-Test for Deep Learning Accelerators in Automotive Applications
Chen He (NXP Semiconductors, United States)
Paul Grosch (NXP Semiconductors, United States)
Onder Anilturk (NXP Semiconductors, United States)
Joyce Witowski (NXP Semiconductors, United States)
Carl Ford (NXP Semiconductors, United States)
Rahul Kalyan (NXP Semiconductors, United States)
John Robinson (KLA Corporation, United States)
David Price (KLA Corporation, United States)
Jay Rathert (KLA Corporation, United States)
Barry Saville (KLA Corporation, United States)
Defect-Directed Stress Testing Based on Inline Inspection Results
Bijay Raj Paudel (Southern Illinois University Carbondale, United States)
Spyros Tragoudas (Southern Illinois University Carbondale, United States)
The impact of on-chip training to adversarial attacks in Memristive Crossbar Arrays
PRESENTER: Bijay Raj Paudel
Shamik Kundu (The University of Texas at Dallas, United States)
Akul Malhotra (Purdue University, United States)
Arnab Raha (Intel Corporation, United States)
Sumeet Gupta (Purdue University, United States)
Kanad Basu (The University of Texas at Dallas, United States)
RIBoNN: Designing Robust In-Memory Binary Neural Network Accelerators
PRESENTER: Shamik Kundu
14:30-16:00 Session C4: Memory Test/Repair
Jongsin Yun (Siemens, United States)
Wei Zou (Siemens EDA, United States)
Benoit Nadeau-Dostie (Siemens EDA, Canada)
Configurable BISR Chain For Fast Repair Data Loading
Shyue-Kung Lu (National Taiwan University of Science and Technology, Taiwan)
Shi-Chun Tseng (National Taiwan University of Science and Technology, Taiwan)
Kohei Miyase (Kyushu Institute of Technology, Japan)
Efficient Built-In Self-Repair Techniques with Fine-Grained Redundancy Mechanisms for NAND Flash Memories
PRESENTER: Shyue-Kung Lu
Mahta Mayahinia (Karlsruhe institute of technology (KIT), Germany)
Mehdi Tahoori (Karlsruhe institute of technology (KIT), Germany)
Manu Perumkunnil (IMEC, Belgium)
Kristof Croes (IMEC, Belgium)
Francky Catthoor (IMEC, Belgium)
Analyzing the Electromigration Challenges of Computation in Resistive Memories
PRESENTER: Mehdi Tahoori
Ze-Wei Pan (National Central University, Taiwan)
Jin-Fu Li (National Central University, Taiwan)
DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs
14:30-16:00 Session D4: Automotive I
Peter Wohl (Synopsys, United States)
Paolo Bernardi (Politecnico di Torino, Italy)
Angione Francesco (Politecnico di Torino, Italy)
Stefano Quer (Politecnico di Torino, Italy)
Lorenzo Cardone (Politecnico di Torino, Italy)
Andrea Calabrese (Politecnico di Torino, Italy)
Davide Piumatti (Politecnico di Torino, Italy)
Alessandro Niccoletti (Politecnico di Torino, Italy)
Davide Appello (STMicroelectronics, Italy)
Vincenzo Tancorre (STMicroelectronics, Italy)
Roberto Ugioli (STMicroelectronics, Italy)
An innovative Strategy to Quickly Grade Functional Test Programs
PRESENTER: Paolo Bernardi
Kazuya Ioki (ROHM Co., Ltd., Japan)
Yasuyuki Kai (Kyushu Institute of Technology, Japan)
Kohei Miyase (Kyushu Institute of Technology, Japan)
Seiji Kajihara (Kyushu Institute of Technology, Japan)
A Practical Online Error Detection Method for Functional Safety Using Three-Site Implications
PRESENTER: Kazuya Ioki
Brian Foutz (Cadence Design Systems, United States)
Sarthak Singhal (Cadence Design Systems, India)
Prateek Kumar Rai (Cadence Design Systems, India)
Krishna Chakravadhanula (Cadence Design Systems, United States)
Vivek Chickermane (Cadence Design Systems, United States)
Bharath Nandakumar (Cadence Design Systems, India)
Sameer Chillarige (Cadence Design Systems, India)
Christos Papameletis (Cadence Design Systems, United States)
Satish Ravichandran (Cadence Design Systems, United States)
PPA Optimization of Testpoints in Automotive Designs
PRESENTER: Brian Foutz
14:30-16:00 Session E4: Industrial Practices II
Cheng-Wen Wu (NTHU, Taiwan)
Makoto Eiki (Sony Semiconductor Manufacturing, Japan)
Masuo Kajiyama (Sony Semiconductor Manufacturing, Japan)
Tomoki Nakamura (Sony Semiconductor Manufacturing, Japan)
Michihiro Shintani (Kyoto Institute of Technology, Japan)
Michiko Inoue (Nara Institute of Science and Technology, Japan)
Accurate Failure Rate Prediction Based on Gaussian Process Using WAT Data
PRESENTER: Makoto Eiki
Seongkwan Lee (Samsung Electronics, South Korea)
Cheolmin Park (Samsung Electronics, South Korea)
Minho Kang (Samsung Electronics, South Korea)
Jun Yeon Won (Samsung Electronics, South Korea)
HyungSun Ryu (Samsung Electronics, South Korea)
Jaemoo Choi (Samsung Electronics, South Korea)
Byunghyun Yim (Samsung Electronics, South Korea)
4.5Gsps MIPI D-PHY Receiver Circuit for Automatic Test Equipment
PRESENTER: Seongkwan Lee
David Lerner (Intel Corporation, United States)
Benson Inkley (Intel Corporation, United States)
Shubhada Sahasrabudhe (Intel Corporation, United States)
Ethan Hansen (Intel Corporation, United States)
Arjan Van De Ven (Intel Corporation, United States)
Optimization of Tests for Managing Silicon Defects in Data Centers
PRESENTER: David Lerner
Benjamin Niewenhuis (Texas Instruments, United States)
Devanathan Varadarajan (Texas Instruments, United States)
Improving structural coverage of functional tests with checkpoint signature computation
Brian Buras (Advantest, United States)
Constantinos Xanthopoulos (Advantest, United States)
Jason Kim (Advantest, United States)
Ken Butler (Advantest, United States)
Zero Trust Approach to IC Manufacturing and Testing
PRESENTER: Brian Buras
Thomas Nirmaier (Infineon Technologies, Germany)
Manuel Harrant (Infineon Technologies, Germany)
Marc Huppmann (Infineon Technologies, Germany)
Georg Pelz (Infineon Technologies, Germany)
Virtual Prototyping: Closing the digital gap between product requirements and post-Si verification & validation
PRESENTER: Thomas Nirmaier
16:30-18:00 Session A5: Special Session on HW Certification
Tung-Yi Chan (Winbond, Taiwan)
Rachel Menda-Shabat (Winbond, Israel)
Latest Cybersecurity regulations, certifications and labeling trends

ABSTRACT. The talk will present the latest trends in regulations and certifications related to Cyber security, including the EU Cybersecurity Act, US IoT Cybersecurity Improvement Act, and various industrial security requirements for IoT and Automotive.

Gil Bernabeu (GlobalPlatform, United States)
GlobalPlatform: 20 years of Security evaluation on secure components

ABSTRACT. This presentation will share the experience of GlobalPlatform in the last 20 years about the security evaluation of secure components and the effort to improve these evaluations, where a secure component is a combination of hardware and software to create an isolated environment to protect application and data.

Tung-Yi Chan (Winbond, Taiwan)
Hardware Security in Internet Connected Platforms and Certification

ABSTRACT. This speech demonstrates a framework to integrate secure MCU, secure memory and firmware to build secured IoT platforms with “Root of Trust”, “cyber resilience” and secure storage including external secure Flash memory. The security certification ecosystem and certification process flow are illustrated.

16:30-18:00 Session B5: Analog Testing
Hans Martin von Staudt (Renesas, Germany)
Jun-Yang Lei (Georgia Institute of Technology, United States)
Abhijit Chatterjee (Georgia Institute of Technology, United States)
ML-Assisted Bug Emulation Experiments for Post-Silicon Multi-Debug of AMS Circuits
Tobias Kilian (Infineon Technologies AG / Technical University of Munich, Germany)
Markus Hanel (Technical University of Munich, Germany)
Daniel Tille (Infineon Technologies AG, Germany)
Martin Huch (Infineon Technology AG, Germany)
Ulf Schlichtmann (Technical University of Munich, Germany)
A Path Selection Flow for Functional Path Ring Oscillators using Physical Design Data
PRESENTER: Tobias Kilian
Michael Laisne (Dialog Semiconductor - a Renesas Company, United States)
Alfred Crouch (Amida Technology Solutions, Inc., United States)
Michele Portolan (Univ Grenoble Alpes, CNRS, Grenoble INP, TIMA, France)
Martin Keim (Siemens Digital Industries Software, United States)
Bradford Van Treuren (VT Enterprises Consulting Services, United States)
Hans Martin von Staudt (Dialog Semiconductor - a Renesas Company, Germany)
Jeff Rearick (Advanced Micro Devices, United States)
Songlin Zuo (Tailored Management, United States)
IEEE P1687.1: Extending the Network Boundaries for Test
PRESENTER: Martin Keim
16:30-18:00 Session D5: Automotive: Special Session on High-Power Electronics
Shi-Yu Huang (National Tsing Hua University, Taiwan)
Wen-Chi Chang (ITRI, Taiwan, Taiwan)
The Importance and Demand Market of SiC Substrate Defect Testing

ABSTRACT. SiC is a potential material for high-power devices such as EVs and green energy applications. If it’s used as a substrate for GaN epitaxial layer, it’s also highly recommended to make a 5G or 6G communication device. The above application makes SiC device has more than a 20% CAGR growth rate before 2027. However, growing SiC substrate is more difficult than Si substrate. The main reason is that SiC has silicon and carbide two elements, during the high-temperature crystallization process, it might generate lots of defects. Some of the key defects might deliver to the epitaxial layer and device, and finally, make the device fail. In this talk, we will introduce the importance and market of SiC substrate defect testing.

Hung-Yi Teng (ITRI, Taiwan, Taiwan)
Validation of SPICE models for commercial SiC MOSFETs

ABSTRACT. Silicon carbide (SiC) MOSFETs are promising for electric vehicles because they show excellent performance in low on-resistance, high-frequency, and high-speed switching, as well as in operation at high temperatures. The accuracy of the SPICE model of SiC MOSFET is crucial when evaluating the performance of power devices. We validated the SPICE model of commercial 1.2kV SiC MOSFETs regarding its static characteristics, dynamic characteristics, and switching characteristics. In this paper, we will introduce our validation methodology and present major findings observed from the validation results. Furthermore, how to improve the accuracy of the SPICE model of SiC MOSFETs will also be discussed.

Chih-Chung Chiu (ITRI, Taiwan, Taiwan)
Practical Design Experiences on a Multi-Voltage-Level Motor Driver System using a Power Inverter

ABSTRACT. In this talk, we share our design experiences on a motor driver system incorporating power inverters. To support the switching among several different operating voltages, the controller of the power inverters based on pulse-width modulation have to be tailored in a way to mix the currents from different power conversion paths, so that the performance is optimized with robust operation at the same time. Simulation results and the measurement results of a prototype system are presented to demonstrate how the adopted pulse-modulation schemes for the power inverters, including CPS-SPWM and PD-SPWM schemes can improve the system’s stability.

16:30-18:00 Session E5: Analog Test, Diagnosis, Test Cost, All-In-One
Adit Singh (Auburn University, United States)
Kwondo Ma (Georgia Institute of Technology, United States)
Anurup Saha (Georgia Institute of Technology, United States)
Chandramouli Amarnath (Georgia Institute of Technology, United States)
Abhijit Chatterjee (Georgia Institute of Technology, United States)
Efficient Low Cost Alternative Testing of Analog Crossbar Arrays for Deep Neural Networks
Kushagra Bhatheja (Iowa State University, United States)
Shravan Chaganti (Iowa State University, United States)
Xiankun Robert Jin (NXP Semiconductors, United States)
Chris C Dao (NXP Semiconductors, United States)
Juxiang Ren (NXP Semiconductors, United States)
Abhishek Kumar (NXP Semiconductors, United States)
Daniel Correa (NXP Semiconductors, United States)
Mark Lehmann (NXP Semiconductors, United States)
Thomas Rodriguez (NXP Semiconductors, United States)
Eric Kingham (NXP Semiconductors, United States)
Joel R Knight (NXP Semiconductors, United States)
Allan Dobbin (NXP Semiconductors, United States)
Scott W Herrin (NXP Semiconductors, United States)
Doug Garrity (NXP Semiconductors, United States)
Degang Chen (Iowa State University, United States)
Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing
Praise Farayola (Iowa State University, United States)
Isaac Bruce (Iowa State University, United States)
Shravan Chaganti (Texas Instruments Inc, United States)
Abalhassan Sheikh (Texas Instruments Inc, United States)
Srivaths Ravi (Texas Instruments Inc, United States)
Degang Chen (Iowa State University, United States)
Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing
PRESENTER: Praise Farayola
Irith Pomeranz (Purdue University, United States)
Transforming an n-Detection Test Set into a Test Set for a Variety of Fault Models
Vijayakumar Thangamariappan (Advantest America Inc, United States)
Nidhi Agrawal (Advantest America Inc, United States)
Constantinos Xanthopoulos (Advantest America Inc, United States)
Jason Kim (Advantest America Inc, United States)
Ira Leventhal (Advantest America Inc, United States)
Joe Xiao (Essai Inc., (an Advantest Group), United States)
Ken Butler (Advantest America Inc, United States)
Improvements in the Automated IC Socket Pin Defect Detection
Mukta Debnath (Indian Statistical Institute, Kolkata, India)
Animesh Basak Chowdhury (New York University, New York, United States)
Debasri Saha (A.K. Chowdhury School of IT,University of Calcutta, Kolkata, India)
Susmita Sur-Kolay (Indian Statistical Institute, Kolkata, India)
GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs

ABSTRACT. Exhaustive testing of high-level designs pose an arduous challenge due to complex branching conditions, loop structures and inherent concurrency of hardware designs. Test engineers aim to generate quality test-cases satisfying various code coverage metrics to ensure minimal presence of bugs in a design. Prior works in testing SystemC designs are time inefficient which obstruct achieving the desired coverage in shorter time-span. We interleave greybox fuzzing and concolic execution in a systematic manner and generate quality test-cases accelerating test coverage metrics. Our results outperform state-of-the-art methods in terms of number of test cases and branch-coverage for some of the benchmarks, and runtime for most of them.