ABSTRACT. In-memory computing (IMC) has become an active area of research in the circuits community. IMC addresses the energy and latency costs of memory accesses that dominate when processing AI workloads. It does so by transforming the conventional memory read access into one that computes AI functions of data by employing analog computations. As a result, IMC chips have demonstrated > 100X reduction in the energy-delay product over equivalent von Neumann architectures at ISO-accuracy. However, today, bank-level IMC designs have matured and efficiency gains have stagnated. This talk will provide a historical overview of the technology, describe current trends, and identify future opportunities and challenges in deploying IMCs in emerging applications.

ABSTRACT. Testing of RRAM based CIM devices is fundamentally different from testing traditional memories. Non-volatile memories used to realize CIM concepts allows not only for data-storage (i.e., memory configuration), but also for the execution of logical and arithmetic operations (i.e., computing configuration). Therefore, not only significant design changes are needed in memory array and/or in the peripheral circuits, but also new fault models and test approaches are needed. Moreover, RRAM based CIM makes use of non-linear non-volatile devices making the defect modeling with traditional linear resistor inappropriate for such device defects. Hence, even the way of doing defect modeling has to change. This talk discusses testing for RRAM based CIM and highlights the test challenges and how testing CIM dies is different from the traditional way of testing logic and memory. Methods for defect modeling, fault modeling, and test development will be discussed. The talk demonstrates that unique faults can occur in the CIM die while in the computation configuration, and that these faults cannot be detected by just testing the CIM die in the memory configuration. Moreover, it shows that testing the CIM die in the computation configuration reduces the overall test time while improving the outgoing product quality.

ABSTRACT. Computing-in-memory (CIM) is being widely explored to minimize power consumption in data movement and multiply-and-accumulate (MAC) for edge-AI devices. Although most prior work focuses on analog-based CIM (ACIM) to leverage the BL charge/discharge operation, the lack of accuracy caused by transistor variation and the ADC is a concern. In contrast, a digital-based CIM (DCIM) approach realizes enough accuracy and flexibility for various input and weight bit widths while also benefiting from technology scaling. This presentation provides an overview of SRAM based DCIM macro using 1R1W bit-cell and cascaded adders. The DCIM macro can realize simultaneous MAC + write operations and wide range dynamic voltage-frequency. A programmable BIST based test solution is designed and implemented for the DCIM macro. Special features were designed in the BIST engine to enable DCIM macro performance and power characterization. Fault simulation shows the BIST achieved > 99% test coverage. The BIST test results were validate on a test chip.

ABSTRACT. The talk will present the latest trends in regulations and certifications related to Cyber security, including the EU Cybersecurity Act, US IoT Cybersecurity Improvement Act, and various industrial security requirements for IoT and Automotive.

ABSTRACT. This presentation will share the experience of GlobalPlatform in the last 20 years about the security evaluation of secure components and the effort to improve these evaluations, where a secure component is a combination of hardware and software to create an isolated environment to protect application and data.

ABSTRACT. This speech demonstrates a framework to integrate secure MCU, secure memory and firmware to build secured IoT platforms with “Root of Trust”, “cyber resilience” and secure storage including external secure Flash memory. The security certification ecosystem and certification process flow are illustrated.

ABSTRACT. SiC is a potential material for high-power devices such as EVs and green energy applications. If it’s used as a substrate for GaN epitaxial layer, it’s also highly recommended to make a 5G or 6G communication device. The above application makes SiC device has more than a 20% CAGR growth rate before 2027. However, growing SiC substrate is more difficult than Si substrate. The main reason is that SiC has silicon and carbide two elements, during the high-temperature crystallization process, it might generate lots of defects. Some of the key defects might deliver to the epitaxial layer and device, and finally, make the device fail. In this talk, we will introduce the importance and market of SiC substrate defect testing.

ABSTRACT. Silicon carbide (SiC) MOSFETs are promising for electric vehicles because they show excellent performance in low on-resistance, high-frequency, and high-speed switching, as well as in operation at high temperatures. The accuracy of the SPICE model of SiC MOSFET is crucial when evaluating the performance of power devices. We validated the SPICE model of commercial 1.2kV SiC MOSFETs regarding its static characteristics, dynamic characteristics, and switching characteristics. In this paper, we will introduce our validation methodology and present major findings observed from the validation results. Furthermore, how to improve the accuracy of the SPICE model of SiC MOSFETs will also be discussed.

ABSTRACT. In this talk, we share our design experiences on a motor driver system incorporating power inverters. To support the switching among several different operating voltages, the controller of the power inverters based on pulse-width modulation have to be tailored in a way to mix the currents from different power conversion paths, so that the performance is optimized with robust operation at the same time. Simulation results and the measurement results of a prototype system are presented to demonstrate how the adopted pulse-modulation schemes for the power inverters, including CPS-SPWM and PD-SPWM schemes can improve the system’s stability.

ABSTRACT. Exhaustive testing of high-level designs pose an arduous challenge due to complex branching conditions, loop structures and inherent concurrency of hardware designs. Test engineers aim to generate quality test-cases satisfying various code coverage metrics to ensure minimal presence of bugs in a design. Prior works in testing SystemC designs are time inefficient which obstruct achieving the desired coverage in shorter time-span. We interleave greybox fuzzing and concolic execution in a systematic manner and generate quality test-cases accelerating test coverage metrics. Our results outperform state-of-the-art methods in terms of number of test cases and branch-coverage for some of the benchmarks, and runtime for most of them.