previous day
next day
all days

View: session overviewtalk overview

11:00-12:00Diamond Supporter Presentation (Ball Room)
12:00-14:00Lunch Break (Corporate Forum) on Exhibit Floor
14:00-15:30 Session A1: New Frontiers in Fault Modeling
Saman Adham (TSMC, Canada)
Wei Li (Carnegie Mellon University, United States)
Danielle Duvalsaint (Carnegie Mellon University, United States)
Chris Nigh (Carnegie Mellon University, United States)
R. D. Blanton (Carnegie Mellon University, United States)
Subhasish Mitra (Stanford University, United States)
PEPR: Pseudo-Exhaustive Physical Region Testing
PRESENTER: R. D. Blanton
Nirmal Saxena (NVIDIA, United States)
Atieh Lotfi (NVIDIA, United States)
Error Model- A New Way of Doing Fault Simulation
PRESENTER: Nirmal Saxena
Subhadip Kundu (Qualcomm, India)
Gaurav Bhargava (Qualcomm Technologies Inc, United States)
Lesly Endrinal (Qualcomm Technologies Inc, United States)
Lavakumar Ranganathan (Qualcomm Technologies Inc, United States)
Using Custom Fault Modelling to Improve Understanding of Silicon Failures
PRESENTER: Subhadip Kundu
14:00-15:30 Session B1: Innovation with Machine Learning I
Kenneth Butler (Advantest, United States)
Zhengyuan Shi (The Chinese University of Hong Kong, Hong Kong)
Min Li (The Chinese University of Hong Kong, Hong Kong)
Sadaf Khan (The Chinese University of Hong Kong, Hong Kong)
Liuzheng Wang (Huawei Technologies Co., Ltd., China)
Naixing Wang (Huawei Technologies Co., Ltd., China)
Yu Huang (Huawei Technologies Co., Ltd., China)
Qiang Xu (The Chinese University of Hong Kong, Hong Kong)
DeepTPI: Test Point Insertion with Deep Reinforcement Learning
PRESENTER: Zhengyuan Shi
Yiwen Liao (University of Stuttgart, Germany)
Zahra Paria Najafi-Haghi (University of Stuttgart, Germany)
Hans-Joachim Wunderlich (University of Stuttgart, Germany)
Bin Yang (University of Stuttgart, Germany)
Efficient and Robust Resistive Open Defect Detection based on Unsupervised Deep Learning
Xiaopeng Zhang (The Chinese University of Hong Kong, Hong Kong)
Shoubo Hu (Huawei Noah’s Ark Lab, Hong Kong)
Zhitang Chen (Huawei Noah’s Ark Lab, Hong Kong)
Shengyu Zhu (Huawei Noah’s Ark Lab, China)
Evangeline F.Y. Young (The Chinese University of Hong Kong, Hong Kong)
Pengyun Li (HiSilicon, China)
Cheng Chen (HiSilicon, China)
Yu Huang (HiSilicon, China)
Jianye Hao (Huawei Noah’s Ark Lab, China)
RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement
PRESENTER: Xiaopeng Zhang
14:00-15:30 Session C1: Diagnosis and Debug
Shi-Yu Huang (National Tsing Hua University, Taiwan)
Bharath Nandakumar (Cadence Design Systems, India)
Sameer Chillarige (Cadence Design Systems, India)
Madhur Maheshwari (Cadence Design Systems, India)
Robert Redburn (IBM, United States)
Jeff Zimmerman (IBM, United States)
Nicholai L'Esperance (IBM, United States)
Edward Dziarcak (IBM, United States)
Scaling physically aware logic diagnosis to complex high volume 7nm server processors
Cheng-Sian Kuo (National Taiwan University, Taiwan)
James Chien-Mo Li (National Taiwan University, Taiwan)
Bing-Han Hsieh (National Taiwan University, Taiwan)
Chris Nigh (Qualcomm Technologies, Inc., United States)
Mason Chern (Qualcomm Semiconductor Corporation, Taiwan)
Gaurav Bhargava (Qualcomm Technologies, Inc., United States)
Diagnosing Double Faulty Chains through Failing Bit Separation
PRESENTER: Bing-Han Hsieh
Dun-An Yang (National Tsing Hua University, Department of Electrical Engineering, Hsinchu, Taiwan, Taiwan)
Jing-Jia Liou (National Tsing Hua University, Department of Electrical Engineering, Hsinchu, Taiwan, Taiwan)
Harry H. Chen (MediaTek Inc., Computing and AI Technology Group, Hsinchu, Taiwan, Taiwan)
Transient Fault Pruning for Effective Candidate Reduction in Functional Debugging
PRESENTER: Jing-Jia Liou
14:00-15:30 Session D1: TTTC PhD Thesis Competition - Final Round
Michele Portolan (Univ Grenoble Alpes, CNRS, Grenoble INP, TIMA, France)
Sebastian Huhn (University of Bremen, Germany)
Rolf Drechsler (University of Bremen, Germany, Germany)
Next Generation Design For Testability, Debug and Reliability Using Formal Techniques
PRESENTER: Sebastian Huhn
Supriyo Srimani (Indian Institute of Engineering Science and Technology (IIEST),Shibpur, India)
Hafizur Rahaman (Indian Institute of Engineering Science and Technology (IIEST),Shibpur, India)
Testing of Analog Circuits using Statistical and Machine Learning Techniques
PRESENTER: Supriyo Srimani
Prabuddha Chakraborty (University of Florida, United States)
Swarup Bhunia (University of Florida, United States)
AI-Driven Assurance of Hardware IP against Reverse Engineering Attacks
14:00-15:30 Session E1: Special Session Dedicated to the Memory of T.W. Williams, W. Maly and D. Pradhan

Title: Dedicated to Remembering Late Test Giants

Organizer/Moderator: Yervant Zorian, Synopsys

  • “Wojciech Maly Memorial”, Anne Meixner; Phil Nigh, Broadcoam
  • “Tom W Williams Memorial”, Ray Mercer; Subhasish Mitra, Stanford U
  • “Dhiraj K Pradhan Memorial”, Adit Sing, Auburn U; Sandeep Gupta, USC
Yervant Zorian (Synopsys, United States)
16:00-17:30 Session A2: Panel 2: Are last century’s test techniques suitable for 21st century Silent Errors?


Are last century’s test techniques suitable for 21st century Silent Errors?


  • Dr. Sreejit Chakravarty, Intel Corporation,
  • Prof. Subhasish Mitra, Stanford University, USA;


Undetected errors produced by computing systems, also called silent errors, have major consequences ranging from loss of data and services to financial and productivity losses, or even loss of human life. Silent errors produced by computing hardware have been recently identified as a highly critical challenge in several articles by Google, Meta, and New York Times.

The existing HVM test paradigm is falling short. And the test community is helping port the HVM test paradigm to InField Testing to cover for HVM escapes and aging related failures. In this panel, we discuss on whether this is the right approach or if there is a need for a paradigm shift for HVM and InField testing. Several unanswered questions will be touched upon by the panelist. Should we rely on structural, functional, or quasi functional tests? Are HVM fault models like stuck-at etc. the right fault models around which to develop and evaluate the test content to be used for infield testing? Is there a need to rethink how we develop and evaluate online protection schemes like array ECC etc.?  How can academia step in to help us select and develop the new paradigm? What kind of infrastructure support do we need from CAD vendors? We are also looking forward to the audience raising additional questions during this discussion.


  • Rama Govindaraju, Google, USA [10 Minutes]
  • Harish Dixit, Facebook, USA [10 Minutes]
  • Pradeep Bose, IBM, USA [10 Minutes]
  • Subhasish Mitra [5 minutes]
  • Sreejit Chakravarty [5 minutes]
  • One more TBD
Jeff Rearick (AMD, United States)
16:00-17:30 Session B2: Innovation with Machine Learning II
Charles H.-P. Wen (National Chiao Tung University, Taiwan)
Junhua Huang (Noah's Ark Lab, Huawei, China)
Hui-Ling Zhen (Noah's Ark Lab, Huawei, China)
Naixing Wang (Hisilicon, Huawei, China)
Hui Mao (Noah's Ark Lab, Huawei, China)
Mingxuan Yuan (Noah's Ark Lab, Huawei, China)
Yu Huang (Hisilicon, Huawei, China)
Neural Fault Analysis for SAT-based ATPG
PRESENTER: Hui-Ling Zhen
Ya-Chi Cheng (NCKU, Taiwan)
Pai-Yu Tan (NTHU, Taiwan)
Cheng-Wen Wu (NTHU, Taiwan)
Ming-Der Shieh (NCKU, Taiwan)
Chien-Hui Chuang Chien-Hui Chuang (TSMC, Taiwan)
Gordon Liao (TSMC, Taiwan)
Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method
Shyue-Kung Lu (National Taiwan University of Science and Technology, Taiwan)
Yu-Sheng Wu (National Taiwan University of Science and Technology, Taiwan)
Jin-Hua Hong (National University of Kaohsiung, Taiwan)
Kohei Miyase (Kyushu Institute of Technology, Japan)
Fault Resilience Techniques for Flash Memory of DNN Accelerators
PRESENTER: Shyue-Kung Lu
16:00-17:30 Session C2: New Frontiers in Test Content Optimization
Mehdi Tahoori (Karlsruhe Institute of Technology, Germany)
Jonti Talukdar (Duke University, United States)
Arjun Chaudhuri (Duke University, United States)
Mayukh Bhattacharya (Synopsys, United States)
Krishnendu Chakrabarty (Duke University, United States)
Automatic Structural Test Generation for Analog Circuits using Neural Twins
PRESENTER: Arjun Chaudhuri
Suriyaprakash Natarajan (Intel Corporation, United States)
Abhijit Sathaye (Intel Corporation, United States)
Chaitali Oak (Intel Corporation, United States)
Nipun Chaplot (Intel Corporation, United States)
Suvadeep Banerjee (Intel Corporation, United States)
DEFCON: Defect Acceleration through Content Optimization
Ankush Srivastava (Qualcomm Inc, India)
Jais Abraham (Qualcomm Inc, India)
Low Capture Power At-Speed Test with Local Hot Spot Analysis to Reduce Over-Test
16:00-17:30 Session D2: Test of HW Accelerators I
Krishna Chakravadhanula (Cadence Design Systems, United States)
Josie Esteban Rodriguez Condia (Politecnico di Torino, Italy)
Juan David Guerrero Balaguera (Politecnico di Torino, Italy)
Fernando Fernandes dos Santos (Institut National de Recherche en Sciences et Technologies du Numérique (INRIA), France)
Paolo Rech (University of Trento, Italy)
Matteo Sonza Reorda (Politecnico di Torino, Italy)
A Multi-level Approach to Evaluate the Impact of GPU Permanent Faults on CNN's Reliability
Abhairaj Singh (TU Delft, Netherlands)
Moritz Fieback (TU Delft, Netherlands)
Rajendra Bishnoi (TU Delft, Netherlands)
Filip Bradarić (TU Delft, Netherlands)
Anteneh Gebregiorgis (TU Delft, Netherlands)
Rajiv Joshi (IBM, United States)
Said Hamdioui (TU Delft, Netherlands)
Accelerating RRAM Testing with Low-cost Computation-in-Memory based DFT
PRESENTER: Abhairaj Singh
Soyed Tuhin Ahmed (Karlsruhe Institute Of Technology, Germany)
Mehdi B. Tahoori (Karlsruhe Institute of Technology (KIT), Faculty of Informatik, Karlsruhe, Germany, Germany)
Compact Functional Test Generation for Memristive Deep Learning Implementations Using Approximate Gradient Ranking
16:00-17:30 Session E2: Special Session on Silicon Life-Cycle Management

  Special Session on SLM

                Title: “Experiences in Silicon Lifecycle Management”

                Moderator: Mehdi

                Organizer: Yervant Zorian, Synopsys


  • "In-Field System Debug and Silicon Life Cycle Management of Compute Systems”, Sankarn Menon, Rolf Kuehnis and Rakesh Kandula, Intel
  • “Sensor Aware Production Testing”, Firooz Massoudi, Ash Patel, Karen Darbinian, Yervant Zorian, Synopsys
  • “Empowering Secure and Reliable BIST Solution for Automotive SOCs”, Madhu Sudhana Julapati, Qualcomm
Yervant Zorian (Synopsys, United States)