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| 14:00 | PEPR: Pseudo-Exhaustive Physical Region Testing PRESENTER: R. D. Blanton |
| 14:30 | Error Model- A New Way of Doing Fault Simulation PRESENTER: Nirmal Saxena |
| 15:00 | Using Custom Fault Modelling to Improve Understanding of Silicon Failures PRESENTER: Subhadip Kundu |
| 14:00 | DeepTPI: Test Point Insertion with Deep Reinforcement Learning PRESENTER: Zhengyuan Shi |
| 14:30 | Efficient and Robust Resistive Open Defect Detection based on Unsupervised Deep Learning PRESENTER: Yiwen Liao |
| 15:00 | RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement PRESENTER: Xiaopeng Zhang |
| 14:00 | Scaling physically aware logic diagnosis to complex high volume 7nm server processors PRESENTER: Bharath Nandakumar |
| 14:30 | Diagnosing Double Faulty Chains through Failing Bit Separation PRESENTER: Bing-Han Hsieh |
| 15:00 | Transient Fault Pruning for Effective Candidate Reduction in Functional Debugging PRESENTER: Jing-Jia Liou |
| 14:00 | Next Generation Design For Testability, Debug and Reliability Using Formal Techniques PRESENTER: Sebastian Huhn |
| 14:30 | Testing of Analog Circuits using Statistical and Machine Learning Techniques PRESENTER: Supriyo Srimani |
| 15:00 | AI-Driven Assurance of Hardware IP against Reverse Engineering Attacks PRESENTER: Prabuddha Chakraborty |
Title: Dedicated to Remembering Late Test Giants
Organizer/Moderator: Yervant Zorian, Synopsys
- “Wojciech Maly Memorial”, Anne Meixner; Phil Nigh, Broadcoam
- “Tom W Williams Memorial”, Ray Mercer; Subhasish Mitra, Stanford U
- “Dhiraj K Pradhan Memorial”, Adit Sing, Auburn U; Sandeep Gupta, USC
Title:
Are last century’s test techniques suitable for 21st century Silent Errors?
Organizer(s):
- Dr. Sreejit Chakravarty, Intel Corporation, sreejit.chakravarty@intel.com
- Prof. Subhasish Mitra, Stanford University, USA; subh@stanford.edu
Abstract:
Undetected errors produced by computing systems, also called silent errors, have major consequences ranging from loss of data and services to financial and productivity losses, or even loss of human life. Silent errors produced by computing hardware have been recently identified as a highly critical challenge in several articles by Google, Meta, and New York Times.
The existing HVM test paradigm is falling short. And the test community is helping port the HVM test paradigm to InField Testing to cover for HVM escapes and aging related failures. In this panel, we discuss on whether this is the right approach or if there is a need for a paradigm shift for HVM and InField testing. Several unanswered questions will be touched upon by the panelist. Should we rely on structural, functional, or quasi functional tests? Are HVM fault models like stuck-at etc. the right fault models around which to develop and evaluate the test content to be used for infield testing? Is there a need to rethink how we develop and evaluate online protection schemes like array ECC etc.? How can academia step in to help us select and develop the new paradigm? What kind of infrastructure support do we need from CAD vendors? We are also looking forward to the audience raising additional questions during this discussion.
Panelists
- Rama Govindaraju, Google, USA [10 Minutes]
- Harish Dixit, Facebook, USA [10 Minutes]
- Pradeep Bose, IBM, USA [10 Minutes]
- Subhasish Mitra [5 minutes]
- Sreejit Chakravarty [5 minutes]
- One more TBD
| 16:00 | Neural Fault Analysis for SAT-based ATPG PRESENTER: Hui-Ling Zhen |
| 16:30 | Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method PRESENTER: Ya-Chi Cheng |
| 17:00 | Fault Resilience Techniques for Flash Memory of DNN Accelerators PRESENTER: Shyue-Kung Lu |
| 16:00 | Automatic Structural Test Generation for Analog Circuits using Neural Twins PRESENTER: Arjun Chaudhuri |
| 16:30 | DEFCON: Defect Acceleration through Content Optimization PRESENTER: Suriyaprakash Natarajan |
| 17:00 | Low Capture Power At-Speed Test with Local Hot Spot Analysis to Reduce Over-Test PRESENTER: Ankush Srivastava |
| 16:00 | A Multi-level Approach to Evaluate the Impact of GPU Permanent Faults on CNN's Reliability PRESENTER: Josie Esteban Rodriguez Condia |
| 16:30 | Accelerating RRAM Testing with Low-cost Computation-in-Memory based DFT PRESENTER: Abhairaj Singh |
| 17:00 | Compact Functional Test Generation for Memristive Deep Learning Implementations Using Approximate Gradient Ranking PRESENTER: Soyed Tuhin Ahmed |
Special Session on SLM
Title: “Experiences in Silicon Lifecycle Management”
Moderator: Mehdi
Organizer: Yervant Zorian, Synopsys
Presenters:
- "In-Field System Debug and Silicon Life Cycle Management of Compute Systems”, Sankarn Menon, Rolf Kuehnis and Rakesh Kandula, Intel
- “Sensor Aware Production Testing”, Firooz Massoudi, Ash Patel, Karen Darbinian, Yervant Zorian, Synopsys
- “Empowering Secure and Reliable BIST Solution for Automotive SOCs”, Madhu Sudhana Julapati, Qualcomm