PROGRAM FOR MONDAY, SEPTEMBER 26TH
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16:30-18:00 Session P1: Panel 1 (Monday): “An Industry-wide Dialog on Chiplets and Heterogeneous Integration”
- Panel 1 (Monday): “An Industry-wide Dialog on Chiplets and Heterogeneous Integration”
- Format: three short presentations then an interactive dialog with the audience
- Goal: gather feedback on the HIR roadmap projections and about current and future test standards
- Presentation topics:
- Chiplet trends and drivers (Jeff)
- UCIe (Yervant)
- HIR (Dave Armstrong or Marc Hutner)
- Dialog (guided by Phil Nigh)
- Dialog with the audience topics:
- Are the HIR projections sensible? [e.g. compression ratios]
- What should the test community contribute to UCIe?
- Are the existing HIR-related standards (1838, 1149.10, etc.) sufficient? If not, what infrastructure needs more work (e.g. the details of the FPP in 1838)?
- Does there need to be a new scan test standard for chiplets which otherwise only have short-reach I/Os that can’t drive a tester channel?
- Will hybrid-bonding and other fine-pitch 3D integration techniques be forever beyond the reach of probe access at wafer sort? If so, what will we do instead?
- If self-test in the field becomes a universal part of chip lifecycle management, what does that mean for the ATE companies?
- What are the test roadblocks to the vision of Lego-like integration of chiplets from a wide variety of silicon providers?
Chair:
Jeff Rearick (AMD, United States)