TALK KEYWORD INDEX
This page contains an index consisting of author-provided keywords.
3 | |
3D ICs | |
A | |
Adaptive Algorithm Selection | |
Adaptive Test in Practice | |
Adversarial Attacks | |
aging | |
AI Accelerator | |
AI/Machine Learning in Test | |
Alternative testing | |
AMS Circuits | |
Analog and Mixed Signal Circuits | |
Analog and mixed-signal BIST | |
analog bug diagnosis | |
analog defect simulation | |
analog fault simulation | |
Analog Site-to-Site Variations | |
analog test | |
analog test generation | |
analog/RF design validation | |
Analysis of Variance (ANOVA) | |
application resiliency | |
At-speed Test | |
ATE | |
ATPG | |
Authentication | |
Automated Optical Inspection | |
Automated Test Environments | |
Automated Test Equipment (ATE) | |
Automated Test Pattern Generation | |
Automotive | |
automotive safety | |
Automotive Test | |
B | |
Binary Neural Network | |
BIRA | |
BISR | |
BIST | |
bounded model checking | |
BR-PUF | |
Built-In self-Repair | |
Burn-In Stress | |
C | |
C-testable | |
Calibration | |
callback | |
Capture clocks | |
Capture Power | |
Cell aware models | |
Cell Internal Defects | |
Centroid Selection Algorithm | |
Challenge covariance analysis | |
chip disaggregation | |
Chip performance prediction | |
chiplet | |
Chips and SOC designs | |
CIS Tester | |
Classification | |
Cleaning | |
CMOS backplane | |
Code Coverage | |
compression aborts | |
Computation in memory | |
computation-in-memory | |
Compute In Memory | |
Compute-in-Memory | |
Concolic Execution | |
concurrent error detection | |
Convolutional Neural Networks (CNNs) | |
Correlation | |
CTLE | |
Cybersecurity Act | |
Cybersecurity regulations | |
Cybersecutity certifications | |
D | |
D-PHY Receiver | |
Data Augmentation | |
data flow analysis | |
Data Transformations | |
DCDIAG | |
Debugging | |
decision tree | |
Decoder | |
deep learning | |
deep learning accelerator | |
Deep Neural Network | |
Deep neural network (DNN) testing | |
Deep Neural Networks | |
defect | |
defect acceleration | |
Defects | |
Design | |
Design for security | |
design for test | |
Design for testability | |
design-for-testability | |
design-for-testability (DFT) | |
detectability | |
Device Under Test (DUT) | |
Device Validation | |
DFT | |
diagnosis | |
display driver | |
E | |
early life failure | |
edge | |
Electric Vehicle | |
Electromigration | |
Embedded | |
embedded compression | |
embedded instruments | |
embedded IO | |
embedded-test | |
encryption | |
ENGINEERING CHANGE ORDER | |
Equalizer | |
error detection coverage | |
error estimation | |
Explainable AI | |
F | |
Failure Analysis | |
Fault Classification Prediction | |
fault coverage | |
Fault Detection | |
Fault Diagnosis | |
Fault Injection | |
Fault Model | |
fault modeling | |
fault models | |
Fault Resilience | |
fault simulation | |
Fault Simulator | |
Fault Tolerance | |
final package test | |
Flash | |
Flash Memory | |
FSM Automata Theory | |
FSM Extraction | |
functional path ring oscillator | |
functional safety | |
functional test | |
Functional Test Generation | |
Functional Test Programs | |
G | |
GaN | |
GlobalPlatform | |
gpu | |
Graph Neural Network | |
Graphics Processing Units (GPUs) | |
Greybox Fuzzing | |
H | |
hardware root of trust | |
hardware security | |
Hardware security and trust | |
Hardware Systematic Errors | |
Hardware Trojans | |
hash functions | |
HDL Code Analysis | |
headlight | |
heterogeneous integration | |
High accuracy | |
High resolution | |
High-level Synthesis | |
high-volume manufacture | |
HTOL test | |
HW Acceleration | |
hybrid cloud | |
I | |
IC Socket PINs defect detection | |
IC Sockets | |
IC testing | |
IEEE 1687 | |
IEEE 1687 standard | |
IEEE 1687.1 | |
IJTAG | |
Image Processing | |
implication | |
implication extraction | |
implied values | |
in-field self-test | |
In-Memory Computing | |
in-system test | |
Infant Mortality | |
INL estimation | |
Inline Inspection | |
integrated circuit | |
Intra-cell defects | |
IOT | |
IP Features | |
IR drop | |
L | |
Laser Fault Injection | |
latent defect | |
latent variable learning | |
launch-on-shift tests | |
LBIST | |
Lifetime | |
Linear Programming | |
Local Hot-Spot | |
Logic Locking | |
Logic minimization | |
Low power test | |
Low voltage | |
M | |
machine learning | |
manufacturing test | |
manufacturing variations | |
March tests | |
Measurement | |
Measurement System Analysis (MSA) | |
memory | |
Memory tests | |
Memory Yield | |
Memristive | |
Memristive Crossbar Array | |
Memristor | |
Method of Least Squares | |
micro-LED | |
MIPI | |
Mixed-signal | |
ML | |
Modeling attack | |
Monolithic 3D Integration | |
Monolithic Inter-tier Via | |
MOSFET | |
Motor Driver | |
multi die test | |
Multiple binning | |
multitask learning | |
N | |
n-detection test set | |
Natural Language Processing | |
neural networks | |
neural twins | |
non-volatile resistive memory | |
O | |
On-chip spectral testing | |
On-Chip Training | |
online diagnostic tests | |
Optimization | |
P | |
Parallel (Multisite) Testing | |
path selection | |
Pattern Recognition | |
pattern retargeting | |
performance screening | |
permanent faults | |
Physical diagnostics | |
Physical Optimization | |
Physical unclonable function | |
Power Device | |
Power Inverter | |
Power-Aware pattern generation | |
Pre-distortion | |
Probing | |
Process variation | |
Process Variations | |
pseudo-Boolean Optimization | |
Pulse-Width Modulation | |
Q | |
Q-bit fluctuations | |
quality | |
Quantum circuits | |
Quantum computing | |
Quantum electronics | |
Qubit | |
R | |
radiation-hardened technique | |
re-usability | |
reconfigurable binary logic | |
Reconfigurable Scan Networks | |
Redundancy | |
Redundancy Analysis | |
Register Transfer Level | |
Reinforcement Learning | |
Reliability | |
reliability analysis | |
Repeatability and Reproducibility (R&R) | |
resistive open detection | |
Resistive Random-Access Memory | |
Resistive Random-Access Memory (RRAM) | |
retargeting | |
reuse | |
Reversible scan chain | |
ring oscillator | |
Robust Operation | |
root cause analysis | |
RTL CHANGES | |
Rule-Based | |
S | |
sampling | |
SAT-based ATPG | |
SAT-Solver | |
Scalability | |
scan chain | |
Scan chain diagnosis | |
scan compression | |
scan test | |
scan-based designs | |
scan-based testing | |
Secure Access | |
Secure components | |
Secure flash memory | |
Secure IoT platforms | |
security | |
Security Assessment | |
Security certification ecosystem | |
Security certification process flow | |
self-monitoring | |
self-test | |
Semiconductor testing | |
SiC | |
Signal Integrity | |
Silent Data Errors | |
silicon execution trace | |
silicon photonics | |
Silicon test | |
single-event double-node transient | |
single-event double-node upset | |
Smart Power | |
soft error | |
Soft Errors | |
Software Tests | |
Software-Based Self-Test | |
Speed Grading | |
SPICE Model | |
Spiking Neural Network | |
Stacked ICs | |
Standard cell characterization | |
Statistical Testing | |
Stimulus Generator | |
Streaming Scan Network | |
Stress | |
Stress Test | |
STT-MRAM | |
stuck-at faults | |
Substrate Defect Testing | |
Symbolic Execution | |
System Level Test | |
System-Level Test | |
systematic defect | |
SystemC | |
T | |
TAP Controller | |
Techniques to achieve Zero Test Escapes | |
tensor cores | |
Test | |
Test Algorithm | |
Test and diagnosis | |
Test chip design | |
test compaction | |
test compression | |
test fabric | |
test generation | |
test metrics | |
test optimization | |
Test Point Insertion | |
TESTABILITY | |
Testability Prediction | |
Testing | |
Testing Crossbar Arrays | |
Testing Memristive Deep Learning Implementations Compact Test Generation | |
Testing Neural Networks | |
Testing of Quantum circuits | |
Testpoint Insertion | |
timing marginality | |
timing tests | |
transfer matrix | |
transient fault | |
Transient Faults | |
true random number generation | |
TSV | |
U | |
Unexpected Silicon Behavior | |
unknown states | |
unsupervised learning | |
Unsupervised Machine Learning | |
User Defined Fault Model (UDFM) | |
V | |
Validation | |
Verification | |
VH-bijection | |
Virtual Prototyping | |
Void | |
Volume diagnostics | |
W | |
wafer defect | |
Wafer defect map | |
Wafer Map | |
wafer sort test | |
Wafer Test | |
Watermarking | |
Wide-Bandgap | |
X | |
X-masking | |
X-tolerant | |
XOR APUF | |
XOR-gate | |
Y | |
Yield | |
Yield Analysis and Optimization | |
yield improvement | |
Yield Learning | |
Z | |
zero trust | |
Zero-Overhead |