ITC 2022: INTERNATIONAL TEST CONFERENCE 2022

This page contains an index consisting of author-provided keywords.

3
3D ICs	TSV BIST Repair: Design-For-Test Challenges and Emerging Solution for 3D Stacked IC’s
A
Adaptive Algorithm Selection	Neural Fault Analysis for SAT-based ATPG
Adaptive Test in Practice	Accurate Failure Rate Prediction Based on Gaussian Process Using WAT Data
Adversarial Attacks	The impact of on-chip training to adversarial attacks in Memristive Crossbar Arrays
aging	Reliability Study of 14 nm Scan Chains and Its Application to Hardware Security
AI Accelerator	RIBoNN: Designing Robust In-Memory Binary Neural Network Accelerators
AI/Machine Learning in Test	Accurate Failure Rate Prediction Based on Gaussian Process Using WAT Data
Alternative testing	Efficient Low Cost Alternative Testing of Analog Crossbar Arrays for Deep Neural Networks
AMS Circuits	Unsupervised Learning-based Early Anomaly Detection in AMS Circuits of Automotive SoCs
Analog and Mixed Signal Circuits	Testing of Analog Circuits using Statistical and Machine Learning Techniques
Analog and mixed-signal BIST	Circuit-to-Circuit Attacks in SoCs via Trojan-Infected IEEE 1687 Test Infrastructure
analog bug diagnosis	ML-Assisted Bug Emulation Experiments for Post-Silicon Multi-Debug of AMS Circuits
analog defect simulation	Application of Sampling in Industrial Analog Defect Simulation
analog fault simulation	Application of Sampling in Industrial Analog Defect Simulation
Analog Site-to-Site Variations	Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing
analog test	Application of Sampling in Industrial Analog Defect Simulation
analog test generation	Automatic Structural Test Generation for Analog Circuits using Neural Twins
analog/RF design validation	ML-Assisted Bug Emulation Experiments for Post-Silicon Multi-Debug of AMS Circuits
Analysis of Variance (ANOVA)	New R&R Methodology in Semiconductor Manufacturing Electrical Testing
application resiliency	Error Model- A New Way of Doing Fault Simulation
At-speed Test	Low Capture Power At-Speed Test with Local Hot Spot Analysis to Reduce Over-Test
ATE	IEEE P1687.1: Extending the Network Boundaries for Test 4.5Gsps MIPI D-PHY Receiver Circuit for Automatic Test Equipment
ATPG	PEPR: Pseudo-Exhaustive Physical Region Testing Test Generation for an Iterative Design Flow with RTL Changes DEFCON: Defect Acceleration through Content Optimization Compression-Aware ATPG Selective Multiple Capture Test (SMART) XLBIST
Authentication	IEEE P1687.1: Extending the Network Boundaries for Test
Automated Optical Inspection	Improvements in the Automated IC Socket Pin Defect Detection
Automated Test Environments	IEEE P1687.1: Extending the Network Boundaries for Test
Automated Test Equipment (ATE)	New R&R Methodology in Semiconductor Manufacturing Electrical Testing
Automated Test Pattern Generation	Low Capture Power At-Speed Test with Local Hot Spot Analysis to Reduce Over-Test
Automotive	Probeless DfT Scheme for Testing 20k I/Os of an Automotive Micro-LED Headlamp Driver IC A Path Selection Flow for Functional Path Ring Oscillators using Physical Design Data Functional In-Field Self-Test for Deep Learning Accelerators in Automotive Applications New R&R Methodology in Semiconductor Manufacturing Electrical Testing Virtual Prototyping: Closing the digital gap between product requirements and post-Si verification & validation
automotive safety	Error Model- A New Way of Doing Fault Simulation
Automotive Test	PPA Optimization of Testpoints in Automotive Designs
B
Binary Neural Network	RIBoNN: Designing Robust In-Memory Binary Neural Network Accelerators
BIRA	Configurable BISR Chain For Fast Repair Data Loading
BISR	Configurable BISR Chain For Fast Repair Data Loading
BIST	Probeless DfT Scheme for Testing 20k I/Os of an Automotive Micro-LED Headlamp Driver IC Configurable BISR Chain For Fast Repair Data Loading TSV BIST Repair: Design-For-Test Challenges and Emerging Solution for 3D Stacked IC’s
bounded model checking	Next Generation Design For Testability, Debug and Reliability Using Formal Techniques
BR-PUF	Modeling Challenge Covariances and Design Dependency for Efficient Attacks on Strong PUFs
Built-In self-Repair	Efficient Built-In Self-Repair Techniques with Fine-Grained Redundancy Mechanisms for NAND Flash Memories
Burn-In Stress	An innovative Strategy to Quickly Grade Functional Test Programs
C
C-testable	Scan-Based Test Chip Design with XOR-based C-testable Functional Blocks
Calibration	Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing
callback	IEEE P1687.1: Extending the Network Boundaries for Test
Capture clocks	Selective Multiple Capture Test (SMART) XLBIST
Capture Power	Low Capture Power At-Speed Test with Local Hot Spot Analysis to Reduce Over-Test
Cell aware models	A Comprehensive Learning-Based Flow for Cell-Aware Model Generation
Cell Internal Defects	Using Custom Fault Modelling to Improve Understanding of Silicon Failures
Centroid Selection Algorithm	Unsupervised Learning-based Early Anomaly Detection in AMS Circuits of Automotive SoCs
Challenge covariance analysis	Modeling Challenge Covariances and Design Dependency for Efficient Attacks on Strong PUFs
chip disaggregation	Challenges for High Volume Testing of Embedded IO Interfaces in Disaggregated Microprocessor Products
Chip performance prediction	ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
chiplet	Multi-die Parallel Test Fabric for Scalability and Pattern Reusability
Chips and SOC designs	GlobalPlatform: 20 years of Security evaluation on secure components
CIS Tester	4.5Gsps MIPI D-PHY Receiver Circuit for Automatic Test Equipment
Classification	WXAI: Wafer Defect Pattern Classification with Explainable Rule Based Decision Tree Methodology
Cleaning	Yield-Enhanced Probing Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test
CMOS backplane	Probeless DfT Scheme for Testing 20k I/Os of an Automotive Micro-LED Headlamp Driver IC
Code Coverage	GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs
compression aborts	Next Generation Design For Testability, Debug and Reliability Using Formal Techniques
Computation in memory	Analyzing the Electromigration Challenges of Computation in Resistive Memories
computation-in-memory	Accelerating RRAM Testing with Low-cost Computation-in-Memory based DFT Testing Computation-in-Memory Architectures Based on Memristive Devices
Compute In Memory	Fully Digital Compute In Memory Design and Test challenges
Compute-in-Memory	RIBoNN: Designing Robust In-Memory Binary Neural Network Accelerators
Concolic Execution	GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs
concurrent error detection	A Practical Online Error Detection Method for Functional Safety Using Three-Site Implications
Convolutional Neural Networks (CNNs)	A Multi-level Approach to Evaluate the Impact of GPU Permanent Faults on CNN's Reliability
Correlation	Language Driven Analytics for Failure Pattern Feedforward and Feedback New R&R Methodology in Semiconductor Manufacturing Electrical Testing
CTLE	4.5Gsps MIPI D-PHY Receiver Circuit for Automatic Test Equipment
Cybersecurity Act	Latest Cybersecurity regulations, certifications and labeling trends
Cybersecurity regulations	Latest Cybersecurity regulations, certifications and labeling trends
Cybersecutity certifications	Latest Cybersecurity regulations, certifications and labeling trends
D
D-PHY Receiver	4.5Gsps MIPI D-PHY Receiver Circuit for Automatic Test Equipment
Data Augmentation	Neural Fault Analysis for SAT-based ATPG
data flow analysis	An innovative Strategy to Quickly Grade Functional Test Programs
Data Transformations	IEEE P1687.1: Extending the Network Boundaries for Test
DCDIAG	Optimization of Tests for Managing Silicon Defects in Data Centers
Debugging	Transient Fault Pruning for Effective Candidate Reduction in Functional Debugging
decision tree	Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method
Decoder	Enhanced Data Pattern to Detect Defects in Flash Memory Address Decoder
deep learning	Efficient and Robust Resistive Open Defect Detection based on Unsupervised Deep Learning Wafer Map Defect Classification Based on the Fusion of Pattern and Pixel Information Improvements in the Automated IC Socket Pin Defect Detection
deep learning accelerator	Functional In-Field Self-Test for Deep Learning Accelerators in Automotive Applications
Deep Neural Network	Fault Resilience Techniques for Flash Memory of DNN Accelerators
Deep neural network (DNN) testing	Efficient Low Cost Alternative Testing of Analog Crossbar Arrays for Deep Neural Networks
Deep Neural Networks	The impact of on-chip training to adversarial attacks in Memristive Crossbar Arrays
defect	Defect-Directed Stress Testing Based on Inline Inspection Results DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs
defect acceleration	DEFCON: Defect Acceleration through Content Optimization
Defects	DEFCON: Defect Acceleration through Content Optimization Enhanced Data Pattern to Detect Defects in Flash Memory Address Decoder Optimization of Tests for Managing Silicon Defects in Data Centers
Design	Fully Digital Compute In Memory Design and Test challenges
Design for security	Hardware Root of Trust for SSN-based DFT Ecosystems
design for test	Challenges for High Volume Testing of Embedded IO Interfaces in Disaggregated Microprocessor Products Hardware Root of Trust for SSN-based DFT Ecosystems Improving structural coverage of functional tests with checkpoint signature computation
Design for testability	Scan-Based Test Chip Design with XOR-based C-testable Functional Blocks
design-for-testability	DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs
design-for-testability (DFT)	Accelerating RRAM Testing with Low-cost Computation-in-Memory based DFT
detectability	Error Model- A New Way of Doing Fault Simulation
Device Under Test (DUT)	New R&R Methodology in Semiconductor Manufacturing Electrical Testing
Device Validation	Validation of SPICE models for commercial SiC MOSFETs
DFT	Compression-Aware ATPG
diagnosis	PEPR: Pseudo-Exhaustive Physical Region Testing
display driver	Probeless DfT Scheme for Testing 20k I/Os of an Automotive Micro-LED Headlamp Driver IC
E
early life failure	DEFCON: Defect Acceleration through Content Optimization
edge	Zero Trust Approach to IC Manufacturing and Testing
Electric Vehicle	Validation of SPICE models for commercial SiC MOSFETs
Electromigration	Analyzing the Electromigration Challenges of Computation in Resistive Memories
Embedded	Configurable BISR Chain For Fast Repair Data Loading
embedded compression	Next Generation Design For Testability, Debug and Reliability Using Formal Techniques
embedded instruments	Reusing IEEE 1687-Compatible Instruments and Sub-Networks over a System Bus
embedded IO	Challenges for High Volume Testing of Embedded IO Interfaces in Disaggregated Microprocessor Products
embedded-test	DIST: Deterministic In-System Test with X-masking
encryption	Zero Trust Approach to IC Manufacturing and Testing
ENGINEERING CHANGE ORDER	Test Generation for an Iterative Design Flow with RTL Changes
Equalizer	4.5Gsps MIPI D-PHY Receiver Circuit for Automatic Test Equipment
error detection coverage	A Practical Online Error Detection Method for Functional Safety Using Three-Site Implications
error estimation	Application of Sampling in Industrial Analog Defect Simulation
Explainable AI	WXAI: Wafer Defect Pattern Classification with Explainable Rule Based Decision Tree Methodology
F
Failure Analysis	Using Custom Fault Modelling to Improve Understanding of Silicon Failures
Fault Classification Prediction	Neural Fault Analysis for SAT-based ATPG
fault coverage	Accelerating RRAM Testing with Low-cost Computation-in-Memory based DFT Improving structural coverage of functional tests with checkpoint signature computation
Fault Detection	Testing of Analog Circuits using Statistical and Machine Learning Techniques
Fault Diagnosis	Fault Diagnosis for Resistive Random-Access Memory and Monolithic Inter-tier Vias in Monolithic 3D Integration Testing of Analog Circuits using Statistical and Machine Learning Techniques
Fault Injection	Transient Fault Pruning for Effective Candidate Reduction in Functional Debugging
Fault Model	Fault Modeling and Testing of Memristor-Based Spiking Neural Networks
fault modeling	DEFCON: Defect Acceleration through Content Optimization
fault models	PEPR: Pseudo-Exhaustive Physical Region Testing
Fault Resilience	Fault Resilience Techniques for Flash Memory of DNN Accelerators
fault simulation	Error Model- A New Way of Doing Fault Simulation
Fault Simulator	Fault Modeling and Testing of Memristor-Based Spiking Neural Networks
Fault Tolerance	TAMED: Transitional Approaches for LFI Resilient State Machine Encoding RIBoNN: Designing Robust In-Memory Binary Neural Network Accelerators
final package test	Challenges for High Volume Testing of Embedded IO Interfaces in Disaggregated Microprocessor Products
Flash	Enhanced Data Pattern to Detect Defects in Flash Memory Address Decoder
Flash Memory	Efficient Built-In Self-Repair Techniques with Fine-Grained Redundancy Mechanisms for NAND Flash Memories Fault Resilience Techniques for Flash Memory of DNN Accelerators
FSM Automata Theory	RTL-FSMx: Fast and Accurate Finite State Machine Extraction at the RTL for Security Applications
FSM Extraction	RTL-FSMx: Fast and Accurate Finite State Machine Extraction at the RTL for Security Applications
functional path ring oscillator	A Path Selection Flow for Functional Path Ring Oscillators using Physical Design Data
functional safety	Probeless DfT Scheme for Testing 20k I/Os of an Automotive Micro-LED Headlamp Driver IC Unsupervised Learning-based Early Anomaly Detection in AMS Circuits of Automotive SoCs A Practical Online Error Detection Method for Functional Safety Using Three-Site Implications Runtime Fault Diagnostics for GPU Tensor Cores Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing
functional test	Functional In-Field Self-Test for Deep Learning Accelerators in Automotive Applications Improving structural coverage of functional tests with checkpoint signature computation
Functional Test Generation	Compact Functional Test Generation for Memristive Deep Learning Implementations Using Approximate Gradient Ranking
Functional Test Programs	An innovative Strategy to Quickly Grade Functional Test Programs
G
GaN	The Importance and Demand Market of SiC Substrate Defect Testing
GlobalPlatform	GlobalPlatform: 20 years of Security evaluation on secure components
gpu	Runtime Fault Diagnostics for GPU Tensor Cores
Graph Neural Network	DeepTPI: Test Point Insertion with Deep Reinforcement Learning
Graphics Processing Units (GPUs)	A Multi-level Approach to Evaluate the Impact of GPU Permanent Faults on CNN's Reliability
Greybox Fuzzing	GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs
H
hardware root of trust	Hardware Root of Trust for SSN-based DFT Ecosystems
hardware security	Reliability Study of 14 nm Scan Chains and Its Application to Hardware Security AI-Driven Assurance of Hardware IP against Reverse Engineering Attacks
Hardware security and trust	Circuit-to-Circuit Attacks in SoCs via Trojan-Infected IEEE 1687 Test Infrastructure
Hardware Systematic Errors	Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing
Hardware Trojans	Circuit-to-Circuit Attacks in SoCs via Trojan-Infected IEEE 1687 Test Infrastructure
hash functions	Hardware Root of Trust for SSN-based DFT Ecosystems
HDL Code Analysis	RTL-FSMx: Fast and Accurate Finite State Machine Extraction at the RTL for Security Applications
headlight	Probeless DfT Scheme for Testing 20k I/Os of an Automotive Micro-LED Headlamp Driver IC
heterogeneous integration	Challenges for High Volume Testing of Embedded IO Interfaces in Disaggregated Microprocessor Products
High accuracy	Scaling physically aware logic diagnosis to complex high volume 7nm server processors
High resolution	Scaling physically aware logic diagnosis to complex high volume 7nm server processors
High-level Synthesis	GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs
high-volume manufacture	Challenges for High Volume Testing of Embedded IO Interfaces in Disaggregated Microprocessor Products
HTOL test	Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method
HW Acceleration	In-Memory Computing: History, Overview, Current and Future Directions
hybrid cloud	Zero Trust Approach to IC Manufacturing and Testing
I
IC Socket PINs defect detection	Improvements in the Automated IC Socket Pin Defect Detection
IC Sockets	Improvements in the Automated IC Socket Pin Defect Detection
IC testing	Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method
IEEE 1687	Reusing IEEE 1687-Compatible Instruments and Sub-Networks over a System Bus
IEEE 1687 standard	Circuit-to-Circuit Attacks in SoCs via Trojan-Infected IEEE 1687 Test Infrastructure
IEEE 1687.1	IEEE P1687.1: Extending the Network Boundaries for Test
IJTAG	IEEE P1687.1: Extending the Network Boundaries for Test
Image Processing	Yield-Enhanced Probing Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test
implication	A Practical Online Error Detection Method for Functional Safety Using Three-Site Implications
implication extraction	A Practical Online Error Detection Method for Functional Safety Using Three-Site Implications
implied values	Compression-Aware ATPG
in-field self-test	Functional In-Field Self-Test for Deep Learning Accelerators in Automotive Applications
In-Memory Computing	Fault Modeling and Testing of Memristor-Based Spiking Neural Networks In-Memory Computing: History, Overview, Current and Future Directions
in-system test	DIST: Deterministic In-System Test with X-masking
Infant Mortality	DEFCON: Defect Acceleration through Content Optimization Just-Enough Stress Test for Infant-Mortality Screening Using Speed Binning
INL estimation	Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing
Inline Inspection	Defect-Directed Stress Testing Based on Inline Inspection Results
integrated circuit	RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement
Intra-cell defects	A Comprehensive Learning-Based Flow for Cell-Aware Model Generation
IOT	IEEE P1687.1: Extending the Network Boundaries for Test
IP Features	ADWIL: A Zero-Overhead Analog Device Watermarking Using Inherent IP Features
IR drop	Comprehensive Power-Aware ATPG methodology for complex low-power Designs
L
Laser Fault Injection	TAMED: Transitional Approaches for LFI Resilient State Machine Encoding
latent defect	DEFCON: Defect Acceleration through Content Optimization
latent variable learning	RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement
launch-on-shift tests	Transforming an n-Detection Test Set into a Test Set for a Variety of Fault Models
LBIST	Selective Multiple Capture Test (SMART) XLBIST
Lifetime	Just-Enough Stress Test for Infant-Mortality Screening Using Speed Binning
Linear Programming	TAMED: Transitional Approaches for LFI Resilient State Machine Encoding
Local Hot-Spot	Low Capture Power At-Speed Test with Local Hot Spot Analysis to Reduce Over-Test
Logic Locking	AI-Driven Assurance of Hardware IP against Reverse Engineering Attacks
Logic minimization	Modeling Challenge Covariances and Design Dependency for Efficient Attacks on Strong PUFs
Low power test	Comprehensive Power-Aware ATPG methodology for complex low-power Designs Low Capture Power At-Speed Test with Local Hot Spot Analysis to Reduce Over-Test
Low voltage	Understand VDDmin Failures for Improved Testing of Timing Marginalities
M
machine learning	ML-Assisted Bug Emulation Experiments for Post-Silicon Multi-Debug of AMS Circuits Automatic Structural Test Generation for Analog Circuits using Neural Twins Modeling Challenge Covariances and Design Dependency for Efficient Attacks on Strong PUFs WXAI: Wafer Defect Pattern Classification with Explainable Rule Based Decision Tree Methodology A Comprehensive Learning-Based Flow for Cell-Aware Model Generation Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method AI-Driven Assurance of Hardware IP against Reverse Engineering Attacks
manufacturing test	Comprehensive Power-Aware ATPG methodology for complex low-power Designs
manufacturing variations	Transfer-Matrix Abstractions to Analyze the Effect of Manufacturing Variations in Silicon Photonic Circuits
March tests	Fault-coverage Maximizing March Tests for Memory Testing
Measurement	Practical Design Experiences on a Multi-Voltage-Level Motor Driver System using a Power Inverter
Measurement System Analysis (MSA)	New R&R Methodology in Semiconductor Manufacturing Electrical Testing
memory	Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method
Memory tests	Fault-coverage Maximizing March Tests for Memory Testing
Memory Yield	Configurable BISR Chain For Fast Repair Data Loading
Memristive	Testing Computation-in-Memory Architectures Based on Memristive Devices
Memristive Crossbar Array	The impact of on-chip training to adversarial attacks in Memristive Crossbar Arrays
Memristor	Fault Modeling and Testing of Memristor-Based Spiking Neural Networks
Method of Least Squares	Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing
micro-LED	Probeless DfT Scheme for Testing 20k I/Os of an Automotive Micro-LED Headlamp Driver IC
MIPI	4.5Gsps MIPI D-PHY Receiver Circuit for Automatic Test Equipment
Mixed-signal	Virtual Prototyping: Closing the digital gap between product requirements and post-Si verification & validation
ML	In-Memory Computing: History, Overview, Current and Future Directions
Modeling attack	Modeling Challenge Covariances and Design Dependency for Efficient Attacks on Strong PUFs
Monolithic 3D Integration	Fault Diagnosis for Resistive Random-Access Memory and Monolithic Inter-tier Vias in Monolithic 3D Integration
Monolithic Inter-tier Via	Fault Diagnosis for Resistive Random-Access Memory and Monolithic Inter-tier Vias in Monolithic 3D Integration
MOSFET	Validation of SPICE models for commercial SiC MOSFETs
Motor Driver	Practical Design Experiences on a Multi-Voltage-Level Motor Driver System using a Power Inverter
multi die test	Multi-die Parallel Test Fabric for Scalability and Pattern Reusability
Multiple binning	ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
multitask learning	Wafer Map Defect Classification Based on the Fusion of Pattern and Pixel Information
N
n-detection test set	Transforming an n-Detection Test Set into a Test Set for a Variety of Fault Models
Natural Language Processing	Language Driven Analytics for Failure Pattern Feedforward and Feedback
neural networks	Wafer Map Defect Classification Based on the Fusion of Pattern and Pixel Information
neural twins	Automatic Structural Test Generation for Analog Circuits using Neural Twins
non-volatile resistive memory	Analyzing the Electromigration Challenges of Computation in Resistive Memories
O
On-chip spectral testing	Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing
On-Chip Training	The impact of on-chip training to adversarial attacks in Memristive Crossbar Arrays
online diagnostic tests	Runtime Fault Diagnostics for GPU Tensor Cores
Optimization	Optimization of Tests for Managing Silicon Defects in Data Centers
P
Parallel (Multisite) Testing	Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing
path selection	A Path Selection Flow for Functional Path Ring Oscillators using Physical Design Data
Pattern Recognition	Language Driven Analytics for Failure Pattern Feedforward and Feedback Yield-Enhanced Probing Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test
pattern retargeting	Multi-die Parallel Test Fabric for Scalability and Pattern Reusability
performance screening	A Path Selection Flow for Functional Path Ring Oscillators using Physical Design Data
permanent faults	Error Model- A New Way of Doing Fault Simulation A Multi-level Approach to Evaluate the Impact of GPU Permanent Faults on CNN's Reliability Runtime Fault Diagnostics for GPU Tensor Cores
Physical diagnostics	Scaling physically aware logic diagnosis to complex high volume 7nm server processors
Physical Optimization	PPA Optimization of Testpoints in Automotive Designs
Physical unclonable function	Modeling Challenge Covariances and Design Dependency for Efficient Attacks on Strong PUFs
Power Device	The Importance and Demand Market of SiC Substrate Defect Testing
Power Inverter	Practical Design Experiences on a Multi-Voltage-Level Motor Driver System using a Power Inverter
Power-Aware pattern generation	Comprehensive Power-Aware ATPG methodology for complex low-power Designs
Pre-distortion	Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing
Probing	Yield-Enhanced Probing Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test
Process variation	Understand VDDmin Failures for Improved Testing of Timing Marginalities ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
Process Variations	The impact of on-chip training to adversarial attacks in Memristive Crossbar Arrays
pseudo-Boolean Optimization	Next Generation Design For Testability, Debug and Reliability Using Formal Techniques
Pulse-Width Modulation	Practical Design Experiences on a Multi-Voltage-Level Motor Driver System using a Power Inverter
Q
Q-bit fluctuations	Qubit fluctuations in quantum systems
quality	Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method
Quantum circuits	Introduction to Quantum Circuit Testing (from test engineers’ perspective)
Quantum computing	Qubit fluctuations in quantum systems
Quantum electronics	Introduction to Quantum Circuit Testing (from test engineers’ perspective)
Qubit	Qubit fluctuations in quantum systems
R
radiation-hardened technique	Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65 nm CMOS Technologies
re-usability	Multi-die Parallel Test Fabric for Scalability and Pattern Reusability
reconfigurable binary logic	Accelerating RRAM Testing with Low-cost Computation-in-Memory based DFT
Reconfigurable Scan Networks	IEEE P1687.1: Extending the Network Boundaries for Test
Redundancy	TSV BIST Repair: Design-For-Test Challenges and Emerging Solution for 3D Stacked IC’s
Redundancy Analysis	Efficient Built-In Self-Repair Techniques with Fine-Grained Redundancy Mechanisms for NAND Flash Memories
Register Transfer Level	RTL-FSMx: Fast and Accurate Finite State Machine Extraction at the RTL for Security Applications
Reinforcement Learning	DeepTPI: Test Point Insertion with Deep Reinforcement Learning
Reliability	Efficient Built-In Self-Repair Techniques with Fine-Grained Redundancy Mechanisms for NAND Flash Memories Just-Enough Stress Test for Infant-Mortality Screening Using Speed Binning Transient Fault Pruning for Effective Candidate Reduction in Functional Debugging Reliability Study of 14 nm Scan Chains and Its Application to Hardware Security Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method Fault Resilience Techniques for Flash Memory of DNN Accelerators Next Generation Design For Testability, Debug and Reliability Using Formal Techniques
reliability analysis	Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65 nm CMOS Technologies
Repeatability and Reproducibility (R&R)	New R&R Methodology in Semiconductor Manufacturing Electrical Testing
resistive open detection	Efficient and Robust Resistive Open Defect Detection based on Unsupervised Deep Learning
Resistive Random-Access Memory	Fault Diagnosis for Resistive Random-Access Memory and Monolithic Inter-tier Vias in Monolithic 3D Integration
Resistive Random-Access Memory (RRAM)	Efficient Low Cost Alternative Testing of Analog Crossbar Arrays for Deep Neural Networks
retargeting	IEEE P1687.1: Extending the Network Boundaries for Test
reuse	Reusing IEEE 1687-Compatible Instruments and Sub-Networks over a System Bus
Reversible scan chain	Industry Evaluation of Reversible Scan Chain Diagnosis
ring oscillator	A Path Selection Flow for Functional Path Ring Oscillators using Physical Design Data
Robust Operation	Practical Design Experiences on a Multi-Voltage-Level Motor Driver System using a Power Inverter
root cause analysis	RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement
RTL CHANGES	Test Generation for an Iterative Design Flow with RTL Changes
Rule-Based	WXAI: Wafer Defect Pattern Classification with Explainable Rule Based Decision Tree Methodology
S
sampling	Application of Sampling in Industrial Analog Defect Simulation
SAT-based ATPG	Neural Fault Analysis for SAT-based ATPG
SAT-Solver	Next Generation Design For Testability, Debug and Reliability Using Formal Techniques
Scalability	Scaling physically aware logic diagnosis to complex high volume 7nm server processors Multi-die Parallel Test Fabric for Scalability and Pattern Reusability
scan chain	Reliability Study of 14 nm Scan Chains and Its Application to Hardware Security
Scan chain diagnosis	Diagnosing Double Faulty Chains through Failing Bit Separation Industry Evaluation of Reversible Scan Chain Diagnosis
scan compression	Diagnosing Double Faulty Chains through Failing Bit Separation
scan test	DEFCON: Defect Acceleration through Content Optimization
scan-based designs	Hardware Root of Trust for SSN-based DFT Ecosystems
scan-based testing	DIST: Deterministic In-System Test with X-masking
Secure Access	IEEE P1687.1: Extending the Network Boundaries for Test
Secure components	GlobalPlatform: 20 years of Security evaluation on secure components
Secure flash memory	Hardware Security in Internet Connected Platforms and Certification
Secure IoT platforms	Hardware Security in Internet Connected Platforms and Certification
security	Zero Trust Approach to IC Manufacturing and Testing
Security Assessment	RTL-FSMx: Fast and Accurate Finite State Machine Extraction at the RTL for Security Applications
Security certification ecosystem	Hardware Security in Internet Connected Platforms and Certification
Security certification process flow	Hardware Security in Internet Connected Platforms and Certification
self-monitoring	Probeless DfT Scheme for Testing 20k I/Os of an Automotive Micro-LED Headlamp Driver IC
self-test	Probeless DfT Scheme for Testing 20k I/Os of an Automotive Micro-LED Headlamp Driver IC
Semiconductor testing	New R&R Methodology in Semiconductor Manufacturing Electrical Testing
SiC	Validation of SPICE models for commercial SiC MOSFETs The Importance and Demand Market of SiC Substrate Defect Testing
Signal Integrity	Yield-Enhanced Probing Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test
Silent Data Errors	Optimization of Tests for Managing Silicon Defects in Data Centers
silicon execution trace	An innovative Strategy to Quickly Grade Functional Test Programs
silicon photonics	Transfer-Matrix Abstractions to Analyze the Effect of Manufacturing Variations in Silicon Photonic Circuits
Silicon test	Industry Evaluation of Reversible Scan Chain Diagnosis
single-event double-node transient	Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65 nm CMOS Technologies
single-event double-node upset	Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65 nm CMOS Technologies
Smart Power	Virtual Prototyping: Closing the digital gap between product requirements and post-Si verification & validation
soft error	Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65 nm CMOS Technologies
Soft Errors	Transient Fault Pruning for Effective Candidate Reduction in Functional Debugging
Software Tests	Optimization of Tests for Managing Silicon Defects in Data Centers
Software-Based Self-Test	An innovative Strategy to Quickly Grade Functional Test Programs
Speed Grading	Just-Enough Stress Test for Infant-Mortality Screening Using Speed Binning
SPICE Model	Validation of SPICE models for commercial SiC MOSFETs
Spiking Neural Network	Fault Modeling and Testing of Memristor-Based Spiking Neural Networks
Stacked ICs	TSV BIST Repair: Design-For-Test Challenges and Emerging Solution for 3D Stacked IC’s
Standard cell characterization	A Comprehensive Learning-Based Flow for Cell-Aware Model Generation
Statistical Testing	Testing of Analog Circuits using Statistical and Machine Learning Techniques
Stimulus Generator	Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing
Streaming Scan Network	Hardware Root of Trust for SSN-based DFT Ecosystems
Stress	DEFCON: Defect Acceleration through Content Optimization Defect-Directed Stress Testing Based on Inline Inspection Results
Stress Test	Just-Enough Stress Test for Infant-Mortality Screening Using Speed Binning Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method
STT-MRAM	DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs
stuck-at faults	Error Model- A New Way of Doing Fault Simulation
Substrate Defect Testing	The Importance and Demand Market of SiC Substrate Defect Testing
Symbolic Execution	GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs
System Level Test	Optimization of Tests for Managing Silicon Defects in Data Centers
System-Level Test	An innovative Strategy to Quickly Grade Functional Test Programs
systematic defect	Diagnosing Double Faulty Chains through Failing Bit Separation
SystemC	GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs
T
TAP Controller	Next Generation Design For Testability, Debug and Reliability Using Formal Techniques
Techniques to achieve Zero Test Escapes	Improvements in the Automated IC Socket Pin Defect Detection
tensor cores	Runtime Fault Diagnostics for GPU Tensor Cores
Test	Enhanced Data Pattern to Detect Defects in Flash Memory Address Decoder Defect-Directed Stress Testing Based on Inline Inspection Results DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs Fully Digital Compute In Memory Design and Test challenges
Test Algorithm	Fault Modeling and Testing of Memristor-Based Spiking Neural Networks DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs
Test and diagnosis	A Comprehensive Learning-Based Flow for Cell-Aware Model Generation
Test chip design	Scan-Based Test Chip Design with XOR-based C-testable Functional Blocks
test compaction	Transforming an n-Detection Test Set into a Test Set for a Variety of Fault Models
test compression	Compression-Aware ATPG DIST: Deterministic In-System Test with X-masking
test fabric	Multi-die Parallel Test Fabric for Scalability and Pattern Reusability
test generation	DEFCON: Defect Acceleration through Content Optimization ML-Assisted Bug Emulation Experiments for Post-Silicon Multi-Debug of AMS Circuits Fault-coverage Maximizing March Tests for Memory Testing Transforming an n-Detection Test Set into a Test Set for a Variety of Fault Models
test metrics	PEPR: Pseudo-Exhaustive Physical Region Testing
test optimization	Multi-die Parallel Test Fabric for Scalability and Pattern Reusability
Test Point Insertion	DeepTPI: Test Point Insertion with Deep Reinforcement Learning
TESTABILITY	Test Generation for an Iterative Design Flow with RTL Changes PPA Optimization of Testpoints in Automotive Designs
Testability Prediction	Neural Fault Analysis for SAT-based ATPG
Testing	Testing Computation-in-Memory Architectures Based on Memristive Devices
Testing Crossbar Arrays	Compact Functional Test Generation for Memristive Deep Learning Implementations Using Approximate Gradient Ranking
Testing Memristive Deep Learning Implementations Compact Test Generation	Compact Functional Test Generation for Memristive Deep Learning Implementations Using Approximate Gradient Ranking
Testing Neural Networks	Compact Functional Test Generation for Memristive Deep Learning Implementations Using Approximate Gradient Ranking
Testing of Quantum circuits	Introduction to Quantum Circuit Testing (from test engineers’ perspective)
Testpoint Insertion	PPA Optimization of Testpoints in Automotive Designs
timing marginality	Understand VDDmin Failures for Improved Testing of Timing Marginalities
timing tests	Understand VDDmin Failures for Improved Testing of Timing Marginalities
transfer matrix	Transfer-Matrix Abstractions to Analyze the Effect of Manufacturing Variations in Silicon Photonic Circuits
transient fault	Next Generation Design For Testability, Debug and Reliability Using Formal Techniques
Transient Faults	Transient Fault Pruning for Effective Candidate Reduction in Functional Debugging
true random number generation	Hardware Root of Trust for SSN-based DFT Ecosystems
TSV	TSV BIST Repair: Design-For-Test Challenges and Emerging Solution for 3D Stacked IC’s
U
Unexpected Silicon Behavior	Using Custom Fault Modelling to Improve Understanding of Silicon Failures
unknown states	DIST: Deterministic In-System Test with X-masking
unsupervised learning	Efficient and Robust Resistive Open Defect Detection based on Unsupervised Deep Learning
Unsupervised Machine Learning	Unsupervised Learning-based Early Anomaly Detection in AMS Circuits of Automotive SoCs
User Defined Fault Model (UDFM)	Using Custom Fault Modelling to Improve Understanding of Silicon Failures
V
Validation	Virtual Prototyping: Closing the digital gap between product requirements and post-Si verification & validation
Verification	Virtual Prototyping: Closing the digital gap between product requirements and post-Si verification & validation
VH-bijection	Scan-Based Test Chip Design with XOR-based C-testable Functional Blocks
Virtual Prototyping	Virtual Prototyping: Closing the digital gap between product requirements and post-Si verification & validation
Void	TSV BIST Repair: Design-For-Test Challenges and Emerging Solution for 3D Stacked IC’s
Volume diagnostics	Scaling physically aware logic diagnosis to complex high volume 7nm server processors
W
wafer defect	Wafer Map Defect Classification Based on the Fusion of Pattern and Pixel Information
Wafer defect map	WXAI: Wafer Defect Pattern Classification with Explainable Rule Based Decision Tree Methodology
Wafer Map	Language Driven Analytics for Failure Pattern Feedforward and Feedback
wafer sort test	Challenges for High Volume Testing of Embedded IO Interfaces in Disaggregated Microprocessor Products
Wafer Test	Yield-Enhanced Probing Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test
Watermarking	ADWIL: A Zero-Overhead Analog Device Watermarking Using Inherent IP Features
Wide-Bandgap	The Importance and Demand Market of SiC Substrate Defect Testing
X
X-masking	DIST: Deterministic In-System Test with X-masking Selective Multiple Capture Test (SMART) XLBIST
X-tolerant	Selective Multiple Capture Test (SMART) XLBIST
XOR APUF	Modeling Challenge Covariances and Design Dependency for Efficient Attacks on Strong PUFs
XOR-gate	Scan-Based Test Chip Design with XOR-based C-testable Functional Blocks
Y
Yield	Efficient Built-In Self-Repair Techniques with Fine-Grained Redundancy Mechanisms for NAND Flash Memories Yield-Enhanced Probing Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test Fault Resilience Techniques for Flash Memory of DNN Accelerators
Yield Analysis and Optimization	Accurate Failure Rate Prediction Based on Gaussian Process Using WAT Data
yield improvement	RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement
Yield Learning	Industry Evaluation of Reversible Scan Chain Diagnosis
Z
zero trust	Zero Trust Approach to IC Manufacturing and Testing
Zero-Overhead	ADWIL: A Zero-Overhead Analog Device Watermarking Using Inherent IP Features

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