ITC 2022: INTERNATIONAL TEST CONFERENCE 2022

A
Abdel-Hafez, Khader	Comprehensive Power-Aware ATPG methodology for complex low-power Designs
Abraham, Jais	Low Capture Power At-Speed Test with Local Hot Spot Analysis to Reduce Over-Test
Adham, Saman	Fully Digital Compute In Memory Design and Test challenges
Agnihotri, Pratishtha	Transfer-Matrix Abstractions to Analyze the Effect of Manufacturing Variations in Silicon Photonic Circuits
Agrawal, Nidhi	Improvements in the Automated IC Socket Pin Defect Detection
Ahmed, Soyed Tuhin	Compact Functional Test Generation for Memristive Deep Learning Implementations Using Approximate Gradient Ranking
Akkapolu, Sankararao	TSV BIST Repair: Design-For-Test Challenges and Emerging Solution for 3D Stacked IC’s
Amarnath, Chandramouli	Efficient Low Cost Alternative Testing of Analog Crossbar Arrays for Deep Neural Networks
Amrouch, Hussam	Wafer Map Defect Classification Based on the Fusion of Pattern and Pixel Information
Anilturk, Onder	Defect-Directed Stress Testing Based on Inline Inspection Results
Appello, Davide	An innovative Strategy to Quickly Grade Functional Test Programs
Arunachalam, Ayush	Unsupervised Learning-based Early Anomaly Detection in AMS Circuits of Automotive SoCs
B
Banerjee, Sanmitra	Fault Diagnosis for Resistive Random-Access Memory and Monolithic Inter-tier Vias in Monolithic 3D Integration
Banerjee, Suvadeep	Unsupervised Learning-based Early Anomaly Detection in AMS Circuits of Automotive SoCs DEFCON: Defect Acceleration through Content Optimization
Basak Chowdhury, Animesh	GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs
Basu, Kanad	Unsupervised Learning-based Early Anomaly Detection in AMS Circuits of Automotive SoCs RIBoNN: Designing Robust In-Memory Binary Neural Network Accelerators
Bernabeu, Gil	GlobalPlatform: 20 years of Security evaluation on secure components
Bernardi, Paolo	An innovative Strategy to Quickly Grade Functional Test Programs
Bhargava, Gaurav	Diagnosing Double Faulty Chains through Failing Bit Separation Using Custom Fault Modelling to Improve Understanding of Silicon Failures
Bhat, Anushree	Selective Multiple Capture Test (SMART) XLBIST
Bhatheja, Kushagra	Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing
Bhattacharya, Mayukh	Application of Sampling in Industrial Analog Defect Simulation
Bhattacharya, Mayukh	Automatic Structural Test Generation for Analog Circuits using Neural Twins
Bhunia, Swarup	AI-Driven Assurance of Hardware IP against Reverse Engineering Attacks
Bishnoi, Rajendra	Accelerating RRAM Testing with Low-cost Computation-in-Memory based DFT
Blair, Steve	Transfer-Matrix Abstractions to Analyze the Effect of Manufacturing Variations in Silicon Photonic Circuits
Blanton, R. D.	PEPR: Pseudo-Exhaustive Physical Region Testing
Bradarić, Filip	Accelerating RRAM Testing with Low-cost Computation-in-Memory based DFT
Brembilla, Fabio	New R&R Methodology in Semiconductor Manufacturing Electrical Testing
Bruce, Isaac	Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing
Buras, Brian	Zero Trust Approach to IC Manufacturing and Testing
Butler, Ken	Zero Trust Approach to IC Manufacturing and Testing Improvements in the Automated IC Socket Pin Defect Detection
C
Cai, Wenjie	Modeling Challenge Covariances and Design Dependency for Efficient Attacks on Strong PUFs
Calabrese, Andrea	An innovative Strategy to Quickly Grade Functional Test Programs
Cardone, Lorenzo	An innovative Strategy to Quickly Grade Functional Test Programs
Carroll, Malcolm	Qubit fluctuations in quantum systems
Catthoor, Francky	Analyzing the Electromigration Challenges of Computation in Resistive Memories
Chaganti, Shravan	Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing
Chaganti, Shravan	Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing
Chakrabarty, Krishnendu	Fault Diagnosis for Resistive Random-Access Memory and Monolithic Inter-tier Vias in Monolithic 3D Integration Automatic Structural Test Generation for Analog Circuits using Neural Twins
Chakraborty, Prabuddha	AI-Driven Assurance of Hardware IP against Reverse Engineering Attacks
Chakravadhanula, Krishna	PPA Optimization of Testpoints in Automotive Designs
Chan, Tung-Yi	Hardware Security in Internet Connected Platforms and Certification
Chang, Wen-Chi	The Importance and Demand Market of SiC Substrate Defect Testing
Chaplot, Nipun	DEFCON: Defect Acceleration through Content Optimization
Chatterjee, Abhijit	ML-Assisted Bug Emulation Experiments for Post-Silicon Multi-Debug of AMS Circuits Efficient Low Cost Alternative Testing of Analog Crossbar Arrays for Deep Neural Networks
Chaudhuri, Arjun	Fault Diagnosis for Resistive Random-Access Memory and Monolithic Inter-tier Vias in Monolithic 3D Integration
Chaudhuri, Arjun	Automatic Structural Test Generation for Analog Circuits using Neural Twins
Chen, Cheng	RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement
Chen, Chun	ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
Chen, Degang	Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing
Chen, Harry H.	Transient Fault Pruning for Effective Candidate Reduction in Functional Debugging
Chen, Leon Li-Yang	WXAI: Wafer Defect Pattern Classification with Explainable Rule Based Decision Tree Methodology
Chen, Yan-Fu	Scan-Based Test Chip Design with XOR-based C-testable Functional Blocks
Chen, Yu	Modeling Challenge Covariances and Design Dependency for Efficient Attacks on Strong PUFs
Chen, Zhitang	RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement
Cheng, Hsueh-Hung	Fault Modeling and Testing of Memristor-Based Spiking Neural Networks
Cheng, Ken Chau-Cheung	WXAI: Wafer Defect Pattern Classification with Explainable Rule Based Decision Tree Methodology
Cheng, Wu-Tung	Industry Evaluation of Reversible Scan Chain Diagnosis
Cheng, Ya-Chi	Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method
Chern, Mason	Diagnosing Double Faulty Chains through Failing Bit Separation
Chickermane, Vivek	PPA Optimization of Testpoints in Automotive Designs
Chien-Hui Chuang, Chien-Hui Chuang	Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method
Chillarige, Sameer	Scaling physically aware logic diagnosis to complex high volume 7nm server processors PPA Optimization of Testpoints in Automotive Designs
Chiu, Chih-Chung	Practical Design Experiences on a Multi-Voltage-Level Motor Driver System using a Power Inverter
Cho, Yonsang	Multi-die Parallel Test Fabric for Scalability and Pattern Reusability
Choi, Jaemoo	4.5Gsps MIPI D-PHY Receiver Circuit for Automatic Test Equipment
Choi, Jung Woo	Probeless DfT Scheme for Testing 20k I/Os of an Automotive Micro-LED Headlamp Driver IC
Choudhury, Muhtadi	TAMED: Transitional Approaches for LFI Resilient State Machine Encoding
Chowdary Nekkanti, Vennela	Fault-coverage Maximizing March Tests for Memory Testing
Chung, Kun Young	Industry Evaluation of Reversible Scan Chain Diagnosis
Correa, Daniel	Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing
Croes, Kristof	Analyzing the Electromigration Challenges of Computation in Resistive Memories
Crouch, Alfred	IEEE P1687.1: Extending the Network Boundaries for Test
D
d'Hondt, Pierre	A Comprehensive Learning-Based Flow for Cell-Aware Model Generation
Dao, Chris C	Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing
Das, Upoma	ADWIL: A Zero-Overhead Analog Device Watermarking Using Inherent IP Features
Debnath, Mukta	GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs
Di Natale, Giorgio	Circuit-to-Circuit Attacks in SoCs via Trojan-Infected IEEE 1687 Test Infrastructure
Dobbin, Allan	Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing
Drechsler, Rolf	Next Generation Design For Testability, Debug and Reliability Using Formal Techniques
Dsouza, Michael	Comprehensive Power-Aware ATPG methodology for complex low-power Designs
Durr, Michael	Application of Sampling in Industrial Analog Defect Simulation
Duvalsaint, Danielle	PEPR: Pseudo-Exhaustive Physical Region Testing
Dziarcak, Edward	Scaling physically aware logic diagnosis to complex high volume 7nm server processors
E
Easter, Jon	Multi-die Parallel Test Fabric for Scalability and Pattern Reusability
Eiki, Makoto	Accurate Failure Rate Prediction Based on Gaussian Process Using WAT Data
Elnawawy, Luai	Probeless DfT Scheme for Testing 20k I/Os of an Automotive Micro-LED Headlamp Driver IC
Endrinal, Lesly	Using Custom Fault Modelling to Improve Understanding of Silicon Failures
F
Faehn, Eric	Circuit-to-Circuit Attacks in SoCs via Trojan-Infected IEEE 1687 Test Infrastructure
Fang, Eric Jia-Wei	ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
Farahmandi, Farimah	RTL-FSMx: Fast and Accurate Finite State Machine Extraction at the RTL for Security Applications ADWIL: A Zero-Overhead Analog Device Watermarking Using Inherent IP Features
Farayola, Praise	Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing
Feng, Ryan	Fault-coverage Maximizing March Tests for Memory Testing
Fernandes dos Santos, Fernando	A Multi-level Approach to Evaluate the Impact of GPU Permanent Faults on CNN's Reliability
Fieback, Moritz	Accelerating RRAM Testing with Low-cost Computation-in-Memory based DFT
Ford, Carl	Defect-Directed Stress Testing Based on Inline Inspection Results
Forte, Domenic	TAMED: Transitional Approaches for LFI Resilient State Machine Encoding
Foutz, Brian	PPA Optimization of Testpoints in Automotive Designs
Francesco, Angione	An innovative Strategy to Quickly Grade Functional Test Programs
G
G, Vaishnavi	TSV BIST Repair: Design-For-Test Challenges and Emerging Solution for 3D Stacked IC’s
Gao, Lei	Fault-coverage Maximizing March Tests for Memory Testing
Gao, Minyan	TAMED: Transitional Approaches for LFI Resilient State Machine Encoding
Garita-Rodríguez, Esteban J.	Challenges for High Volume Testing of Embedded IO Interfaces in Disaggregated Microprocessor Products
Garrity, Doug	Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing
Gebregiorgis, Anteneh	Accelerating RRAM Testing with Low-cost Computation-in-Memory based DFT
Genssler, Paul R.	Wafer Map Defect Classification Based on the Fusion of Pattern and Pixel Information
Gera, Vaibhav	Fault-coverage Maximizing March Tests for Memory Testing
Ghani Zadegan, Farrokh	Reusing IEEE 1687-Compatible Instruments and Sub-Networks over a System Bus
Girard, Patrick	A Comprehensive Learning-Based Flow for Cell-Aware Model Generation
Grosch, Paul	Defect-Directed Stress Testing Based on Inline Inspection Results
Guerrero Balaguera, Juan David	A Multi-level Approach to Evaluate the Impact of GPU Permanent Faults on CNN's Reliability
Gupta, Sandeep	Fault-coverage Maximizing March Tests for Memory Testing
Gupta, Sumeet	RIBoNN: Designing Robust In-Memory Binary Neural Network Accelerators
H
Hamdioui, Said	Testing Computation-in-Memory Architectures Based on Memristive Devices Accelerating RRAM Testing with Low-cost Computation-in-Memory based DFT
Hanel, Markus	A Path Selection Flow for Functional Path Ring Oscillators using Physical Design Data
Hansen, Ethan	Optimization of Tests for Managing Silicon Defects in Data Centers
Hao, Jianye	RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement
Harrant, Manuel	Virtual Prototyping: Closing the digital gap between product requirements and post-Si verification & validation
He, Chen	Enhanced Data Pattern to Detect Defects in Flash Memory Address Decoder Defect-Directed Stress Testing Based on Inline Inspection Results
He, Yi	Functional In-Field Self-Test for Deep Learning Accelerators in Automotive Applications
Herrin, Scott W	Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing
Hong, Jin-Hua	Fault Resilience Techniques for Flash Memory of DNN Accelerators
Hou, Kuan-Wei	Fault Modeling and Testing of Memristor-Based Spiking Neural Networks
Hsiao, Ming-Hsien	Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65 nm CMOS Technologies
Hsieh, Bing-Han	Diagnosing Double Faulty Chains through Failing Bit Separation
Hsieh, Chao-Ho	ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
Hsueh, Sung S.-Y.	ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
Hsueh, Wenhao	Comprehensive Power-Aware ATPG methodology for complex low-power Designs
Hu, Shoubo	RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement
Huang, Andrew Yi-Ann	WXAI: Wafer Defect Pattern Classification with Explainable Rule Based Decision Tree Methodology
Huang, Junhua	Neural Fault Analysis for SAT-based ATPG
Huang, Shi-Yu	Just-Enough Stress Test for Infant-Mortality Screening Using Speed Binning
Huang, Yu	Compression-Aware ATPG DeepTPI: Test Point Insertion with Deep Reinforcement Learning RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement Neural Fault Analysis for SAT-based ATPG
Huch, Martin	A Path Selection Flow for Functional Path Ring Oscillators using Physical Design Data
Huhn, Sebastian	Next Generation Design For Testability, Debug and Reliability Using Formal Techniques
Hukerikar, Saurabh	Runtime Fault Diagnostics for GPU Tensor Cores
Hung, Shao-Chun	Fault Diagnosis for Resistive Random-Access Memory and Monolithic Inter-tier Vias in Monolithic 3D Integration
Huppmann, Marc	Virtual Prototyping: Closing the digital gap between product requirements and post-Si verification & validation
I
Inkley, Benson	Optimization of Tests for Managing Silicon Defects in Data Centers
Inoue, Michiko	Accurate Failure Rate Prediction Based on Gaussian Process Using WAT Data
Ioki, Kazuya	A Practical Online Error Detection Method for Functional Safety Using Three-Site Implications
J
Janicki, Jakub	Industry Evaluation of Reversible Scan Chain Diagnosis
Jin, Hai	Modeling Challenge Covariances and Design Dependency for Efficient Attacks on Strong PUFs
Jin, Xiankun	Unsupervised Learning-based Early Anomaly Detection in AMS Circuits of Automotive SoCs Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing
Joe, Jerin	Test Generation for an Iterative Design Flow with RTL Changes
Joshi, Rajiv	Accelerating RRAM Testing with Low-cost Computation-in-Memory based DFT
K
K S, Vijay Kumar	Selective Multiple Capture Test (SMART) XLBIST
Kai, Yasuyuki	A Practical Online Error Detection Method for Functional Safety Using Three-Site Implications
Kajihara, Seiji	A Practical Online Error Detection Method for Functional Safety Using Three-Site Implications
Kajiyama, Masuo	Accurate Failure Rate Prediction Based on Gaussian Process Using WAT Data
Kalla, Priyank	Transfer-Matrix Abstractions to Analyze the Effect of Manufacturing Variations in Silicon Photonic Circuits
Kalyan, Rahul	Defect-Directed Stress Testing Based on Inline Inspection Results
Kang, Duo-Yao	Scan-Based Test Chip Design with XOR-based C-testable Functional Blocks
Kang, Minho	4.5Gsps MIPI D-PHY Receiver Circuit for Automatic Test Equipment
Karmakar, Rajit	Selective Multiple Capture Test (SMART) XLBIST
Keim, Martin	IEEE P1687.1: Extending the Network Boundaries for Test
Khan, Sadaf	DeepTPI: Test Point Insertion with Deep Reinforcement Learning
Kibria, Rasheed	RTL-FSMx: Fast and Accurate Finite State Machine Extraction at the RTL for Security Applications
Kilian, Tobias	A Path Selection Flow for Functional Path Ring Oscillators using Physical Design Data
Kim, Jason	Zero Trust Approach to IC Manufacturing and Testing Improvements in the Automated IC Socket Pin Defect Detection
Kingham, Eric	Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing
Kizhakkayil, Athulya	Unsupervised Learning-based Early Anomaly Detection in AMS Circuits of Automotive SoCs
Knight, Joel R	Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing
Kumar, Abhishek	Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing
Kundu, Shamik	Unsupervised Learning-based Early Anomaly Detection in AMS Circuits of Automotive SoCs RIBoNN: Designing Robust In-Memory Binary Neural Network Accelerators
Kundu, Subhadip	Using Custom Fault Modelling to Improve Understanding of Silicon Failures
Kuo, Cheng-Sian	Diagnosing Double Faulty Chains through Failing Bit Separation
L
L'Esperance, Nicholai	Scaling physically aware logic diagnosis to complex high volume 7nm server processors
Ladhar, Aymen	A Comprehensive Learning-Based Flow for Cell-Aware Model Generation
Lai, Smith	Comprehensive Power-Aware ATPG methodology for complex low-power Designs
Laisne, Michael	IEEE P1687.1: Extending the Network Boundaries for Test
Larsson, Erik	Reusing IEEE 1687-Compatible Instruments and Sub-Networks over a System Bus
Latty, Raphaël	Wafer Map Defect Classification Based on the Fusion of Pattern and Pixel Information
Lee, Chen-Shiun	WXAI: Wafer Defect Pattern Classification with Explainable Rule Based Decision Tree Methodology
Lee, Kuen-Jong	Scan-Based Test Chip Design with XOR-based C-testable Functional Blocks
Lee, Seongkwan	4.5Gsps MIPI D-PHY Receiver Circuit for Automatic Test Equipment
Lehmann, Mark	Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing
Lei, Jun-Yang	ML-Assisted Bug Emulation Experiments for Post-Silicon Multi-Debug of AMS Circuits
Lerner, David	Optimization of Tests for Managing Silicon Defects in Data Centers
Leventhal, Ira	Improvements in the Automated IC Socket Pin Defect Detection
Li, Boxuan	Fault-coverage Maximizing March Tests for Memory Testing
Li, James	Introduction to Quantum Circuit Testing (from test engineers’ perspective) ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption Diagnosing Double Faulty Chains through Failing Bit Separation
Li, Jian-De	Yield-Enhanced Probing Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test
Li, Jin-Fu	DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs
Li, Katherine Shu-Min	WXAI: Wafer Defect Pattern Classification with Explainable Rule Based Decision Tree Methodology Yield-Enhanced Probing Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test
Li, Min	DeepTPI: Test Point Insertion with Deep Reinforcement Learning
Li, Pengyun	RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement
Li, Wei	PEPR: Pseudo-Exhaustive Physical Region Testing
Li, Yanjing	Functional In-Field Self-Test for Deep Learning Accelerators in Automotive Applications
Liang, Chia-Wei	Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65 nm CMOS Technologies
Liao, Gordon	Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method
Liao, Peter Yi-Yu	WXAI: Wafer Defect Pattern Classification with Explainable Rule Based Decision Tree Methodology
Liao, Yiwen	Wafer Map Defect Classification Based on the Fusion of Pattern and Pixel Information Efficient and Robust Resistive Open Defect Detection based on Unsupervised Deep Learning
Lin, Wei-Chen	ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
Lin, Yunkun	Fault-coverage Maximizing March Tests for Memory Testing
Liou, Jing-Jia	Transient Fault Pruning for Effective Candidate Reduction in Functional Debugging
Liu, Wei	Modeling Challenge Covariances and Design Dependency for Efficient Attacks on Strong PUFs
Lotfi, Atieh	Error Model- A New Way of Doing Fault Simulation
Lou, Yunfei	Fault-coverage Maximizing March Tests for Memory Testing
Lu, Juin-Ming	Fault Modeling and Testing of Memristor-Based Spiking Neural Networks
Lu, Shyue-Kung	Efficient Built-In Self-Repair Techniques with Fine-Grained Redundancy Mechanisms for NAND Flash Memories Fault Resilience Techniques for Flash Memory of DNN Accelerators
M
Ma, Kwondo	Efficient Low Cost Alternative Testing of Analog Crossbar Arrays for Deep Neural Networks
Maheshwari, Madhur	Scaling physically aware logic diagnosis to complex high volume 7nm server processors
Malhotra, Akul	RIBoNN: Designing Robust In-Memory Binary Neural Network Accelerators
Malige, Sandya Rani	TSV BIST Repair: Design-For-Test Challenges and Emerging Solution for 3D Stacked IC’s
Manchukonda, Likith Kumar	Comprehensive Power-Aware ATPG methodology for complex low-power Designs
Mao, Hui	Neural Fault Analysis for SAT-based ATPG
Mayahinia, Mahta	Analyzing the Electromigration Challenges of Computation in Resistive Memories
Menda-Shabat, Rachel	Latest Cybersecurity regulations, certifications and labeling trends
Mitra, Subhasish	PEPR: Pseudo-Exhaustive Physical Region Testing
Mittal, Soumya	Industry Evaluation of Reversible Scan Chain Diagnosis
Miyase, Kohei	Efficient Built-In Self-Repair Techniques with Fine-Grained Redundancy Mechanisms for NAND Flash Memories A Practical Online Error Detection Method for Functional Safety Using Three-Site Implications Fault Resilience Techniques for Flash Memory of DNN Accelerators
Mrugalski, Grzegorz	DIST: Deterministic In-System Test with X-masking
Mukherjee, Nilanjan	Test Generation for an Iterative Design Flow with RTL Changes
Muttaki, Md Rafid	ADWIL: A Zero-Overhead Analog Device Watermarking Using Inherent IP Features
N
Nadeau-Dostie, Benoit	Configurable BISR Chain For Fast Repair Data Loading
Najafi-Haghi, Zahra Paria	Efficient and Robust Resistive Open Defect Detection based on Unsupervised Deep Learning
Nakamura, Tomoki	Accurate Failure Rate Prediction Based on Gaussian Process Using WAT Data
Nandakumar, Bharath	Scaling physically aware logic diagnosis to complex high volume 7nm server processors PPA Optimization of Testpoints in Automotive Designs
Natarajan, Karthikeyan	Comprehensive Power-Aware ATPG methodology for complex low-power Designs
Natarajan, Suriyaprakash	DEFCON: Defect Acceleration through Content Optimization
Niccoletti, Alessandro	An innovative Strategy to Quickly Grade Functional Test Programs
Nicholson, Shaun	Industry Evaluation of Reversible Scan Chain Diagnosis
Niewenhuis, Benjamin	Improving structural coverage of functional tests with checkpoint signature computation
Nigh, Chris	PEPR: Pseudo-Exhaustive Physical Region Testing Diagnosing Double Faulty Chains through Failing Bit Separation
Nirmaier, Thomas	Virtual Prototyping: Closing the digital gap between product requirements and post-Si verification & validation
O
Oak, Chaitali	DEFCON: Defect Acceleration through Content Optimization
P
Pagani, Alberto	New R&R Methodology in Semiconductor Manufacturing Electrical Testing
Pan, Ze-Wei	DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs
Papameletis, Christos	PPA Optimization of Testpoints in Automotive Designs
Park, Cheolmin	4.5Gsps MIPI D-PHY Receiver Circuit for Automatic Test Equipment
Parley, Martin	Industry Evaluation of Reversible Scan Chain Diagnosis
Paudel, Bijay Raj	The impact of on-chip training to adversarial attacks in Memristive Crossbar Arrays
Pavlidis, Antonios	Circuit-to-Circuit Attacks in SoCs via Trojan-Infected IEEE 1687 Test Infrastructure
Pelz, Georg	Virtual Prototyping: Closing the digital gap between product requirements and post-Si verification & validation
Perumkunnil, Manu	Analyzing the Electromigration Challenges of Computation in Resistive Memories
Petersén, Kim	Reusing IEEE 1687-Compatible Instruments and Sub-Networks over a System Bus
Ping, Larry	Probeless DfT Scheme for Testing 20k I/Os of an Automotive Micro-LED Headlamp Driver IC
Piumatti, Davide	An innovative Strategy to Quickly Grade Functional Test Programs
Pomeranz, Irith	Test Generation for an Iterative Design Flow with RTL Changes Transforming an n-Detection Test Set into a Test Set for a Variety of Fault Models
Portolan, Michele	Circuit-to-Circuit Attacks in SoCs via Trojan-Infected IEEE 1687 Test Infrastructure IEEE P1687.1: Extending the Network Boundaries for Test
Price, David	Defect-Directed Stress Testing Based on Inline Inspection Results
Q
Quer, Stefano	An innovative Strategy to Quickly Grade Functional Test Programs
R
Raha, Arnab	Unsupervised Learning-based Early Anomaly Detection in AMS Circuits of Automotive SoCs RIBoNN: Designing Robust In-Memory Binary Neural Network Accelerators
Rahaman, Hafizur	Testing of Analog Circuits using Statistical and Machine Learning Techniques
Rahman, M Sazadur	RTL-FSMx: Fast and Accurate Finite State Machine Extraction at the RTL for Security Applications
Rai, Prateek Kumar	PPA Optimization of Testpoints in Automotive Designs
Rajendra Pharande, Aditya	Fault-coverage Maximizing March Tests for Memory Testing
Rajski, Janusz	DIST: Deterministic In-System Test with X-masking Test Generation for an Iterative Design Flow with RTL Changes Hardware Root of Trust for SSN-based DFT Ecosystems
Ranganathan, Lavakumar	Using Custom Fault Modelling to Improve Understanding of Silicon Failures
Rathert, Jay	Defect-Directed Stress Testing Based on Inline Inspection Results
Ravi, Srivaths	Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing
Ravichandran, Satish	PPA Optimization of Testpoints in Automotive Designs
Rearick, Jeff	IEEE P1687.1: Extending the Network Boundaries for Test
Rech, Paolo	A Multi-level Approach to Evaluate the Impact of GPU Permanent Faults on CNN's Reliability
Redburn, Robert	Scaling physically aware logic diagnosis to complex high volume 7nm server processors
Ren, Juxiang	Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing
Rimolo-Donadio, Renato	Challenges for High Volume Testing of Embedded IO Interfaces in Disaggregated Microprocessor Products
Robinson, John	Defect-Directed Stress Testing Based on Inline Inspection Results
Rodriguez, Thomas	Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing
Rodriguez Condia, Josie Esteban	A Multi-level Approach to Evaluate the Impact of GPU Permanent Faults on CNN's Reliability
Ryu, HyungSun	4.5Gsps MIPI D-PHY Receiver Circuit for Automatic Test Equipment
S
Saha, Anurup	Efficient Low Cost Alternative Testing of Analog Crossbar Arrays for Deep Neural Networks
Saha, Debasri	GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs
Sahasrabudhe, Shubhada	Optimization of Tests for Managing Silicon Defects in Data Centers
Sathaye, Abhijit	DEFCON: Defect Acceleration through Content Optimization
Saville, Barry	Defect-Directed Stress Testing Based on Inline Inspection Results
Saxena, Nirmal	Runtime Fault Diagnostics for GPU Tensor Cores Error Model- A New Way of Doing Fault Simulation
Schlichtmann, Ulf	A Path Selection Flow for Functional Path Ring Oscillators using Physical Design Data
Shanhbag, Narish	In-Memory Computing: History, Overview, Current and Future Directions
Sharma, Manish	Industry Evaluation of Reversible Scan Chain Diagnosis
Sheikh, Abalhassan	Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing
Sheth, Kunal	Fault-coverage Maximizing March Tests for Memory Testing
Shi, Zhengyuan	DeepTPI: Test Point Insertion with Deep Reinforcement Learning
Shieh, Ming-Der	Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method
Shintani, Michihiro	Accurate Failure Rate Prediction Based on Gaussian Process Using WAT Data
Singh, Abhairaj	Accelerating RRAM Testing with Low-cost Computation-in-Memory based DFT
Singh, Adit	Understand VDDmin Failures for Improved Testing of Timing Marginalities
Singhal, Sarthak	PPA Optimization of Testpoints in Automotive Designs
Sinha, Arani	Multi-die Parallel Test Fabric for Scalability and Pattern Reusability
Sinhabahu, Nadun	Yield-Enhanced Probing Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test
Soh, Weng Joe	Enhanced Data Pattern to Detect Defects in Flash Memory Address Decoder
Solignac, Beatrice	Application of Sampling in Industrial Analog Defect Simulation
Song, Peilin	Reliability Study of 14 nm Scan Chains and Its Application to Hardware Security
Sonza Reorda, Matteo	A Multi-level Approach to Evaluate the Impact of GPU Permanent Faults on CNN's Reliability
Srimani, Supriyo	Testing of Analog Circuits using Statistical and Machine Learning Techniques
Srivastava, Ankush	Low Capture Power At-Speed Test with Local Hot Spot Analysis to Reduce Over-Test
Stellari, Franco	Reliability Study of 14 nm Scan Chains and Its Application to Hardware Security
Stratigopoulos, Haralampos	Circuit-to-Circuit Attacks in SoCs via Trojan-Infected IEEE 1687 Test Infrastructure
Su, Fei	Unsupervised Learning-based Early Anomaly Detection in AMS Circuits of Automotive SoCs
Sur-Kolay, Susmita	GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs
T
Tahoori, Mehdi	Analyzing the Electromigration Challenges of Computation in Resistive Memories Compact Functional Test Generation for Memristive Deep Learning Implementations Using Approximate Gradient Ranking
Tajik, Shahin	TAMED: Transitional Approaches for LFI Resilient State Machine Encoding
Talukdar, Jonti	Automatic Structural Test Generation for Analog Circuits using Neural Twins
Tan, Pai-Yu	Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method
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Thommondru, Meghana	Fault-coverage Maximizing March Tests for Memory Testing
Tille, Daniel	A Path Selection Flow for Functional Path Ring Oscillators using Physical Design Data
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Tsai, Elddie	Comprehensive Power-Aware ATPG methodology for complex low-power Designs
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U
Uezono, Takumi	Functional In-Field Self-Test for Deep Learning Accelerators in Automotive Applications
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V
V. Leiva Rojas, Meizel	Multi-die Parallel Test Fabric for Scalability and Pattern Reusability
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von Staudt, Hans Martin	IEEE P1687.1: Extending the Network Boundaries for Test
W
Waicukauski, John	Selective Multiple Capture Test (SMART) XLBIST
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X
Xanthopoulos, Constantinos	Zero Trust Approach to IC Manufacturing and Testing Improvements in the Automated IC Socket Pin Defect Detection
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Y
Yang, Bin	Wafer Map Defect Classification Based on the Fusion of Pattern and Pixel Information Efficient and Robust Resistive Open Defect Detection based on Unsupervised Deep Learning
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Z
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