ABSTRACT. Before a full device fabrication, test structures such as MOS-capacitors (MOSCAPs) are typically used to evaluate how specific fabrication steps affect the quality of SiC-oxide interface. The conductance method is a well-known characterization method for MOSCAPs, allowing to extract both the amount of traps and their time responses. An application of the conductance method to SiC power MOSFETs was also shown to be a useful method to analyze the SiC-oxide interface that can be further utilized for understanding the interface behavior after reliability tests. The importance of ac- and ramp-C-V MOSCAP/MOSFET characterization is on the other hand two-fold: Measurements of application-relevant C-V characteristics and evaluation of the quality of SiC-oxide interface. However, MOSCAPs do not allow for evaluating the two-voltage dependent behavior of MOSFETs during switching. Understanding the footprint of the slow and fast traps within the measured C-V and I-V device characteristics of SiC power MOSFETs is of great interest for both device manufacturers and system engineers. With an assistance of advanced simulations, evidence of the dynamic nature of traps was observed for SiC power MOSFETs at the switching transients. Overall, the selected examples point out that combining experimental characterization and intricate simulations is the best way to understand the gate-oxide reliability of SiC power MOSFETs relevant for their field operation.

ABSTRACT. An advanced structural and physical model of Intermediate-Layer-Dielectric (ILD) cracking in a planar gate under short-pulse short-circuit conditions has been developed as a continuation of our previous studies. This approach utilizes an energy-based Rankine damage model, which is applied based on the mechanical properties of SiO2. The Rankine model has been seamlessly integrated into a comprehensive 2D electrothermal-metallurgical and elastoplastic-mechanical framework, which accounts for both the high-temperature rise and its return to its reference value. In a novel approach, multiple repetitive mechanical cycles were simulated to evaluate the progression and rate of crack penetration, with variations in parameters such as pulse duration and damage model coefficients. This model illustrated the evolution of crack formation and direction during cycling, in alignment with the crack progression observed experimentally in microsections.

ABSTRACT. Losses in SiC MOSFETs implemented in power conversion circuits have a direct impact on conversion efficiency and power density. Higher gate voltage can reduce SiC MOSFET losses, but there is concern that it reduces the TDDB lifetime of the gate oxide. In this study, a more accurate TDDB lifetime evaluation method is proposed for SiC MOSFETs implemented in power conversion circuits. Experiments show that the mean time to failure (MTTF) of the proposed test method is longer than that of the conventional test method.

ABSTRACT. This paper will investigate influencing factors (gate voltage, switch on time etc.) on the dynamic behaviour of the source-drain characteristic (VSD) of SiC-MOSFETs in TO-housing with a voltage class of 1200 V with nearly the same RDS(ON) of 80mΩ, which is needed for the temperature read-out during the power cycling or other reliability test via the VSD(T) method. In total ten different technologies from different manufacturer as well as chip generations were analyzed. If the off-gate voltage is not sufficiently negative during temperature read-out, a run-in behavior of the forward voltage of the body diode up to a static value occurs for every manufacturer, which should be avoided when determining the temperature of the chip. Otherwise, large errors in temperature detection can be made and a possible gate under- and overshoots due to high parasitic gate loops of a power cycling test bench have stronger impact on the transient response of the VSD. Therefore, a sufficiently negative gate voltage should be applied to close the n-channel completely – even below the datasheet. Further, it has been confirmed that some manufacturers still face a transient VSD response, although the gate voltage is already very negative, which could make the temperature read-out quite complicated.

ABSTRACT. The paper presents a wide frequency band characterization for modeling discrete SiC MOSFET - TO247 package. The data analysis is conducted for several components and for three configurations driving to several impedances to characterize. An accurate RLC model of the transmission behavior between two ports is given over 1 MHz to 1 GHz. Moreover, the performance of the differential impedance, which is a generic indicator that eases the identification process, is discussed. Some conclusions are provided on the best way to run the characterization

ABSTRACT. This work investigates the initial electrical parameter drift in 150 nm gate-length GaN-on-SiC HEMTs subjected to DC high-temperature operating life stress for up to 96 hours at multiple baseplate temperatures. Junction temperature was estimated to assess the actual operating temperature of the device under stress conditions. A transient current IDS drift was observed, evolving differently with temperature. Electrical characterizations revealed threshold voltage shifts associated with trap dynamics. Drain-lag (DL) increased while gate-lag (GL) remained stable, indicating a dominant role of buffer traps over surface effects. Schottky diode analysis showed no significant gate degradation, suggesting that bulk-related trapping mechanisms are the main contributors to electrical shifts.

ABSTRACT. While traditional high-performance receivers use GaAs technologies offering very low noise but poor protection against electromagnetic aggression, GaN-based LNAs make it possible to eliminate the RF protection device (whose insertion loss significantly degrades the noise figure, by 50% to 100%). While the potential of such GaN LNAs is not disputed, their behavior under electromagnetic (EM) aggression at different levels is not yet well known; but it must be taken into account because these EM signals can be detrimental to their use in telecommunication or radar systems. The objective of this work is to evaluate a batch of three LNAs of the same design when subjected to a stepwise RF stress using a continuous RF (CW) signal within its frequency bandwidth. By using an experimental bench allowing in-situ measurements of S-parameters and noise factors, beyond the capabilities of the conventional stress bench, it is possible to cross-reference measurements of DC, RF (linear and non-linear) and high-frequency noise factors before, during and after the stress sequences. For the tested LNAs, RF signals between 35 and 65 dB above the input power compression point are applied without degradation of S-parameters or noise figure. Higher amplitude signals degrade some grid fingers of the first HEMT stage. The originality of our experimental bench lies in the possibility of unambiguously determining the history of the degradation process at each step of the stress sequence.

ABSTRACT. A modified design of RC-inverter power-rail ESD clamp circuit realized in a 0.5-μm GaN-on-Si technology is proposed in this article. This study carefully verified the proposed design by SPICE simulation and test chip measurement. The experimental results show that the DC standby leakage under 6 V is 6.9 μA, and there is no transient leakage current during normal power-on conditions. Regarding the ESD robustness, the positive and negative TLP failure currents are 4.8 and -5.8 A, respectively. The positive and negative HBM levels are 4500 and -5500 V, respectively. Therefore, the proposed design can be integrated into GaN ICs to enhance the whole-chip ESD robustness.

ABSTRACT. Dynamic model of ESD protection devices presents many advantages to simulate the response of these components when they are submitted to very high-level transient pulses such as EMP (electro-magnetic pulses) residual0. Dynamic models extracted from frequency measurements will be used to demonstrate how such measurement can provide a complete dynamic model (including fast response and thermal effect of ESD device protection). Doing so, a topology composed of a capacitor in parallel to a snapback protection will be studied in order to decide whether or not it is interesting to used dynamic model obtained from frequency measurement over usual quasi-static model to predict a component failure.

ABSTRACT. 3D integration technologies are essential for classical microelectronics but also for upcoming quantum computing devices. Ongoing miniaturization in this context challenges modern failure analysis and consolidates the need for efficiently detecting defects. Here, we review our latest work in context to AI-powered failure analysis workflows. Non-destructive scanning acoustic microscopy (SAM) is applied to measure the underlying image data. Examples comprise through silicon vias (TSVs), to wafer to wafer bonding technologies or flip chip bonding, etc. . We show how artificial intelligence-based image enhancement, advanced object detection and semantic segmentation drives modern failure analysis. For the segmentation we utilize a ML-based technique, whereas for the object detection, methods like YOLO etc. are utilized. Furtherer different image enhancement model architectures are tested on their ability to generalize on a large dataset and restrict unphysical hallucination but also in terms of evaluation time and power consumption. Note, that our presented workflow is not limited to SAM generated image data and can be extended to other imaging techniques.

ABSTRACT. Good thermal performance and thermomechanical stability is required for baseplate solder layers in power modules. Intermetallic compounds, which are formed during the solder process, ensure a strong interconnection. Diffusion, induced by high temperature, in solid state of certain elements into structures of other elements can result in the formation of voids or changes in the mechanical properties. In this work the effect of long term high temperature storage on the baseplate solder layer is evaluated using non-destructive and destructive methods. Parameters for accelerated testing were identified within this study. Variations of temperatures, storage durations and materials were investigated. Furthermore, the influence of structural change to thermal resistance is examined by comparing different species of aged and damaged structures.

ABSTRACT. Lifetime assessments only based on silicon wear-out mechanisms are insufficient to explain electrical parameter drifts of devices aged at high temperatures for long durations. This complexifies predictions for semiconductor device aging. An alternative approach has been adopted in this study to explain these electrical drifts, by taking into account the interaction of the silicon and its encapsulation. Specifically, this analysis is performed on a degraded Bandgap Voltage Reference circuit embedded in an encapsulated Integrated Circuit, previously aged during High Temperature Operating Life test conditions for 6500 h at a junction temperature of 165 °C. Aged samples showed oxidized and deformed packages, that can explain the electrical parameter drift measured in the circuit as recovery was observed after samples decapsulation, reducing the interaction between silicon and package.

ABSTRACT. High Temperature Reverse Bias (HTRB) testing is a critical reliability assessment for power semiconductor devices, evaluating long-term stability under high reverse bias conditions. While leakage current is the primary parameter monitored, mechanical stress from thermal expansion can also impact device reliability. This study introduces a novel approach for on-line strain monitoring of the package during HTRB using Fiber Bragg Grating (FBG) sensors. A TO-247 high-voltage Si diode was equipped with two FBG sensors to simultaneously monitor temperature variations and mechanical deformations. Experimental results demonstrate that strain variations correlate with leakage current fluctuations, suggesting that mechanical deformation influences leakage current evolution. This technique provides valuable insights into degradation mechanisms in power devices, enhancing the reliability assessment of HTRB testing.

ABSTRACT. Epoxy potting resin moisture diffusion parameters need to be characterized in order to assess the kinetics and the amount of absorbed moisture in power modules. For this reason, we propose to combine two characterization approaches on two different potting resins: methods with constant and with stepped moisture stress. By confronting results obtained with the two methods, the variables impacting the moisture diffusion parameters are identified. The saturated moisture concentration increases linearly with the applied humidity levels environment while the moisture diffusion coefficient can be modelled with a modified Arrhenius equation with the temperature and the initial moisture concentration.

ABSTRACT. Prismatic lithium-iron-phosphate (LiFePO4) battery diffusion is growing, and their thermal management is an important issue nowadays. This study investigates the definition of a test bench to assess the effects of temperature on prismatic cells and a direct liquid technique for thermal management. Finite Element Method (FEM) simulations are used to analyze possible effective heat exchanger, that occupies minimal space while ensuring effective heat exchange and maximum uniformity on the external surface of the cell. For the evaluation of the test bench, two cells were compared, one maintained colder than the other, both with at charge and discharge cycles of 1C continuously. The test bench is realized assessing both electrical and thermal parameters using a supervision and control algorithm. The methodology presented here is the basis for a study of the degradation of prismatic cells by charging cycles by thermosetting them at different temperatures.

ABSTRACT. As the line width of DRAM products circuit shrink, defects by incorrect connection between electric circuits or disconnection within line have been representative bottlenecks in improving production yield for all generations. In this paper, we suggested a Bidirectional 1D-CNN model for classifying Failure Current which is measured in specific circuit area and used for detecting exquisite defects’ type segmentation. So It is important to get diverse shape of as many current as possible. And from model point of view, more diverse features could be trained by both forward and backward directions of individual currents and oversampling of less frequent occurrence with giving random noises, the decision boundaries of each class could be clearly determined. In addition, open-set recognition was applied so that new types of current that had not been observed before by different product architecture or by new defect could be distinguished from the model and defined as ‘unknown’ currents to secure consistency of classification results. And these unknown data continuously accumulated and clustered as additional new class, so that update model on time. As a result, Our Bidirectional 1D-CNN Model suggested is expected to improve securing the quality or production yield of all generation DRAM products.

ABSTRACT. In this work, failure analysis is carried out for a 12-bit digital analog converter (DA) which is unable to power up at low temperature. The fault characteristics of the device are tested through designed experiments. Based on the simulation analysis and the internal circuit design, the fault location has been determined. The results shows that the bandgap reference circuit in the startup circuit cannot be started. This is because of the comprehensive effect of the large charging current of the current limiting diode and the slow charging speed of the application circuit. And the large charging current is induced by the large process deviation. Finally, some suggestions are provided for the subsequent products.

ABSTRACT. White, phosphor converted, light emitting diodes (LEDs) allowed the widespread adoption of solid-state lighting systems. During the time, very high chromatic rendering index (CRI) LEDs were developed, allowing to develop systems for critical lighting application. In this study, medium power LEDs for indoor lighting were submitted to a long-term stress (almost 7000 hours) in conditions near or exceeding their absolute maximum rating. These devices showed low long-term stability, with a strong decrease in optical power (from 25% for devices stressed at the lowest temperature and current, well within the safe operation area, up to almost 50% for devices stressed at the strongest conditions) and a significant decrease in their colorimetric parameters. Correlated color temperature shifted by hundreds of kelvins and CRI lowered of almost 10 for the strongest stress condition. The analysis of individual phosphor peaks, normalized by their ratio to the blue peak, showed an initial, stress temperature independent, lowering, followed by a recovery kinetic dependent on the peak. Severe back-reflector degradation was observed on devices with encapsulant removed. This suggests that several package-related processes are causing the degradation of the devices, including encapsulant, back-reflector, and individual phosphor component degradation.

ABSTRACT. The photovoltaic market is dominated by crystalline silicon (c-Si) panels; however the low load-bearing capacity of some buildings and specific surface design constraints make this technology not suitable for every application. Flexible crystalline-silicon photovoltaics (Fc-SiPV) recently attracted attention, enabling operation in contexts where light weight and bendable nature can be desirable. However, the bending of the modules can induce cracks which ultimately compromise the overall efficiency and long-term reliability. In this study, hotspots induced by cracks are investigated through EL (electroluminescence) and IR (infrared) thermography techniques performed both indoor and outdoor. The study is carried out on a flexible module made of four IBC Si cells, laminated with a plastic encapsulant. From the module characterization, a mismatch between cells emerged: thanks to EL investigations, cracks were identified as the main cause for the worsening of some cell’s performance; by IR imaging, the local temperature increase was measured. Finally, it was possible to quantify how much power is dissipated in a single cell due to cracks, by measuring the voltages at the single cell’s terminals. These results underline the necessity to examine the effects of cracks in flexible modules, which cause local heating, possibly leading to critical temperatures for the lamination and inducing significant power losses.

ABSTRACT. With the rapid evolution of prognostics and health management, reliability models now require higher accuracy and extrapolation capabilities. Despite advances in measurement technology, a certain degree of measurement error remains inevitable. Additionally, material variability and equipment inaccuracies during manufacturing lead to initial product values that follow a distribution correlated with degradation rates. Significant differences in degradation rates are also observed under various stress combinations. Furthermore, competing failure relationships among different performance parameters make it insufficient to consider only a single parameter. To address these challenges, this paper introduces a novel nonlinear mixed-effects model that accounts for both measurement errors and stochastic effects from random initial conditions. The model efficiently captures the coupling among stress factors and the competing failure relationships among multiple performance parameters. Model parameters are estimated through a combined approach that integrates least squares estimation with maximum likelihood estimation. Finally, the model's effectiveness and superiority were validated using degradation test data from a specific electrolytic capacitor subjected to combined temperature and voltage stresses. This degradation model can be widely applied to various components and shows considerable potential for system-level degradation analysis.

ABSTRACT. The dynamic characteristics of photovoltaic (PV) strings under current mismatch condition impact the performance and reliability of PV systems. This study proposes a digital twin (DT) model for PV string considering mismatch condition, constructing a four-layer architecture comprising the physical, connection, virtual, and decision layer. In the virtual layer, the Sandia Array Performance Model (SAPM) and the Perez model are utilized to transform environmental parameters into module temperature and Plane of Array Irradiance (POAI), thereby establishing a digital replica of normal PV strings based on bidirectional long short-term memory (Bi-LSTM) network. In the decision layer, the solar elevation angle (SEA) is used to construct the current mismatch ratio (CMR), which is incorporated as an additional input to correct the Bi-LSTM-based prediction model, enhancing prediction accuracy under mismatch condition. Experimental results demonstrate that the root mean square error (RMSE) of proposed method decreased from 0.9281 to 0.6767 compared to the traditional method ignoring the impact of current mismatch, while the correlation coefficient R improved from 0.7653 to 0.8752. The proposed method improves current prediction accuracy, particularly during high-mismatch periods in the morning and evening, further enhancing the control precision and operational reliability of PV systems under current mismatch condition.

ABSTRACT. This study proposes a novel method for estimating the State of Health (SOH) of lithium-ion batteries using Electrochemical Impedance Spectroscopy (EIS) data and an Autoencoder (AE) model. The method first analyzes the EIS data through Distribution of Relaxation Times (DRT) to extract eight key features, which are then combined with factors such as ambient temperature and State of Charge (SOC) to accurately predict the SOH of the battery. Experimental results show that the AE model outperforms other models, with an overall RMSE of 2.6542, MAE of 1.8870, and MAXE of 6.7539, indicating high accuracy and stability. Furthermore, the error distributions under various SOC and temperature conditions confirm that the AE model provides consistent performance across different operational environments.

ABSTRACT. Through capacitance-voltage and triangular voltage sweep (TVS) measurements, mobile positively charged ions were observed in both as-deposited amorphous Ta2O5 and crystalline β- Ta2O5 layers obtained after subsequent annealing of amorphous layers at 950 °C in O2 and Ar atmospheres. Analyzing the shift of the characteristic TVS peak corresponding to these defects at different temperatures, we determined the activation energy for ion drift to be 360 meV and 380 meV in amorphous and crystalline Ta2O5 layers, respectively. Ion-coupled mass spectrometry (ICP-MS) measurements revealed that Na was the predominant defect in the as-deposited Ta2O5, with its intensity significantly surpassing that of other defects. Consequently, we attribute the positively charged defects to interstitial Na+ ions, which are likely to be incorporated into the targets used for deposition.

ABSTRACT. This paper presents a study of the SiGe HBT 55nm Breakdown Voltages (BVs) related to Impact-Ionization (II) as an earlier reliability assessment. A non-destructive measurement setup allowing a complete Safe Operating Area (SOA) characterization and a derived study of the BVCEO and BVCBO is presented. An automatic extraction methodology of the Breakdown Voltage is proposed. The HiCuM compact model is validated against measurement using the same measurements methodology. Finally, the evolution of the BVs after a degradation is characterized.

ABSTRACT. In this paper, the thermal model and dynamic stress of 55 nm SiGe HBT are investigated. DC and pulsed measurements are performed to obtain the parameters representative to the thermal behaviour. The device is also stressed in DC and pulsed conditions to study their degradation mechanisms depending on the stress types.

ABSTRACT. GaN HEMT (High Electron Mobility Transistor) are considered as critical components for many military applications (radar, electronic warfare...). To support maturity growth of these GaN technologies, a good understanding of failure mechanisms is necessary. Being able to observe essential technology module as the transistor gate at nanoscale will help in this task. This paper presents a method for large (from 40 μm to 100 μm) STEM (Scanning Transmission Electron Microscopy) lamella preparation to observe a large Region Of Interest (ROI) like the entire transistor gate at a nanoscale resolution from different perspectives. This method is presenting lengthways lamella where the 100 nm gate length is centered on the gate foot, and planar lamella that allows observing the interface between gate foot and GaN semiconductor. After defect localisation by mean of any method like EMMI, LIT, etc, these lamellas could help in defect characterisation. These different perspectives bring a defect statistical view at the scale of one entire transistor active area. TEM is usually used on this kind of analysis. Here, with this cost-effective method, everything is done with a dual beam.

ABSTRACT. In this study, we investigate the electrical properties and reliability of silicon dioxide (SiO2) layers deposited using Low-Pressure Tetraethyl Orthosilicate (LP-TEOS) and Plasma-Enhanced Tetraethyl Orthosilicate (PE-TEOS) methods. Capacitance-voltage (C-V) and current-voltage (I-V) measurements were performed to evaluate dielectric constant variations, leakage currents, and charge trapping mechanisms. The results show that LP-TEOS films exhibit a strong dependence on deposition temperature and gas flow rate, affecting both the flat-band voltage (VFB) shift and interface state density. In contrast, PE-TEOS layers demonstrate improved leakage performance with a dominant Fowler-Nordheim conduction mechanism at higher voltages. Furthermore, stress measurements indicate compressive stress in both deposition methods, with a significant reduction at higher process temperatures. These findings provide valuable insights into optimizing TEOS-based SiO2 films for reliable microelectronic and power device applications.

ABSTRACT. To guarantee the protection and reliability of the highly integrated microelectronic chips, the integrity deposition of the passivation layer is a key parameter. Top and cross-sectional failure analysis investigations are performed to identify the origin of an unwanted layer growth on the Silicon Nitride (Si3N4) passivation on the 3D structure of the silicon chip. Atomic Force Microscope (AFM) topographies of the surfaces and Scanning Electron Microscope (SEM) analysis coupled with Energy dispersive X-ray analysis (EDS) acquired for top and FIB (by Focused Ion Beam) cross-sectional observations are combined to reveal the structure of the defect inside the multi-stack layers.

ABSTRACT. Curing conductive Ag paste to bond dies to a substrate is a common process in chip packaging. However, in high-precision analogue devices with feedback or sampling, there often exists a leakage current between the Vref and GND terminals. In this work, an LCC-packaged high-speed PWM controller is investigated. It is found that the agglomeration of Ag particles in the Ag paste during device operation is the primary cause of failure. Further research shows that burn-in testing followed by re-screening is a simple and effective method to avoid device failure during operation.

ABSTRACT. This paper conducts an in - depth analysis and research on the failure and failure mechanism of a certain transistor resulting from defects in the glass passivation layer on the chip surface. During the low - temperature testing of the transistor, an abnormal leakage failure manifested. A series of methods were employed to analyze the cause of the failure, including Residual Gas Analysis (RGA), de - capping for internal inspection, isolation - exclusion testing, and verification testing. Based on the detection by Scanning Electron Microscope (SEM) and Energy - Dispersive Spectrometer (EDS), the abnormal leakage between the collector and the base is attributed to the combined effect of multiple factors. The influencing factors encompass micro - cracks in the chip surface passivation layer, condensation of internal water vapor in a low - temperature environment, and contamination by trace amounts of mobile ions. The formation of micro - cracks in the passivation layer is ascribed to the abnormal passivation process of the chip. This research holds positive significance for guiding foundries to optimize process control. The analysis and testing methods in this failure case offer crucial reference value for other similar failure analyses at low temperatures.

ABSTRACT. The article proposes a new technique of thermally advanced testing, including combining the electrical and thermal impacts at different conditions, high voltage drain (HVD), tests for thermal cycling (TCT) and thermal shock (TST), includes a comparison of their dependability for power RF LDMOS stresses. It is able to alter and deteriorate the electrical and physical behavior of transistors. The reliability of LDMOSFET devices has been gaining much interest in the development of various space electronic systems and power. To address these issues, we propose a numerical method for physical simulation of nonlinear processes in semiconductor devices, and we implemented an innovative reliability bench for thermal aging procedures. It is highlighted how dependability degradation processes affect both the static and dynamic characteristics. The miller capacitance and transconductance shifts are the main causes of the RF performance loss. The deterioration phenomena were confirmed utilizing a model of a numerical device (Silvaco-Atlas) for the purpose of deeper comprehension of the physical mechanics underneath the shift in parameters following aging tests. Lastly, the study shows that the degradation of N-LDMOS is associated with trapped electrons and interface states (traps) created by hot carriers, which causes a negative charge accumulation at the Si/SiO2 contact. A maximal impact ionization rate is positioned in the gate brink, which leads to the creation of more interface states.

ABSTRACT. In semiconductor packaging, solder is a key material that electrically connects the chip and PCB while forming a mechanical bond. Among various solder alloys, Sn-Ag-Cu (SAC) solder is widely used due to its excellent mechanical reliability. However, its high melting point of 217°C can lead to PCB warpage and reliability issues during a bonding process. To address these concerns, a Sn-Bi-based low-melting-point solder has gained attention, with Sn-Bi-Ag solder being a major research focus due to its improved mechanical properties. Recently, although composite solder joints combining SAC and Sn-Bi solders have been investigated to maximize their advantages while compensating for their drawbacks, studies comparing the effect of solder paste printing condition conditions on SAC/Sn-57Bi-1Ag composite solder joints remain limited. This study investigates the influence of solder paste printing conditions, determined by aspect ratio (Smaller AR and Larger AR), on the microstructure, mechanical properties, and thermal reliability of SAC305/Sn-57Bi-1Ag composite solder joints. The results indicate that, for the Smaller AR condition, Bi diffusion was more uniform along the Cu6Sn5 interface, while for the Larger AR condition, Bi coarsening was observed around the IMC interface. For a low-speed shear test after a thermal shock (-40°C to 85°C, 2,000 cycles), the Smaller AR condition maintained a mixed fracture mode due to uniform Bi diffusion reducing stress concentration at the IMC interface, whereas the Larger AR condition exhibited increased brittle fracture due to Bi coarsening. These results suggest that optimizing Bi diffusion in the Larger AR condition to minimize Bi coarsening and maintaining uniform Bi diffusion in the Smaller AR condition are key factors in enhancing the reliability of SAC305/Sn-57Bi-1Ag composite solder joints.

ABSTRACT. In this study a recently developed accelerated mechanical fatigue testing method working at 200 Hz was applied to determine fatigue life curves of 25 µm gold and gold alloy wire bond loops in LED packages. Finite element method (FEM) simulations were conducted to calculate the thermomechanical stresses induced by a ΔT range of 190 K along the bond wire loop and to establish equivalent loading conditions for mechanical fatigue testing. With the help of a customized test setup, the direction of loading could be precisely adapted to the thermal loading conditions and fatigue failure could be induced at vulnerable sites of the wire bond above the ball or the stich side. Fatigue life curves up to the range up to about 1e4 loading cycles are obtained for four types of Au and Au-alloy wire bonds in commercial and model LED chips. Characterization of the surface morphology and fracture surface of the fatigued wire bonds before and after fracture revealed a clear similarity to the type of defects that occur during operation or during thermal cycling tests. The obtained results validate the applicability of the proposed mechanical test methods for the rapid evaluation of wire bond loops in LED packages.

ABSTRACT. This study developed a direct cooling bonding technology that can minimize the thermal deformation of the power module during the heat sink assembly process with a selective area facial laser irradiation and Cu channel to the backside of power modules using low temperature Sn-58Bi solders. Thermal shock tests were performed based on AEC-Q200 to evaluate the thermal reliability of the direct cooling structure. As a result, the initial joint interface had an average of 8.29% voids and exhibited a decreasing trend gradually with repetitive thermal shocks. Voids inside the bonding area were observed to be less than 9% during thermal shock cycling up to 1000 cycles, which means that did not increase or obviously develop into serious defects during repeated thermal shock tests. Namely, since the void standard of IPC-A-610 (revision G 8-93) sets a defect standard of 30%, the direct cooling technology developed in this study was proof of the possibility for use in practical use as mass production. In addition, this study systematically discusses the heat transfer performance of the direct cooling systems based on computational fluid dynamic (CFD) analysis of the increase and decrease of junction voids under thermal shock reliability tests.

ABSTRACT. Wire bonding is widely used for establishing contact in power electronic packages, making bond wire design critical to package reliability. In this study, an electro-thermo-mechanical Finite Element (FEM) simulation model is developed to study the impact of the loop aspect ratio (λ) and the presence of mold material on the lifetime of the bond wire, specifically focusing on lift-off and heel crack failures. The results indicate that while the lifetime of the bond wire foot may increase in the molded assembly, the heel region experiences a decrease in lifetime. Furthermore, an increase in aspect ratio leads to a reduction in bond foot lifetime, an effect that is further amplified in the molded configuration. In contrast, a higher aspect ratio in the molded assembly increases the lifetime of the bond wire heel, contradicting trends observed in prior studies.

ABSTRACT. With the growing market for foldable displays, there is an increasing demand for standardized test methods to evaluate the bending characteristics of foldable materials. This study analyzed the mechanical principles of the folding mechanisms in commercial foldable displays, thereby focusing on the tension-free folding paths that minimize unnecessary stress during material evaluation. Using theoretical analysis and finite element modeling, we investigated various testing scenarios and their impact on the material stress distribution thereby revealing that a natural-arc folding mechanism with appropriate specimen mounting provide more reliable conditions for evaluating the pure bending characteristics. Further, these findings suggest that thickness-adjusted bottom-mounting methods improve consistency by accurately simulating the ideal folding conditions. This study contributes to the development of standardized testing approaches for foldable display materials, while acknowledging existing industrial practices.

ABSTRACT. This study investigates the high-temperature stability of EMC molded Ag joint structures during thermal aging. The joints were designed with Ag plating on Cu TO-247 substrates to evaluate interfacial bonding stability. After the Post molding cure (PMC) process, densification was achieved by reducing porosity and bond line thickness (BLT) while enhancing interconnection. During thermal aging at 250 °C, sinter neck growth and connected length increased and stabilized after 500 h. The bonding strength remained stable after PMC treatment, following similar change with porosity and BLT, while failure energy increased linearly to 160 mJ at 1000 h. Fracture analysis revealed a transition from interfacial to cohesive failure within the sintered joint after thermal aging, accompanied by elongated fracture traces, indicating enhanced plastic deformation. In this study, we thoroughly investigated the effects of the PMC process on bonding stability and mechanical reliability during thermal aging at 250 °C when bonding commercial Ag nano-porous sheets directly onto Ag plated Cu TO-247 substrate, from the perspective of microstructural development.

ABSTRACT. This study focuses on applying the in-air Cu sintering process to perform the die-attach process and the transfer mold process to make the TO-247-3L (i.e., discrete type power semiconductor) package, and performing the high-temperature reliability test in a harsh environment of 250 °C. TO-247-3L was manufactured through die-attach process using Cu sintering in an air atmosphere, transfer-mold process, and post-mold curing (PMC) process, and then underwent high-temperature environment testing at 250 °C for up to 1000 h. The TO-247-3L package, which underwent a 1,000-hour high-temperature environment reliability test from package manufacturing, showed no oxide formation at any stage, proving the effectiveness of the developed in-air Cu sintering process. The Cu sintering joint showed a slight increase in sintering neck thickness with ~ 30% and interfacial connection ratio with ~19% during the PMC process immediately after transfer molding. However, no increase or decrease in the macroscopic microstructural changes of the Cu sintering joint was observed up to 1000 h at 250 °C in the subsequent high-temperature environment reliability tests. In other words, the microstructural state of the Cu sintering joint after PMC was saturated. Bonding strength also remained at 37–44 MPa after 1000 h of high-temperature environmental reliability test, which demonstrates that Cu sinter bonding does not have a large microstructural sensitivity at a temperature of 250 °C. This study verified the feasibility of in-air Cu sintering for automotive power semiconductor packaging and thoroughly examined the implications of its superiority over Ag sintering in terms of the risk of dimensional change of the bonding interface during operation from a metallurgical perspective.

ABSTRACT. In this paper we investigate by means of electrical characterization the impact of OFF-state stress on RON and VTH of 100- V p-GaN HEMTs. Specifically, we analyzed the different degree of degradation caused by stress on these devices considering a target application of a monolithically-integrated half-bridge circuit. To this end, a custom measurement setup was developed to assess the different electrical stress on the device in Low-side (LS) and High-side (HS) configuration. We switched the device OFF- and ON- periodically (T = 10 µs, TON = 2 µs) for a cumulative time of 1000 s. In the OFF-state VDS,OFF = 50 V while VGSOFF was varied between 0 V and -5 V. RON and VTH increased over stress time for both LS and HS configuration, however in the second case drift was larger than in the first. While hole emission from C-traps in the buffer is the cause of degradation in both LS and HS, in the HS configuration the backgating effect further depletes the 2DEG resulting in an higher degradation level. Finally, also the negative VGSOFF has the effect of building up negative charge in the p-GaN layer that further reduces the 2DEG and results in an overall larger degradation for both RON and VTH.

ABSTRACT. Gallium nitride high-electron-mobility transistors (GaN HEMTs) offer unprecedented power densities but face reliability challenges due to hot-carrier effects in hard switching (HS) conditions. Standard Double Pulse Test (DPT) is usually used to characterize these effects, in conditions that are really close to final application: however concerns have been raised regarding the limitations of this tool to evaluate the impact GaN-specific phenomena. Therefore, this work introduces a novel DPT-based test platform that enables independent voltage and current control while mitigating self-heating and reducing the duration of static stress. A three-phase testing protocol was used to evaluate degradation key parameters over 10⁶ switching cycles on commercial GaN HEMTs, validating its capability to analyze long-term device aging.

ABSTRACT. Over the past few years, Silicon Carbide (S iC) power MOSFETs had a huge success both in terms of performances and impact on market. However, threshold voltage (Vth) instability is still a key aspect to attention, especially in long-term switching behaviour. In this work, we have implemented Dynamic Gate Stress (DGS ) reliability test on an automotive grade, planar-gate, S iC MOSFET. We have assessed the impact of duty cycles values, namely 25 % and 50 %, combined with different Rg values, namely 0 Ω and 6.8 Ω. As a result, a limited impact of duty cycle has been noticed on Vth and on-state resistance (RDS,ON) drifts, independently from the gate resistance value adopted. Besides, for each combination of parameters analyzed, gate-source voltage (VGS ) waveforms have been acquired before and after the stress, and, consequently, a statistical analysis have been implemented. Significant variations in peaks and slew rates have not been noticed.

ABSTRACT. This paper investigates the temperature-dependent breakdown of commercially available GaN-on-Si power transistors during off-state drain step-stress. This setup allows us to obtain novel results on commercially available 650V p-GaN HEMT subjected to step-stress under various conditions of temperature and gate voltage. Previously discussed breakdown mechanisms will be compared with the one observed on the current structure and a physical interpretation will be discussed to explain the phenomenon. Activation energy, Weibull parameters and failure analysis will be explored to provide understanding on the failure mechanisms.

ABSTRACT. In this work the short-circuit robustness of 650 V normally-off GaN HEMT is investigated. DUTs were submitted to single event destructive short-circuits at different drain-source voltage levels. Overall, DUTs exhibited a withstanding time of several hundreds of microseconds. Results showed that the failure is believed to be primarily due a critical junction temperature being exceeded. Besides, the results clearly demonstrated the absence of any critical energy as a failure origin.

ABSTRACT. This paper deals with SiC MOSFET preconditioning techniques with the aim to use Vth measurement as a reliable thermosensitive parameter (TSEP). In particular, the efficiency of the different preconditioning processes is studied for different stress voltages applied to the MOSFET. The time constant of the trapping phenomenon is globally revealed by measurements of the Vth shift over time. This leads to choosing the preconditioning and current applied times carefully. The impact of preconditioning Rdson measurement used as a TSEP is also studied.

ABSTRACT. Transient effects may occur while switching the gate voltage of recent SiC MOSFETs. When measuring the junction temperature by using the body-diode-method, those effects will lead to lead to wrongful junction temperature estimation e.g. in power cycle lifetime testing. This work will present a systematic study of the influence of temperature, measurement current, cycle time and gate voltage on the recently discovered effect for six different devices from three different manufacturers. The main focus will be on the influence of VGS,on during the heating phase of a power cycling test.

ABSTRACT. Reliable operation of Silicon carbide (SiC) MOSFETs is critical for applications like new energy grids and electric vehicles, where they face high-voltage, high-current, and high-power conditions. However, their susceptibility to parameter drift and failure necessitates robust reliability assessment. Traditional power cycling tests, a standard method for evaluating package reliability, suffer from inaccuracies in junction temperature estimation due to device degradation during prolonged testing. Mid-test recalibration introduces further interference, reducing efficiency and affecting test consistency. This paper proposes a novel digital-twin assisted power cycling methodology for SiC MOSFETs. By integrating a calibrated digital model with online electro-thermal monitoring information, we accurately identify and quantify damage types and progression throughout uninterrupted power cycling. This approach eliminates the need for intrusive measurements, provides continuous degradation insights, and significantly improves the accuracy and efficiency of reliability assessment. This contribution facilitates more reliable deployment of SiC MOSFETs in demanding applications.

ABSTRACT. With the large-scale application of electric vehicles, accurate assessment of the remaining capacity of batteries has become a core requirement to ensure the vehicle range and safety. This paper proposes a hybrid model framework which achieves multi-scale accurate prediction of lithium-ion battery capacity loss by synergistically integrating the complementary advantages of Arrhenius model and LSTM neural network. The Arrhenius model quantifies the long-term dominant effects of temperature and cumulative ampere-hours on capacity decay from the physical mechanism level. Neural networks learn the temporal residual feature sequences of dynamic charging and discharging conditions through end-to-end learning, adaptively capturing the short-term disturbances of capacity loss caused by complex transient aging mechanisms. Finally, the capacity loss prediction of the Arrhenius model is superimposed with the LSTM residual correction value to obtain the battery capacity loss prediction result. This paper uses real-time charging data collected by electric vehicles under natural driving conditions to verify the capacity loss characteristics of power batteries in real vehicle use scenarios.

ABSTRACT. The efficiency of wind power systems is coupled to accurate lifetime modelling of the used power modules. Typical power cycling lifetime models depend on junction temperatures. For modules which are limited by substrate solder degradation in power cycling, this might lead to inaccuracies, especially if cooling conditions change. This influence is inspected in this publication. For this purpose, a lifetime model based on substrate solder temperatures is derived by substitution of an existing junction-based model. Next, substrate solder and junction temperatures are calculated from a mission profile for three different cooling conditions. Lifetimes are calculated with each lifetime model and the results are compared. It is observed that the lifetime estimates derived with the substrate solder model and junction-based model differ. Furthermore, the lifetimes estimated with substrate solder temperatures develop differently with respect to the cooling condition compared to those obtained with junction temperatures. It is shown that in this case higher loads in the substrate solder for weaker cooling conditions cause this behavior.

ABSTRACT. SiC MOSFETs have very low thermal capacitance compared to their Silicon counterparts. For that reason, when used in AC/DC or DC/AC applications, they suffer from temperature variation as high as 40 °C at frequencies close to 50 Hz. This temperature variation, also called Power Cycling, may reduce lifetime of power modules using SiC transistors, which was not the case for Silicon based power modules. These high frequency power cycles are indeed poorly modelled or even not considered in the presently available lifetime estimation model of SiC power modules. This paper presents the procedure to take into account these high frequency power cycles when estimating SiC power module lifetime using automotive mission profiles. The mission profile is used to create representative current waveforms flowing through the power module for the entire mission. Thus, instantaneous SiC die temperature (averaged in each switching period) is calculated, based on precise instantaneous loss estimation coupled with accurate thermal impedance model. The result is a junction temperature profile which contains power cycles at the same frequency of the sinusoidal current flowing through the SiC die. The influence of such “high frequency” power cycles in the total lifetime of a SiC power module is then demonstrated using lifetime models found in the literature.

ABSTRACT. In-flight demonstration and verification of electronic devices have become a new method for evaluating radiation effects in space. This project presents the flight test data of bipolar junction transistors (BJTs) and verifies the impact of low dose rate space radiation on BJTs by measuring the current gain variation. The results obtained were comparable to the ground test results. In addition, the total accumulated dose in space was accurately measured using a PMOS dosimeter. This project achieved a precise flight verification of the Enhanced Low Dose Rate Sensitivity (ELDRS) effect on bipolar junction devices.