ABSTRACT. Significant temperature variation in frequencies from 10 to 100 Hz was observed in SiC dies used in inverter or rectifier applications. These fast thermal cycles may significantly reduce the lifetime of SiC power modules. This paper proposes an approach and a testbench to investigate power module aging due to these thermal cycles. This testbench produces die temperature variation up to 40°C at frequencies from 10 to 100 Hz. The stressed power module operates the same way it would do in a real inverter or rectifier application, having the same average temperature and power cycles at the frequency of the sinusoidal current flowing through it. Thermal cycle amplitudes are selected using an accurate thermoelectrical model of all dies in the power module. The Modified Opposition Method is used to calculate the switching and conduction losses of SiC dies. A fast thermal camera then is used to measure dynamic temperature and estimate thermal impedance of these dies. Experimental results in the developed testbench show that the parameter values calculated by the developed algorithm accurately impose the desired high-frequency power cycles in the SiC dies inside a power module.

ABSTRACT. This work presents a thorough analysis of machine learning (ML)-based metamodels to assess the reliability of power electronic modules (PEMs). Accurate lifetime prediction pipelines often require frequent updates on the mechanical state of the PEMs by means of finite element simulations (FESs), which are notoriously slow. This compromise between complexity and precision is the motivation behind this study, which aims to harness models that are otherwise not exploitable due to the long computational time of FESs. We deem that ML models are suited for this task thanks to their fast inference speed and high predictive power. The quality of the models is thoroughly studied throughout this paper by analysing often-overlooked statistical properties that have proven to be crucial to analyse and very informative on the behaviour of the model. We applied the approach as a part of a remaining useful life (RUL) estimation pipeline for failure caused by bond-wire degradation in PEMs, but the framework is application-agnostic and can easily be adapted to different systems and degradation forms. The aim of this paper is to present a rigorous yet accessible metamodel implementation framework to appropriately exploit the strengths of ML models when applied to failure analysis.

ABSTRACT. Smart Plug Tops (SPTs) with sensing capabilities become increasingly important for real-time monitoring and diagnostics in internal combustion engines. However, the deployment of numerous electronic devices and the system's complexity can lead to numerous failures that must be investigated. This research presents a categorization of various failures using a machine learning (ML) technique. The method involves the collection of sensor data during the testing phase of SPTs. This data is then associated with potential failures identified after lifetime analysis. ML model uses features retrieved from these data, such as voltage levels, charge times, current levels, etc. The model is refined using a training and validation method to accurately predict various types of failures, such as electric discharge on the transformer secondary winding, damping diode breakdown, and short circuits between windings. The significant challenge of this work is the limited number of failure samples since the device works under normal conditions at major times and only conducts the failure at minor times. Hence, an upsampling technique was applied to improve this imbalanced dataset. The classification algorithm's performance is measured in terms of accuracy, precision, recall, and F1-score. The results enable the identification of any problem symptoms during acceptance testing and the classification of the probability of a certain failure.

ABSTRACT. For three phase inverters, the failure of the power electronic device MOSFET is one of the main reasons affecting the reliability of the inverter, and the junction temperature swing will mainly affect the remaining life of the MOSFET. This paper finds that under different control strategies, the maximum value of the MOSFET junction temperature swing is different under the same operating conditions. Therefore, a control strategy based on Finite Control Set Model Predictive Control (FCS-MPC) is studied, which can incorporate the junction temperature swing model while considering inverter performance indicators such as THD and average switching frequency, achieving a balanced optimization of inverter reliability and performance. In this paper, the control strategy is verified through simulation.

ABSTRACT. The reliability of electronic components is a critical concern in active implantable medical devices (AIMDs). Among the most commonly used components in these devices, SMD tantalum capacitors have been identified as one of the most problematic due to their higher sensitivity to environmental stresses. This article proposes a methodology for a more appropriate qualification of these components with respect to the mission profile of AIMDs by combining accelerated life testing (ALT) with design of experiments (DoE). Failure Modes, Mechanisms, and Effects Analysis (FMMEA) highlights the dominant stress factors (temperature, humidity, and electrical overstress) and the most significant technological factors (packaging technology, cathode material, size, and manufacturing process). A core part of the methodology is the estimation of a predictive reliability model enhanced through the use of statistical methods.

ABSTRACT. In the production process, there are inevitable differences and correlations between the performance characteristics of different batches of multi-performance characteristics systems, and it is a challenge to accurately assess the reliability of such systems. The following work is carried out in this paper to address the above problems: on the one hand, for each performance characteristic in the system, a Wiener process based on random effects is introduced to describe the degradation process; on the other hand, the correlation between different performance characteristics in the system is described by using the R-vine copula and the optimal R-vine structure is determined based on an algorithm, and parameter estimation is carried out to achieve the reliability assessment of the degradation data of the given different systems. Finally, the degradation process of a typical three-phase inverter circuit is used to illustrate the feasibility of the method.

ABSTRACT. In this work, shock and vibration tests were conducted to study the wear mechanisms of silicon surfaces with different finishing layers in MEMS accelerometers. The surfaces analyzed included those without the anti-adhesion layer and coated with a mono-atomic anti-adhesion layer. Physical analyses using AFM, TEM were performed both in the pristine state and after the mechanical stress tests. Adhesion forces were computed from C-V curves and linked to microscopy results. The study highlighted differences in wear mechanisms among the surfaces and proposed explanations for these differences.

ABSTRACT. The electrical properties of Y2O3 thin films for MEMS applications have been investigated. The study employed conventional J-F (current density-electrical field) characterization, surface potential decay (Kelvin Probe) and thermally stimulated depolarization current (TSDC) to detect electrically active defects The results reveal the presence of different transport mechanisms during self-discharge of electrically stressed films.

ABSTRACT. Nano-electromechanical (NEM) switches offer significant potential for future computing and memory applications due to their low power consumption and ability to operate in high-temperature and radiation-harsh environments. However, there is a lack of studies on the robustness of NEM switches under mechanical loads. In this study, we investigated the performance of 3- and 7-terminal NEM relays under mechanical shocks up to 5000 g and vibrations up to 70 g. The results demonstrate that devices maintain their mechanical functionality, with some variations in the electrical characteristics. These findings underscore the potential of NEMS technology for reliable operation in harsh environments, paving the way for their possible integration into next-generation electronic devices.

ABSTRACT. MEMS sensors have emerged as core components in intelligent devices and automation systems owing to their miniaturization, low power consumption, and high accuracy. These sensors are extensively utilized across diverse fields, including the automotive industry, medical and healthcare sectors, and consumer electronics. Ensuring the stable operation of MEMS sensors is of paramount importance. Noise represents a primary factor compromising the stability of these sensors, as it has been demonstrated to reduce sensitivity, increase circuit design complexity, and jeopardize long-term operational reliability. Traditional denoising techniques, such as Kalman filtering, have proven insufficient to address the evolving demands of MEMS sensors. In contrast, emerging data-driven denoising methods, which rely on large datasets for training, face challenges due to data scarcity and the intricacy of training processes. This paper proposes a novel denoising approach for MEMS sensors that integrates time-frequency conversion with image segmentation. Experimental results demonstrate that the proposed method significantly enhances the stability of MEMS sensors.

ABSTRACT. The field emission and resistive switching processes have been investigated using impedance analysis in Y2O3 thin films for MEMS applications. The study was conducted using metal-insulator-metal (MIM) capacitors and MEMS capacitive switches. The aim is to provide insights on the charge kinetics during these mechanisms. Y2O3 Films fabricated with evaporation and Atomic Layer Deposition (ALD) were analysed. MIM capacitors were used to determine the breakdown field, the onset of field emission, and the transition between volatile-analog resistive switch modes. Impedance analysis was performed at preselected electric fields, both before and after the transition to the low-resistive mode. The results revealed the presence of dielectric charging effects.

ABSTRACT. Communication systems supporting long range interactions are of vital importance for numerous domains in our everyday lives e.g. for airport Radar systems that enables efficient and safe take offs and landings. Electronic components supporting these systems should be robust enough to deal with the high-power burden required in these cases in order to enable the long-range interactions. Radio-Frequency Micro-Electro-Mechanical-Systems (RF MEMS) are devices with great potential to support these implementations from the microwave perspective. Considering the high-power operation of RF MEMS, the so-called self-actuation effect constitutes maybe the most fundamental reliability aspect to be addressed. This work aims to present a straightforward experimental study of the self-actuation in a family of bridge type RF MEMS capacitive switches fabricated in shunt configuration and on coplanar waveguide topology. Bearing in mind the already available knowledge in the field, the study presents a direct monitoring of the self-actuation focusing on the role of the RF signal pulsing scheme. The results are analysed and discussed in conjunction with typical S-parameters and Capacitance-Voltage characteristics.

ABSTRACT. Cryo-CMOS devices are becoming increasingly important for quantum computing applications, but the reliability of those devices down to deep-cryogenic temperatures has only been covered sporadically. In this paper, we investigate the mobility degradation of n-type CMOS devices due to hot carrier stress (HCS) at temperatures from 300 K down to 5 K. We use a modified Arrhenius model, which includes an additional parameter, to accurately capture the hot carrier degradation characteristics over the entire temperature range. Our results show that behavior starts to diverge from the classical model below 175 K. This divergence is attributed to freeze-out effects in the bulk region, which cause an effective positive bulk bias that limits the hot carrier degradation. In the deep-cryogenic regime, this causes the lifetime of the devices to become temperature-independent, approaching a constant value.

ABSTRACT. This study introduces a novel weight freezing technique that significantly minimizes the number of pulses needed for high-accuracy performance in FeFETs under multi-level cell operations. Utilizing this method, only an average of 64 pulses are needed to reach a 90% accuracy ( ~94.4% pulsing number reduction compared to the traditional approach). Additionally, our weight-freezing method effectively enhances network convergence ability when accounting for significant cycle-to-cycle variations (10% variations). Furthermore, the recovery cycling procedure stabilizes multi-level cell (MLC) switching. Combining weight freezing and recovery cycling, FeFET-based synapses exhibit an improvement in Modified National Institute of Standards and Technology (MNIST) recognition, from an initial 30.5% to 90.5%. Thus, this approach combining weight freezing methodology and recovery cycling scheme is attractive for compute-in-memory applications toward stable online training

ABSTRACT. Most of the time, ageing model for digital circuit are based on short time and high stress measurements. Then, ageing is extrapolated in time and for operational condition of use. Does the model correctly predict ageing after several years of use under normal temperature and voltage conditions? This paper presents ageing and measurements of degradation made during more than 20000 hours on an optimized test bench on nine FPGA including 567 ring oscillators each, with different temperature and voltage stresses. In our knowledge, this is the longer ageing test performed on digital circuit. Based on these measures, we compare semi-empirical modelling made with high temperature stresses and short ageing time (1000 hours) with low temperature stresses and long ageing time (20000 hours).

ABSTRACT. This study investigates the effect of a TiO₂ seed layer on the reliability of La-doped Hf₀.₅Zr₀.₅O₂ (La:HZO) metal-ferroelectric-metal (MFM) structures, focusing on the uniformity of remanent polarization (2Pr) and breakdown properties. Previous research using grazing-incidence X-ray diffraction (GIXRD) has shown that the TiO₂ seed promotes a higher O(002) orientation, leading to improved dipole alignment. Through cycling and PUND measurements, we observe that the TiO₂-seeded La:HZO (Sample B) exhibits enhanced 2Pr uniformity compared to its non-seeded counterpart (Sample A). Time-dependent dielectric breakdown (TDDB) analysis reveals that while both samples show similar breakdown times under constant voltage stress (CVS), Sample B shows a better TDDB breakdown uniformity and a higher predicted 10-year safe operating electric field. The improved uniformity can be attributed to the fact that the dipoles in O(002) have only a vertical component (in contrast to O(111)), resulting in smaller variations in the local electric field. These findings indicate that the TiO₂ seed layer improves the uniformity and reliability of La:HZO ferroelectric devices, advancing their potential for commercial applications.

ABSTRACT. We investigated the stability of HEMTs with p-GaN gate as a function of the magnesium doping level. The analysis was carried out based on constant voltage stress tests, capacitance-voltage measurements and numerical simulations. Differences between time to failure for “high” and “low” Mg doping concentration were ascribed to the difference in electric field at the Schottky p-GaN interface. This latter is considered to be responsible for the acceleration of electrons in the p-GaN region and consequently to the failure of the gate stack.

ABSTRACT. Vertical GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) are suitable for highly-efficient power conversion in high-power systems. This study demonstrates three-phase inverter operation using vertical GaN trench MOSFETs capable of the gate overdriving up to 20 V. The fabricated MOSFETs showed minimal variations in the threshold voltage (Vth) and on-resistances (Ron), which allowed the parallel connection of four devices in high or low side of each phase. The output power reached 10.4 kW. After inverter operation, the devices showed the Vth shift and the increase of Ron, where the respective degradations depended on an Mg concentration in a p-type body and driving current. The Vth shift resulted from electron injected to near interface traps on the channel region, while the Ron increase was likely caused by injecting hot electrons into the access region similar to the dynamic Ron in a GaN HEMT. Optimization of the MOS interface would lead to a stable device performance.

ABSTRACT. Short-circuit studies for Power GaN HEMT, initiated in 2013, remain limited and focus on destructive tests. To enable better analysis, repetitive, non-destructive short-circuits were performed, interspersed with electrical characterizations to identify degradation. Tests on 650 V GaN components from two suppliers revealed stability and robustness differences. Initial failures due to loop inductance and parasitic effects required bench optimization and SPICE simulations. Parameter drifts led to hypotheses explaining observed discrepancies.

ABSTRACT. Gallium Nitride High Electron Mobility Transistors (GaN HEMTs) are promising candidates for power electronics but suffer from reliability concerns due to, for instance, their lack of avalanche capability. This study investigates the long-term impact of dynamic overvoltage stress on GaN HEMTs using a newly designed test circuit, UIS3, which isolates key stress factors. Devices were subjected to short-duration repetitive overvoltage stress near their dynamic breakdown voltage. Characterization before and after stress reveals permanent degradation in $C_{DS}$ and $I_{DSS}$, suggesting structural damage within the device. A distinct alteration in the $C_{DS}$ curve is observed, possibly linked to local breakdown in the insulating layer. Higher stress levels accelerate failure, with leakage currents increasing as conductive paths develop. Our results provide new insights into GaN HEMT degradation mechanisms under high-voltage stress and highlight the need for refined reliability models.

ABSTRACT. Measuring gravity requires ever more precise measurement methods. One possibility is the use of quantum gravimetry using Bose-Einstein condensates. Here, a defined number of atoms are electro-magnetically trapped by an atom chip and the gravitational acceleration is measured in an interferometric setup. The structure of the atom chip consists of two parts that have to be reliably joined together. The base material of the two chips is silicon. Gold is used as the conductor material. Since Bose-Einstein condensates can only be produced in an ultra-high vacuum atmosphere, a key requirement is that no polymers are used, as these can outgas. As it is necessary to do without polymers, the electrical conductors are inserted into the chip. Deep reactive ion etching is used for this purpose, followed by passivation using PECVD. As the surface of the chip acts as a mirror in the application, the upper chip must be polished using chemical-mechanical polishing after the electrical conductors have been produced. Another requirement is a high current-carrying capacity of the electrical conductors, which must carry a pulsed current of 2A with a conductor cross-section of 20 * 50 µm². This causes the conductor to heat up, which can result in delamination due to the different thermal expansion coefficients. Furthermore, a low-melting joining process is used here in order to keep the thermal load as low as possible when joining the chips. To ensure reliability, current load tests and mechanical and thermal tests were carried out.

ABSTRACT. In this study, the bonding strength and fracture behavior were investigated of wafer-to-wafer (W2W) bonding chip-scale Chevron-notch (CN) Si specimen using the tensile test with real-time acoustic emission (AE) monitoring. Fracture analysis could be identified to two failure modes, “interface open type” and “matrix crack type”. The bonding strength of the interface open type was slightly higher (6.41 J/m2) than the matrix crack type (6.12 J/m2). On the other hand, the interface open type exhibited higher AE absolute energy (4.0 × 10⁷ aJ), 2.7 s of signal detection duration, and more detected signals compared to the matrix crack type, 2.3 × 10⁷ aJ, 1.6 s, and 10.4 signals, respectively. Conventionally, both bonding strength measurement and microstructural analysis were required to classify fracture types, but AE monitoring enabled real-time identification within the measuring of the bonding strength.

ABSTRACT. This study developed the flux-less solder ball (i.e., Sn-3wt%Ag-0.5wt%Cu) attachment technology (FLAT), a novel and eco-friendly approach that eliminates flux processing during mass reflow while significantly reducing the warpages. Furthermore, the ball grid array (BGA) package applied with FLAT was directly compared with the BGA package manufactured by the conventional mass reflow manufacturing method in terms of thermal cycling reliability. As a result, FLAT made an intermetallic compound (IMC) of less than 1.6 μm at bonding interfaces by an instantaneous laser heat source, and solidified immediately after nucleation, forming a solder ball composed of uniform and fine beta-Sn. In contrast, the conventional mass reflow soldering using flux has caused the formation of massive Cu6Sn5 chunks inside the BGA package, and even the thickness of the IMC at the bonding interface with the pad exceeded 4.8 μm. The interfacial IMC layer suppressed by FLAT suppressed the spalling phenomenon during the continuous thermal cycling tests. In contrast, the interfacial IMC layer formed by the conventional mass reflow process had a relatively long aspect ratio, which promoted interdiffusion with the Sn matrix during thermal cycling, allowing the spalling of a large amount of Cu6Sn5 chunks into the Sn matrix. This distinguished behavior explains the distinct pros and cons of the two processes in thermal shock resistance, which determines the rigidity and heat dissipation properties within the solder. This study systematically addresses the thermal cycling behaviors of BGA packages manufactured by FLAT and MR, and heat transfer performances originated from this IMC growth behavior through numerical calculation.

ABSTRACT. We investigate the thermomechanical behavior of thick copper metallization on polyheaters which are chips dedicated for stressing the thick copper metallizations found in high-end power electronic devices. The degradation mechanisms of these metallizations are known to span from surface roughening to crack formation, but the underlying elemental plastic deformation mechanisms (dislocation activity, stress-assisted diffusion, …) remain elusive. Here, we have combined post-mortem TEM observations of such polyheaters that underwent ultra-fast 300K heating cycles and in-situ TEM heating experiments up to 480°C. Both approaches converge to establish that the dislocation microstructure inside the grains is only slightly modified over these cycles and thus that dislocation-based plasticity cannot explain the crack formation and propagation, along with surface roughening observed in these Cu metallizations.

ABSTRACT. In this study, we investigated the microstructure and mechanical properties of the graphene coated copper and ag hybrid sintered joint during high temperature storage test. After the bonding process, the thermal stability of the hybrid joint was evaluated in the high-temperature thermal aging test for up to 1000 h at 250°C. As thermal aging progressed, the die bonding strength of Ag-Cu-Gr sintered joint was increased from 48.81 MPa at the as-sintered state to maximum of 65.51 MPa at the 500 h. On the other hand, the die bonding strength of Ag-Cu sintered joint was increased from 32.81 MPa at the as-sintered state to maximum of 56.23 at the 200 h. The porosity of the sintered layer decreased from an initial from depending on microstructure and the oxidation of copper.

ABSTRACT. Robustness against humidity is vital for power semiconductors. Depending on the application, power semiconductors can be subjected to very harsh climatic conditions. Compared to conventional silicon IGBTs, silicon carbide devices have higher stress due to faster switching. This paper discusses and presents the results of tests in which the impact of humidity and switching stress were investigated using specially prepared sensitive samples. Self-heating, the influence of climate cycling, and other parameters (including voltage) were also examined in these tests. An additional failure mode that is not triggered in the static HV-H3TRB test is observed and discussed.

ABSTRACT. Significant temperature variation at 50Hz was observed in SiC dies used in inverter applications, which can significantly reduce lifetime of SiC transistors. However, this important temperature variation at 50Hz in HEMT GaN transistors was never observed before but they exist and may also reduce lifetime of GaN transistors used in PFC or inverter applications. This paper shows by simulation that junction temperature in HEMT GaN dies may have a temperature swing of up to 40°C in ordinary applications. For that, precise instantaneous loss model is developed for a specific GaN transistor. Then, a precise method to estimate dynamic temperature and thermal impedance of different parts of GaN components is developed. This method uses Thermo-Sensitive Electrical Parameter (TSEP) to measure thermal impedance between the die and the heatsink. Experimental measurements of thermal cycle of GaN dies with representative instantaneous loss profile is shown in order to validate the dynamic junction temperature estimation model as well as to show that high frequency power cycle in GaN transistors is a strong stressor to the device aging process.

ABSTRACT. In this study, the surge current capability of a 60 A–1200 V 4H-SiC diode fabricated by paralleling two 30 A dies is experimentally evaluated. Three bond wire configurations are investigated using a non-repetitive surge current test at 25 °C and 110 °C. The results reveal that the stitch configuration, which employs 3×20 mil bonding wires, significantly outperforms the alternative 4×15 mil and 4×12 mil counterparts in terms of maximum surge current robustness. An extensive analysis is also conducted to identify key differences in the failure mechanisms among the three configurations during surge current stress.

ABSTRACT. Because power switching devices are frequently operated under a negative gate bias to inhibit false turn-on, good stability of the threshold voltage under a negative bias is indispensable. To understand the negative bias instability in GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) with AlSiO gate oxides, we investigated the hole trapping process under a negative bias. During the sweep toward negative bias, high-density interface states capture holes, resulting in pinning of the Fermi level. This effect was observed as the capacitance exhibiting a plateau at a level much lower than the gate-oxide capacitance. A further negative sweep led to hole injection into near-interface traps (NITs) in the gate oxides. In the subsequent forward sweep, holes trapped by interface states caused a negative shift of the threshold voltage, which gradually recovered via recombination with inversion electrons. However, holes trapped by NITs hardly recombined with electrons, which caused a long-term negative threshold-voltage shift. The keys to preventing hole trapping are the suppression of interface states and the design of an interfacial layer that inhibits hole injection into NITs. Doping of Mg to passivate hole traps and inserting an AlN interfacial layer were demonstrated.