ABSTRACT. Wire bonding technology is widely used in power electronics to make electrical interconnections. IGBT power modules, in particular, use thick aluminum wires to drive a power current from a source to a load obeying complex mission profiles. During operation, the aluminum wires are subjected to high thermomechanical stresses due to temperature cycles, which leads to failure under long term exposure conditions. In the presentation, a large experience of lifetime testing, characterization and modelling of this failure is highlighted

ABSTRACT. This paper reports on the integration of power cycling sensors into a PIN diode chip and the experimental verification of the correlation between the change in sensor current and the increase in package thermal resistance through power cycling tests. The sensor device consists of a Schottky barrier MISFET and can be integrated into a power device. Power cycling degradation is detected by a decrease in the drain current of the SB-MISFET, as repetitive mechanical stress increases the interface state density in the MIS gate. In a previous study, the sensor devices demonstrated the basic operation of a decrease in drain current due to repetitive mechanical bending stress. The thermomechanical stress induced by power cycling tests is mainly a biaxial stress, whereas bending stress has a different geometry, with uniaxial and shear stress components. Therefore, a power cycling test is needed to generate thermomechanical stress and evaluate the actual sensitivity. In this study, the increase in package thermal resistance and the decrease in sensor current with an increasing number of stress cycles in the power cycling test were observed, demonstrating the operation of the sensor due to repetitive thermal stress.

ABSTRACT. This study introduces a novel method for directly measuring the dynamic channel temperature in power transistors. By employing a trans-impedance amplifier (TIA), the setup effectively captures fast self-heating effects with high accuracy. Experimental results disclose the significant impact of duty cycle, operating points, and ambient temperature on the thermal behavior of transistors. Simulations confirm the rapid temperature rise. This technique outperforms current methods by delivering real-time, precise temperature data directly at the device’s hot-spot. This advancement can significantly enhance the accuracy of lifetime predictions and device modeling. Moreover, for the first time, the temperature inside the device can be resolved on a nanosecond timescale, offering invaluable contributions to reliability engineering

ABSTRACT. This paper investigates the avalanche robustness of high-voltage silicon diodes under unclamped inductive switching (UIS) conditions. The devices were experimentally tested across a wide range of load inductance values. A significant drop in robustness, both in terms of time to failure and supported avalanche current, was observed at low inductance values, deviating from previously reported trends. This anomaly suggests the presence of a previously unreported failure mechanism, distinct from classical energy-driven failure. Two different failure mechanisms are proposed to explain the observed behavior. Furthermore, 2D TCAD simulations were conducted to validate one of these mechanisms, revealing the role of current filamentation and electrothermal effects in the failure process.

ABSTRACT. Power-cycling degradation monitoring is effective for predicting failure of an IGBT module, where its junction temperature needs to be measured. VCE(sat) is an indicator of the junction temperature but depends on the current flowing in to the device under test as well because it is the sum of the buit-in voltage and a voltage drop in the drift layer and bonding wire resistances. Separation of the effects of the junction temperature and the current is necessary for acuate monitoring. This paper presents junction temperature measurement of an IGBT module with VCE(sat) sensing circuit,where the built-in voltage is separately measured to improve the accuracy of the junction temerature estimation.

ABSTRACT. SRAM-based FPGAs are increasingly used in aerospace due to their reconfigurability and performance. However, their Configuration RAM (CRAM) is highly susceptible to radiation-induced Single Event Upsets (SEUs). We developed a tool to predict the soft error reliability of these devices, considering design-level redundancy techniques. To validate the tool, a proton radiation test was conducted at the PSI Proton facility. A TMR-hardened ALU of a RISC-V processor was implemented on a Zynq-7020 FPGA as the test design.

ABSTRACT. Traditional single-event effect testing with heavy ion beams and lasers faces limitations for modern 3D semiconductor devices, as ions cannot access deeply buried layers, and lasers fail to penetrate metallization layers. This study proposes pulsed hard X-rays as an alternative method. We validate the approach using a 3D NAND Flash memory tested at the European Synchrotron Radiation Facility (ESRF). Results demonstrate X-rays' capability to effectively induce single-bit, multi-bit upsets and single-event functional interrupts across the entire device stack. Pulsed X-ray testing is a valuable complementary technique for reliability assessment and failure analysis in complex semiconductor architectures

ABSTRACT. This paper explores the impact of caches on the reliability of critical systems under radiation, employing C programming language to implement a widely used benchmark in the field of fault tolerance. This benchmark was subject to different variations to further highlight cache behavior and execution time. Afterward, these differences were stated performing a dynamic characterization prior to the experiments under radiation. The experimental stage yielded results indicating that cache optimization has a beneficial impact on fault tolerance in every version. The versions with more cache locality also presents better Mean Work To Failure (MWTF)

ABSTRACT. In this work, the effect of electrical stress and high X-ray Total Ionizing Dose (TID) exposures is studied for BiCMOS 55 nm SiGe:C HBTs technology. The forward gummel plot and the relative base current of pre-stressed and post-stressed devices were used to quantify the impacts of the degradation. HBTs were exposed to a maximum X-ray TID of 520 krad(SiO2) and in terms of electrical stress to a high current injection (i.e. VBE = 1.1 V in the direct gummel-plot configuration). For both stress techniques, the effect of the cumulative X-ray dose and electrical stress duration on the degradation of the base current, IB, is investigated. A linear degradation is observed when increasing TID. In the case of electrical stress, degradation is generally more pronounced, but increasing or decreasing erratically with the duration of the stress. To investigate a possible detrapping mechanism, a two-step annealing process was conducted at temperatures of 100 °C and 130 °C. Annealing results showed a significant difference between the two degradation processes. Moreover, TCAD simulations of X-ray irradiation effects were used to investigate and compare the results with the experimental data regarding the impact of created trap densities and emitter-width on the degradation of DC characteristics

ABSTRACT. Wide-bandgap devices offer higher efficiency, faster switching, and better thermal performance than traditional silicon transistors. Their ability to operate at high voltages with lower losses enables compact and efficient power electronics. Since these devices are expected to find application in high/speed and high/performance power converters, their reliability is subject of intense investigation. Particular focus is on the stability of the main parameters, such as ON-resistance (Rds, on), during switching operation. To assess Rds, on stability, this paper discusses the development of a dynamic high-temperature operating life (DHTOL) setup, designed to mimic actual application conditions. The setup utilizes a boost converter to achieve higher stress voltage with a lower input power supply. It consists of two detachable boards: a daughterboard, which contains only the device under test (DUT), and a main board, which contains all the essential components of the converter and clamping circuit. The detachable design facilitates further degradation analysis of the DUTs without disordering the DUT. A thermocouple is mounted close to the thermal pad of the DUT to monitor temperature, which can be used for thermally activated degradation analysis; this is particularly useful, since we did not employ a external heat sink, but just an active cooling (fan). Furthermore, the setup is used to analyze the stability of two different 650 V commercial technologies with similar parameters: trench-based Silicon Carbide (SiC) and p-Gallium Nitride (p-GaN) High Electron Mobility Transistors (HEMTs). The results indicate that the Rds, on of the trench-based SiC device remains stable, whereas the p-GaN HEMT device exhibits a substantial increase in Rds, on after approximately 8 hours at ~50°C.

ABSTRACT. Three phase inverters are widely used in grid connected and drive systems due to their high power density and high switching efficiency. However, during long-term operation, the degradation of microelectronic components under electrical and thermal stress poses a significant threat to system reliability. Traditional methods struggle to couple the dynamic characteristics of control algorithms with circuit transient responses and fail to effectively reveal the impact of component degradation on system performance. Therefore, this paper proposes an integrated digital-analog co-simulation approach to establish a multi-level coupled evaluation framework covering the device layer, circuit layer, and control layer. First, a digital-analog co-simulation platform is constructed, integrating the inverter main circuit and control modules while developing fine-grained circuit-level models for MOSFETs, current sensors, and other key components. Second, a Physics of Failure model is developed for sensitive components, enabling a collaborative analysis of the influence of degradation on dynamic and static parameters. Finally, an adaptive compensation control strategy based on online parameter identification is proposed, achieving a coupled analysis of microelectronic component degradation and digital-analog interactions. This approach provides a theoretical foundation and optimization methods for the multiphysics collaborative design of high-reliability inverters.

ABSTRACT. A new online monitoring method to detect thermal resistance is proposed, utilizing high-speed sampling of the gate plateau voltage for power cycling degradation detection. For high-speed and highly accurate sampling of the gate plateau voltage, a new sampling technique called turbo sampling was developed. This method consists of 15 repetitive gate voltage measurements with a sampling timing shift of 12.5 ns. A method called the LHL method, which utilizes the temperature dependence of the plateau voltage, was also developed to observe the rise in junction temperature by measuring the plateau voltage before and after heating. Through power cycling tests, samples with an increase in thermal resistance of 15% to 29% were fabricated. By combining turbo sampling with the LHL method, the junction temperature rise was measured. As a result, the change rate of the plateau voltage increased by 11% to 25% before and after the power cycling tests, corresponding to the observed increase in thermal resistance.

ABSTRACT. High-power operation represents the most common and challenging condition for photovoltaic (PV) inverters, where the distribution of power losses and thermal management directly influence system efficiency and long-term reliability. This study examines the thermal characteristics and loss evolution under high-power conditions and proposes an online loss evaluation method based on a linear temperature-rise coupling model. By establishing a linear relationship between power loss and temperature rise, the proposed method dynamically allocates losses among significant heat sources. A duct health factor is also introduced to adaptively c ompensate for variations in the cooling system's performance. Experimental validation involves analysing data from a 1.1 MW centralised PV inverter under various cooling duct conditions, with finite element simulations further evaluating the accuracy of loss estimation. The results demonstrate that the proposed approach accurately estimates loss distribution in high-power operations and maintains a temperature rise estimation error of within 5°C, even under degraded cooling conditions. Compared with conventional modelling methods, the proposed approach offers a reduced computational cost, suitability for real-time monitoring, and adaptive capabilities for cooling system variations, thus providing a reliable basis for enhancing PV inverters' operational stability and energy efficiency.

ABSTRACT. As SiC MOSFETs advance, fast and reliable short-circuit (SC) protection is essential. The Desaturation (DESAT) method, though widely used, has speed limitations therefore SC detections at high currents. This study proposes a Gate Signal Monitoring approach and compares it to the standard DESAT method in terms of detection speed and robustness for Hard Switch Faults (HSF) and Faults Under Load (FUL). For HSF, the proposed method detects faults up to 6 times faster with 2 to 4.4 times lower currents at SC detection. For FUL, it achieves up to 7 times lower detection current, improving fault mitigation. These findings position Gate Signal Monitoring as a superior alternative for next-generation SiC MOSFET protection solutions.