ITC2020: INTERNATIONAL TEST CONFERENCE 2020
PROGRAM

Days: Tuesday, November 3rd Wednesday, November 4th Thursday, November 5th

Tuesday, November 3rd

View this program: with abstractssession overviewtalk overview

10:00-11:00 Session Plenary1: Opening Session

ITC 2020 Opening (30 minutes)

1. General Chair

2. Program Chair

3. TTTC President

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Keynote (30 minutes)

Title: Applying Digital Transformation Technologies to Semiconductor Product Development

At first glance, you might think that digital transformation applies only to IT organizations, e-commerce systems, or your personal strategy to store family photos in the cloud.  However, many of the same technologies that improve our consumer experiences are are fundamentally shaping how semiconductor organizations design, test, and manufacture semiconductor products.  In this presentation, we’ll share some of the latest trends and technologies that best-in-class semiconductor companies are using to accelerate and improve product designs.  More specifically, we’ll share practical examples of how companies are utilizing technologies ranging from the remote automation to the cloud to artificial intelligence to transform modern engineering labs and enterprises.

Speaker: Ritu Favre, Senior Vice President and General Manager of Semiconductor Business

As senior vice president and general manager of the semiconductor business, Ritu Favre is responsible for driving business growth and defining the products, services, and capabilities required to meet the unique needs of NI customers in the market.

Favre is a seasoned high-tech industry leader with experience across general management and executive leadership roles in the RF and semiconductor industries. Most recently, she served as the chief executive officer of NEXT Biometrics and was on the Cohu Board of Directors. Prior to her role at NEXT, she helped build profitable businesses while holding senior management positions with market leaders such as Motorola, Freescale Semiconductor, and Synaptics.

Favre is a member of the Global Semiconductor Association’s Women’s Leadership Council, which is aimed at inspiring and sponsoring the next generation of female leaders in the semiconductor industry. She received both her bachelor’s and master’s degrees in electrical engineering from Arizona State University.

11:00-11:30Social/Exhibit Hall
11:30-12:30 Session 1A: Learning for Failure Analysis and Prediction
11:30
LAIDAR: Learning for Accuracy and Ideal Diagnostic Resolution (abstract)
11:50
Unsupervised Root-Cause Analysis for Integrated Systems (abstract)
12:10
Unleashing the Power of Anomaly Data for Soft Failure Predictive Analytics (abstract)
11:30-12:30 Session 1B: Novel Test Pattern Generation
11:30
qATG: Automatic Test Generation for Quantum Circuits (abstract)
11:50
Functional Test Sequences for inducing Voltage Droops in a Multi-Threaded Processor (abstract)
12:10
SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts (abstract)
11:30-12:30 Session 1C: Test and Mitigation with Analog and RF
11:30
Fast EVM Tuning of MIMO Wireless Systems Using Collaborative Parallel Testing and Implicit Reward Driven Learning (abstract)
11:50
Robust DfT Techniques for Built-in Fault Detection in Operational Amplifiers with High Coverage (abstract)
12:10
Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction (abstract)
11:30-12:30 Session 1D: Interconnect Testing & Test Access (IP Papers)
11:30
IJTAG Through a Two-Pin Chip Interface (abstract)
11:45
High Speed Serial Links Risk Assessment in Industrial Post-Silicon Validation Exploiting Machine Learning Techniques (abstract)
12:00
Cost-Effective Test Method that can screen out Unexpected Failure in High Speed Serial Interface IPs (abstract)
12:15
Scalable Test AccessIEEE 1687-Based Testing Methodology for AI SoC (abstract)
12:30-13:00Social/Exhibit Hall
13:00-14:00 Session 2A: Enhancing Yield and Diagnosis
Chair:
13:00
Improved Chain Diagnosis Methodology with clock and control signal defect identification (abstract)
13:20
Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization (abstract)
13:40
High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips (abstract)
13:00-14:00 Session 2B: Special Session on Chiplet
13:00
Die-to-Die Testing and ECC Error Mitigation in Automotive and Industrial Safety Applications (abstract)
13:00-14:00 Session 2C: Sensing and Modeling for Analog & RF
13:00
Rapid PLL Monitoring By a novel min-MAX Time-to-Digital Converter (abstract)
13:20
Modeling Accuracy of Wideband Power Amplifiers with Memory Effects via Measurements (abstract)
13:40
Design Optimization for N-port RF Network Analyzers under Noise and Gain Imperfections (abstract)
13:00-14:00 Session 2D: Microprocessor & Memory Test (IP Papers)
Chair:
13:00
Test Challenges of Intel IA Cores (abstract)
13:15
Novel Eye Diagram Estimation Technique to Assess Signal Integrity in High-Speed Memory Test (abstract)
13:30
Memory repair logic sharing techniques and their impact on yield (abstract)
13:45
MBIST Supported Reliable eMRAM Sensing (abstract)
14:00-14:30Social/Exhibit Hall
14:30-15:30Diamond Support Presentation
16:30-17:30 Session Panel2: Panel: The Effect of 2020 on the Test Industry

This panel intends to broadly discuss the impact of Covid-19 on the industry this year. Panelists provide their perspective to the current state of the industry, and what might look like going into 2021.

Wednesday, November 4th

View this program: with abstractssession overviewtalk overview

10:00-11:00 Session Plenary2: Plenary - Keynote and Visionary Talk

Keynote (30 minutes)

Title: Reverse Engineering Visual Intelligence

The brain and cognitive sciences are hard at work on a great scientific quest — to reverseengineer the human mind and its intelligent behavior. Yet these field are still in their infancy.Not surprisingly, forward engineering approaches that aim to emulate human intelligence (HI)in artificial systems (AI) are also still in their infancy. Yet the intelligence and cognitive flexibilityapparent in human behavior are an existence proof that machines can be constructed toemulate and work alongside the human mind.I believe that these challenges of reverse engineering human intelligence will be solved bytightly combining the efforts of brain and cognitive scientists (hypothesis generation and dataacquisition), and forward engineering aiming to emulate intelligent behavior (hypothesisinstantiation and data prediction). As this approach discovers the correct neural networkmodels, those models will not only encapsulate our understanding of complex brain systems,they will be the basis of next-generation computing and novel brain interfaces for therapeuticand augmentation goals (e.g, brain disorders).In this session, I will focus on one aspect of human intelligence — visual object categorizationand detection — and I will tell the story of how work in brain science, cognitive science andcomputer science converged to create deep neural networks that can support suchtasks. These networks not only reach human performance for many images, but their internalworkings are modeled after— and largely explain and predict — the internal workings of theprimate visual system. Yet, the primate visual system (HI) still outperforms current generationartificial deep neural networks (AI), and I will show some new clues that the brain and cognitivesciences can offer.These recent successes and related work suggest that the brain and cognitive sciencescommunity is poised to embrace a powerful new research paradigm. More broadly, our speciesis the beginning of its most important science quest — the quest to understand humanintelligence — and I hope to motivate others to engage that frontier alongside us.

About the speaker

James DiCarlo is a Professor of Neuroscience, and Head of the Department of Brain andCognitive Sciences at the Massachusetts Institute of Technology. His research goal is toreverse engineer the brain mechanisms that underlie human visual intelligence. He and hiscollaborators have revealed how population image transformations carried out by a deep stackof neocortical processing stages -- called the primate ventral visual stream -- are effortlesslyable to extract object identity from visual images. His team uses a combination of large-scaleneurophysiology, brain imaging, direct neural perturbation methods, and machine learningmethods to build and test artificial neural network models of the ventral visual stream and itssupport of cognition and behavior. Such an engineering-based understanding is likely to leadto new artificial vision and artificial intelligence approaches, new brain-machine interfaces torestore or augment lost senses, and a new foundation to ameliorate disorders of the mind.

Link to James J. DiCarlo M.D., Ph.D., MIT

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Visionary Talk - TBD (30 minutes)

 

11:00-11:30Social/Exhibit Hall
11:30-12:30 Session 3A: 2020 ITC Paper Highlights

Top three papers selected from the review process as Distingushed papers.

11:30
Learning A Wafer Feature With One Training Sample (abstract)
11:50
Characterization, Modeling, and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs (abstract)
12:10
Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices (abstract)
11:30-12:30 Session 3B: Machine Learning Hardwares and Applications (Short Papers)
11:30
Concurrent detection of failures in GPU control logic for reliable parallel computing (abstract)
11:45
Functional Criticality Classification of Structural Faults in AI Accelerators (abstract)
12:00
Automated Assertion Generation from Natural Language Specifications (abstract)
12:15
Machine Intelligence for Efficient Test Pattern Generation (abstract)
11:30-12:30 Session 3C: Ensuring Secure and Trustworthy Circuitry
11:30
SPARTA: A Laser Probing Approach for Trojan Detection (abstract)
11:50
A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic Gates (abstract)
12:10
Schmitt Trigger-Based Key Provisioning for Locking Analog/RF~Integrated~Circuits (abstract)
11:30-12:30 Session 3D: TTTC-PhD Competition (Asia/Europe)
11:30
Digital Design Techniques for Dependable High Performance Computing (abstract)
12:00
Assuring Security and Reliability of Emerging Non-Volatile Memories (abstract)
12:30-13:00Social/Exhibit Hall
13:00-14:00 Session 4A: Machine Learning for Reliable Operation
13:00
FAT: Training Neural Networks for Reliable Inference Under Hardware Faults (abstract)
13:20
Online Fault Detection in ReRAM-Based Computing Systems by Monitoring Dynamic Power Consumption (abstract)
13:40
Advanced Outlier Detection Using Unsupervised Learning for Screening Potential Customer Returns (abstract)
13:00-14:00 Session 4B: IEEE 1687 and Reconfigurable Scan
13:00
Multi-Level Access Protection for Future IEEE P1687.1 IJTAG Networks (abstract)
13:20
Modeling Novel Non-JTAG IEEE 1687-Like Architectures (abstract)
13:40
Security Preserving Integration and Resynthesis of Reconfigurable Scan Networks (abstract)
13:00-14:00 Session 4C: Security, Safety, & Emerging Devices (Short Papers)
Chair:
13:00
Avionics Simulation Environment (abstract)
13:15
Data-driven fault model development for superconducting logic (abstract)
13:30
BISTLock: Efficient IP Piracy Protection using BIST (abstract)
13:45
Cross PUF Attacks on Arbiter-PUFs through their Power Side-Channel (abstract)
13:00-14:00 Session 4D: TTTC-PhD Competition (Latin America/US)
13:00
Susceptibility Analysis of Logic Gates to Improve the Accuracy of Circuit Reliability Estimation (abstract)
13:30
Hardware IP Protection Using Logic Encryption and Watermarking (abstract)
14:00-14:30Social/Exhibit Hall
14:30-15:30Exhibit Presentations
17:00-17:30 Session Visionary
17:00
Introduction to Quantum Computation Reliability (abstract)
Thursday, November 5th

View this program: with abstractssession overviewtalk overview

10:00-11:00 Session Plenary3: Plenary - Keynote and Visionary Talk

Keynote (30 minutes)

Title: 50 years of ITC! Now what?

Last year we collectively celebrated the 50th International Test Conference. After 50 years it’s tempting to say that everything’s been done, or conversely to look ahead to a glorious but only vaguely specified future. As test professionals, we know that better analysis of existing data can help us to identify and respond to future challenges. Today’s challenges include a slowing of Moore’s Law coupled with an ever-increasing appetite for data and analytics. Security and privacy concerns abound. Machine learning gives fast answers but few reasons. New technologies are emerging and bringing new test challenges with them. This talk takes stock of where we are and how we got here, and then focuses on where we might go next and why.

About The Speaker:

Rob Aitken is an ARM Fellow and technology lead for ARM Research. He is responsible for technology direction of ARM research, including identifying disruptive technologies, monitoring the global technology landscape, and coordinating research efforts within and outside of ARM. He has worked on test and related topics for 35 years, and is a former general chair and program chair of ITC. He has published over 100 technical papers, on a wide range of topics. He holds over 40 US patents.  Dr. Aitken joined ARM as part of its acquisition of Artisan Components in 2004. Prior to Artisan, he worked at Agilent and HP.  He is an IEEE Fellow and holds a Ph.D. from McGill University in Canada.

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Visionary Talk: (30 minutes)

Ttitle: A landscape for dependable autonomous machines

By Riccardo Mariani, VP Industry Safety, Nvidia

11:00-11:30Social/Exhibit Hall
11:30-12:30 Session 5A: Best Practices in Safety (Automotive Track)
11:30
Stress, Test, and Simulation of Analog IO Pads on Automotive ICs (abstract)
11:50
Quick Analyses for Improving Reliability and Functional Safety of Mixed-Signal ICs (abstract)
12:10
On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors (abstract)
11:30-12:30 Session 5B: Diagnosis & Repair
11:30
A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns (abstract)
11:50
Logic Fault Diagnosis of Hidden Delay Defects (abstract)
12:10
Fail Memory Configuration Set for RA Estimation (abstract)
11:30-12:30 Session 5C: Fault Modeling and DFT (Short papers)
11:30
New Perspectives on Core In-field Path Delay Test (abstract)
11:45
A Unified Method of Designing Signature Analyzers for Digital and Mixed-Signal Circuits Testing (abstract)
12:00
Selecting Close-to-Functional Path Delay Faults for Test Generation (abstract)
12:15
Flip-flops fanout splitting in scan designs (abstract)
11:30-12:30 Session 5D: ITC-Asia 2020 Top 3 Papers
11:30
Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations (abstract)
11:50
A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices (abstract)
12:10
Knowledge Transferring for Diagnosis Outcome Preview with Limited Data (abstract)
12:30-13:00Social/Exhibit Hall
13:00-14:00 Session 6A: Quality Test & Analysis (Automotive Track)
13:00
Test and Diagnosis Solution for Functional Safety (abstract)
13:20
Wafer Level Stress: Enabling Zero Defect Quality for Automotive Microcontrollers without Package Burn-In (abstract)
13:40
Concurrent Error Detection in Embedded Digital Control of Nonlinear Autonomous Systems Using Adaptive State Space Checks (abstract)
13:00-14:00 Session 6C: ITC-India Best Paper Presentations

ITC-India 2020 Best Paper Presentation Session:

Best Paper:

6C.1: Analyzing Fault Tolerance Behaviour in Memristor-based Crossbar for Neuromorphic Applications

Presented by, Dev Narayan Yadav received the M.Tech degree in Computer Science and Engineering from National Institute of Technology Meghalaya, India, in 2018. He is currently pursuing his Ph.D. in the Department of Computer Science and Engineering at the Indian Institute of Technology Kharagpur, India. His research interests include memristor and its application in logic design and machine learning.

Honorable Mention:

6C.2: Wavelet Transform based fault diagnosis in analog circuits with SVM classifier

Presented by, Supriyo Srimani received a Bachelor of Electronics and Communication Engineering degree from West Bengal University of Technology, India, in 2013, Master degree in VLSI Design from Calcutta University, India, in 2015. He currently is pursuing his Ph.D. from Indian Institute of Engineering Science and Technology, Shibpur. His current areas of research interest are Analog and Mixed-Signal Circuit Design and Testing.

6C.3: Validating and Characterizing a 2.5D High Bandwidth Memory Sub-System

Presented by, Sreeja Menon is Senior Principal Engineer - Architecture at Rambus Chip Technologies, India Design Center. She has 15+ years of experience working on architecture and design of digital controllers and PHYs. In her current role, she works on architecture of DDR, HBM and GDDR memory PHY families and the test platforms for the validation and characterization of the same. She has received her Bachelor's degree in Applied Electronics and Instrumentation Engineering from University of Kerala, India.

13:00-14:00 Session 6D: Learning & Data Analysis (IP papers)
13:00
Automated Socket Anomaly Detection through Deep Learning (abstract)
13:15
TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning (abstract)
13:30
Machine Learning based Performance Prediction of Microcontrollers using Speed Monitors (abstract)
13:45
Using Volume Cell-aware Diagnosis Results to Improve Physical Failure Analysis Efficiency (abstract)
14:00-14:30Social/Exhibit Hall
14:30-15:30Exhibit Presentations