TALK KEYWORD INDEX
This page contains an index consisting of author-provided keywords.
' | |
'Massive MIMO' | |
'Parallel testing' | |
'Post manufacture tuning' | |
'Reinforcement learning' | |
A | |
AC coupled configuration | |
activation coverage | |
activity coverage | |
AI | |
AI accelerator | |
AI Chip | |
analog | |
analog defect simulation | |
analog locking | |
analysis time | |
Analytics | |
Anomaly detection | |
Assertion generation | |
Asynchronous design | |
Asynchronous digital logic | |
At-speed Test | |
At-speed testing | |
ATE | |
ATPG | |
Authentication | |
Automated Test Pattern Generation (ATPG) | |
Automated testing | |
Automated verification | |
automatic test equipment | |
Automatic test generation | |
automatic test pattern generation | |
automation | |
automotive | |
Automotive subsystem | |
Avionics test | |
B | |
benchmark | |
BIST | |
boosted trees | |
built-in RA (BIRA) | |
built-in self-test | |
Bundled-data circuit | |
C | |
cell-aware diagnosis | |
Cell-Aware Test | |
changepoint detection | |
classification | |
Commonsense reasoning | |
Cost-Effective Test Method | |
countermeasures | |
criticality evaluation | |
Cross PUF Attacks | |
Customer Returns | |
D | |
decision tree | |
deep learning | |
defect inspection | |
Defect Level | |
Defects | |
defense techniques | |
Delay testing | |
Design for Test | |
Design Optimization | |
Design Rule Check (DRC) | |
Design-for-Test (DFT) | |
Design-for-Yield (DFY) | |
Design-Technology Co-optimization | |
deterministic test | |
Device Aging | |
Device-aware test | |
DFM | |
Diagnosis | |
Diagnosis accuracy | |
Diagnosis enhancement | |
Diagnosis outcome preview | |
Diagnosis resolution | |
die-to-die testing | |
DPAT | |
DRAM | |
E | |
Early-Life Failures | |
ECC | |
embedded TAP | |
Emerging Technology | |
Error Detecting Codes | |
error detection | |
EUCLID space mission | |
Extended Kalman filters | |
eye diagram | |
F | |
Failure Prediction | |
Faster-than-at-Speed Testing | |
fault detection | |
fault distribution | |
fault injection | |
Fault model | |
fault modeling | |
fault models | |
Fault tolerance | |
fault-injection framework | |
FIT rate | |
Flip-flops fanout splitting | |
FPGA | |
frequent-pattern mining | |
functional broadside tests | |
functional criticality | |
Functional Safety | |
functional test | |
G | |
GAN | |
gate-level fault | |
GDBC | |
GPU | |
Graph Partitioning | |
H | |
Hardware Security | |
Hardware Security and Trust | |
Hardware Trojan Detection | |
Hidden Delay Defects | |
Hierarchical Test | |
High Speed Serial Interface | |
high voltage stress test | |
high-speed | |
I | |
IC testing | |
IEEE 1687 | |
IEEE P1687.1 | |
IFME | |
IJTAG | |
in-field testing | |
inferencing | |
Integer Linear Programming | |
Integrated Passive Device (IPD) | |
Interference | |
interpolation | |
Intra-cell faults | |
IO | |
IP Piracy | |
J | |
Jitter Measurement | |
JTAG | |
K | |
key provisioning | |
Keyword | |
Keyword_2 | |
Keyword_3 | |
Known-Good-Die Testing | |
L | |
Latch-based design | |
latent defects | |
LDO Test | |
Limited Data | |
Logic Diagnosis | |
Logic gates | |
Logic Locking | |
Logic Timing Simulation | |
logical qubit | |
loopback test | |
Low Pin Count Test | |
low pin-count | |
M | |
machine learning | |
major-minor voltage regulator | |
manufacturing defects | |
memory model | |
memory polynomial (MP) model | |
Memory repair | |
memory test | |
Micropipeline | |
min-max TDC | |
Mixed-Signal | |
ML | |
MRAM | |
Multi-pattern test generation | |
Multi-State Model | |
multi-thread | |
Multiple Abstraction Levels | |
Multiple defects | |
Multiple Identical Cores | |
N | |
Natural language processing | |
Neural Network | |
neural networks | |
nonlinear distortion | |
Null conventional logic (NCL) gates | |
NVM | |
O | |
On-line test | |
Online Monitor | |
Online monitoring | |
Open and short defects | |
Operational Amplifiers | |
Optical Probing | |
outlier detection | |
overproduction | |
P | |
P1687.1 | |
P1687.2 | |
path delay faults | |
path selection | |
Path Tracing | |
Path-delay test | |
PDN | |
Performance Hazard | |
Performance Screening | |
PFA | |
Physical Unclonable Function (PUF) | |
Physically Unclonable Function | |
pin-level fault | |
PMIC | |
post-silicon testing | |
post-silicon validation | |
Power amplifier (PA) | |
power delivery network | |
Power Side-Channel | |
power-on self-test | |
predistorter (PD) | |
proactive noise mitigation | |
Process Variation | |
Processor | |
Q | |
Quadcopter | |
Quality | |
Quantized Neural Networks | |
Quantum Circuit | |
quantum computing | |
quantum error correction | |
quantum fault models | |
R | |
Radiation Effects | |
Radiation hardening | |
Random forest | |
RCAD | |
read operation | |
Reconfigurable Scan Networks | |
reducing test application time | |
redundancy analysis (RA) | |
redundancy structure | |
reference trim | |
Reflection Coefficient | |
Register replication | |
reliability | |
Reliability Analysis | |
repair rate | |
repair time | |
ReRAM | |
Residue Generator | |
Resilient autonomous systems | |
Response Compaction | |
RF Testing | |
risk assessment | |
root-cause analysis | |
RSFQ logic | |
S | |
S11 Measurement | |
Safe Failures | |
Safety | |
SAT-ATPG | |
Scan Chain Defects | |
scan compression design | |
Scan Distribution Architecture | |
Scan Fabric | |
Scan Testing | |
scan-based testing | |
Secure DFT | |
Security | |
self-labeling | |
Semi-supervised learning | |
severity | |
short-term current prediction | |
signal integrity | |
Signature Analyzer | |
silicon area | |
Silicon Health Prognosis | |
Simulation | |
Single Event Transient | |
SoC/SiP/NoC Test | |
soft error | |
Soft errors | |
Soft Failure | |
Software test library | |
Software-based self-test | |
Speed Monitors | |
statistical correlation | |
Statistical Learning | |
Steer-by-wire | |
stress | |
structural fault | |
STT-MRAMs | |
stuck-at | |
supply-chain attacks | |
support vector machines | |
Synthesis-APR | |
system margin validation | |
T | |
test | |
test application time | |
Test chip | |
Test compression | |
Test data volume estimation | |
Test design | |
Test Generation | |
Test pattern count estimation | |
test points | |
test sequences | |
Test Time Reduction | |
Threshold M of N (THMN) gates | |
Time-to-Digital Converter | |
Transfer learning | |
Two-phase clocking | |
two-tier flow | |
U | |
under-kill | |
unexpected failure | |
unknown states | |
unsupervised learning | |
Untrusted Foundry | |
V | |
Vmin | |
voltage droop | |
W | |
wafer defect map | |
wafer level burn-in | |
Wafer plot | |
X | |
X-masking | |
Y | |
yield | |
yield learning | |
Z | |
zero defect |