ITC2020: INTERNATIONAL TEST CONFERENCE 2020

This page contains an index consisting of author-provided keywords.

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'Massive MIMO'	Fast EVM Tuning of MIMO Wireless Systems Using Collaborative Parallel Testing and Implicit Reward Driven Learning
'Parallel testing'	Fast EVM Tuning of MIMO Wireless Systems Using Collaborative Parallel Testing and Implicit Reward Driven Learning
'Post manufacture tuning'	Fast EVM Tuning of MIMO Wireless Systems Using Collaborative Parallel Testing and Implicit Reward Driven Learning
'Reinforcement learning'	Fast EVM Tuning of MIMO Wireless Systems Using Collaborative Parallel Testing and Implicit Reward Driven Learning
A
AC coupled configuration	Cost-Effective Test Method that can screen out Unexpected Failure in High Speed Serial Interface IPs
activation coverage	Quick Analyses for Improving Reliability and Functional Safety of Mixed-Signal ICs
activity coverage	Quick Analyses for Improving Reliability and Functional Safety of Mixed-Signal ICs
AI
AI accelerator	Functional Criticality Classification of Structural Faults in AI Accelerators
AI Chip	Scalable Test AccessIEEE 1687-Based Testing Methodology for AI SoC
analog	Stress, Test, and Simulation of Analog IO Pads on Automotive ICs
analog defect simulation	Quick Analyses for Improving Reliability and Functional Safety of Mixed-Signal ICs
analog locking	Schmitt Trigger-Based Key Provisioning for Locking Analog/RF~Integrated~Circuits
analysis time	Fail Memory Configuration Set for RA Estimation
Analytics
Anomaly detection	Unleashing the Power of Anomaly Data for Soft Failure Predictive Analytics Concurrent Error Detection in Embedded Digital Control of Nonlinear Autonomous Systems Using Adaptive State Space Checks Automated Socket Anomaly Detection through Deep Learning
Assertion generation	Automated Assertion Generation from Natural Language Specifications
Asynchronous design	At-speed DfT Architecture for Bundled-data Design
Asynchronous digital logic	A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic Gates
At-speed Test	Test Challenges of Intel IA Cores
At-speed testing	At-speed DfT Architecture for Bundled-data Design
ATE	Modeling Novel Non-JTAG IEEE 1687-Like Architectures Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices
ATPG	Machine Intelligence for Efficient Test Pattern Generation Improved Chain Diagnosis Methodology with clock and control signal defect identification
Authentication	Multi-Level Access Protection for Future IEEE P1687.1 IJTAG Networks
Automated Test Pattern Generation (ATPG)	Test Challenges of Intel IA Cores
Automated testing	Automated Assertion Generation from Natural Language Specifications
Automated verification	Automated Assertion Generation from Natural Language Specifications
automatic test equipment	Novel Eye Diagram Estimation Technique to Assess Signal Integrity in High-Speed Memory Test
Automatic test generation	Automated Assertion Generation from Natural Language Specifications
automatic test pattern generation	Flip-flops fanout splitting in scan designs
automation	Automated Socket Anomaly Detection through Deep Learning
automotive	On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors Stress, Test, and Simulation of Analog IO Pads on Automotive ICs A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns Wafer Level Stress: Enabling Zero Defect Quality for Automotive Microcontrollers without Package Burn-In Die-to-Die Testing and ECC Error Mitigation in Automotive and Industrial Safety Applications Test and Diagnosis Solution for Functional Safety
Automotive subsystem	Concurrent Error Detection in Embedded Digital Control of Nonlinear Autonomous Systems Using Adaptive State Space Checks
Avionics test	Avionics Simulation Environment
B
benchmark	Fail Memory Configuration Set for RA Estimation
BIST	MBIST Supported Reliable eMRAM Sensing
boosted trees	High Speed Serial Links Risk Assessment in Industrial Post-Silicon Validation Exploiting Machine Learning Techniques
built-in RA (BIRA)	Fail Memory Configuration Set for RA Estimation
built-in self-test	X-Tolerant Tunable Compactor for In-System Test
Bundled-data circuit	At-speed DfT Architecture for Bundled-data Design
C
cell-aware diagnosis	Using Volume Cell-aware Diagnosis Results to Improve Physical Failure Analysis Efficiency
Cell-Aware Test	SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts
changepoint detection	Online Fault Detection in ReRAM-Based Computing Systems by Monitoring Dynamic Power Consumption
classification	Functional Criticality Classification of Structural Faults in AI Accelerators TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning
Commonsense reasoning	Automated Assertion Generation from Natural Language Specifications
Cost-Effective Test Method	Cost-Effective Test Method that can screen out Unexpected Failure in High Speed Serial Interface IPs
countermeasures	Assuring Security and Reliability of Emerging Non-Volatile Memories
criticality evaluation	Functional Criticality Classification of Structural Faults in AI Accelerators
Cross PUF Attacks	Cross PUF Attacks on Arbiter-PUFs through their Power Side-Channel
Customer Returns	A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns
D
decision tree	Unsupervised Root-Cause Analysis for Integrated Systems
deep learning	Automated Socket Anomaly Detection through Deep Learning
defect inspection	Automated Socket Anomaly Detection through Deep Learning
Defect Level	A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices
Defects	Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization
defense techniques	Schmitt Trigger-Based Key Provisioning for Locking Analog/RF~Integrated~Circuits
Delay testing	SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts At-speed DfT Architecture for Bundled-data Design
Design for Test	Robust DfT Techniques for Built-in Fault Detection in Operational Amplifiers with High Coverage
Design Optimization	Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization
Design Rule Check (DRC)	Test Challenges of Intel IA Cores
Design-for-Test (DFT)	Test Challenges of Intel IA Cores
Design-for-Yield (DFY)	Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization
Design-Technology Co-optimization	Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization
deterministic test	Flip-flops fanout splitting in scan designs
Device Aging	Cross PUF Attacks on Arbiter-PUFs through their Power Side-Channel
Device-aware test	Characterization, Modeling, and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs
DFM	Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization
Diagnosis	High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization Improved Chain Diagnosis Methodology with clock and control signal defect identification A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning Knowledge Transferring for Diagnosis Outcome Preview with Limited Data
Diagnosis accuracy	LAIDAR: Learning for Accuracy and Ideal Diagnostic Resolution
Diagnosis enhancement	LAIDAR: Learning for Accuracy and Ideal Diagnostic Resolution
Diagnosis outcome preview	Knowledge Transferring for Diagnosis Outcome Preview with Limited Data
Diagnosis resolution	LAIDAR: Learning for Accuracy and Ideal Diagnostic Resolution
die-to-die testing	Die-to-Die Testing and ECC Error Mitigation in Automotive and Industrial Safety Applications
DPAT	A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices
DRAM	Die-to-Die Testing and ECC Error Mitigation in Automotive and Industrial Safety Applications
E
Early-Life Failures	Logic Fault Diagnosis of Hidden Delay Defects
ECC	Die-to-Die Testing and ECC Error Mitigation in Automotive and Industrial Safety Applications
embedded TAP	Scalable Test AccessIEEE 1687-Based Testing Methodology for AI SoC
Emerging Technology	qATG: Automatic Test Generation for Quantum Circuits
Error Detecting Codes	A Unified Method of Designing Signature Analyzers for Digital and Mixed-Signal Circuits Testing
error detection	Concurrent detection of failures in GPU control logic for reliable parallel computing
EUCLID space mission	Digital Design Techniques for Dependable High Performance Computing
Extended Kalman filters	Concurrent Error Detection in Embedded Digital Control of Nonlinear Autonomous Systems Using Adaptive State Space Checks
eye diagram	Novel Eye Diagram Estimation Technique to Assess Signal Integrity in High-Speed Memory Test
F
Failure Prediction	Unleashing the Power of Anomaly Data for Soft Failure Predictive Analytics
Faster-than-at-Speed Testing	Logic Fault Diagnosis of Hidden Delay Defects
fault detection	Online Fault Detection in ReRAM-Based Computing Systems by Monitoring Dynamic Power Consumption
fault distribution	Fail Memory Configuration Set for RA Estimation
fault injection	Concurrent detection of failures in GPU control logic for reliable parallel computing
Fault model	Robust DfT Techniques for Built-in Fault Detection in Operational Amplifiers with High Coverage
fault modeling	Data-driven fault model development for superconducting logic
fault models	Characterization, Modeling, and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs
Fault tolerance	Digital Design Techniques for Dependable High Performance Computing
fault-injection framework	Functional Criticality Classification of Structural Faults in AI Accelerators
FIT rate	Die-to-Die Testing and ECC Error Mitigation in Automotive and Industrial Safety Applications
Flip-flops fanout splitting	Flip-flops fanout splitting in scan designs
FPGA	FAT: Training Neural Networks for Reliable Inference Under Hardware Faults
frequent-pattern mining	Unsupervised Root-Cause Analysis for Integrated Systems
functional broadside tests	Selecting Close-to-Functional Path Delay Faults for Test Generation
functional criticality	Functional Criticality Classification of Structural Faults in AI Accelerators
Functional Safety	On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors Unleashing the Power of Anomaly Data for Soft Failure Predictive Analytics FAT: Training Neural Networks for Reliable Inference Under Hardware Faults Test and Diagnosis Solution for Functional Safety
functional test	Functional Test Sequences for inducing Voltage Droops in a Multi-Threaded Processor
G
GAN	Functional Criticality Classification of Structural Faults in AI Accelerators
gate-level fault	Functional Criticality Classification of Structural Faults in AI Accelerators
GDBC	A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices
GPU	Concurrent detection of failures in GPU control logic for reliable parallel computing
Graph Partitioning	Security Preserving Integration and Resynthesis of Reconfigurable Scan Networks
H
Hardware Security	Schmitt Trigger-Based Key Provisioning for Locking Analog/RF~Integrated~Circuits Security Preserving Integration and Resynthesis of Reconfigurable Scan Networks SPARTA: A Laser Probing Approach for Trojan Detection
Hardware Security and Trust	BISTLock: Efficient IP Piracy Protection using BIST
Hardware Trojan Detection	SPARTA: A Laser Probing Approach for Trojan Detection
Hidden Delay Defects	Logic Fault Diagnosis of Hidden Delay Defects
Hierarchical Test	Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs
High Speed Serial Interface	Cost-Effective Test Method that can screen out Unexpected Failure in High Speed Serial Interface IPs
high voltage stress test	Stress, Test, and Simulation of Analog IO Pads on Automotive ICs
high-speed	Novel Eye Diagram Estimation Technique to Assess Signal Integrity in High-Speed Memory Test
I
IC testing	A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices
IEEE 1687	Scalable Test AccessIEEE 1687-Based Testing Methodology for AI SoC IJTAG Through a Two-Pin Chip Interface
IEEE P1687.1	Modeling Novel Non-JTAG IEEE 1687-Like Architectures IJTAG Through a Two-Pin Chip Interface
IFME	Data-driven fault model development for superconducting logic
IJTAG	Modeling Novel Non-JTAG IEEE 1687-Like Architectures Multi-Level Access Protection for Future IEEE P1687.1 IJTAG Networks Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices Scalable Test AccessIEEE 1687-Based Testing Methodology for AI SoC IJTAG Through a Two-Pin Chip Interface
in-field testing	Test and Diagnosis Solution for Functional Safety
inferencing	Functional Criticality Classification of Structural Faults in AI Accelerators
Integer Linear Programming	Security Preserving Integration and Resynthesis of Reconfigurable Scan Networks
Integrated Passive Device (IPD)	A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices
Interference	Unleashing the Power of Anomaly Data for Soft Failure Predictive Analytics
interpolation	Modeling Accuracy of Wideband Power Amplifiers with Memory Effects via Measurements
Intra-cell faults	SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts
IO	Stress, Test, and Simulation of Analog IO Pads on Automotive ICs
IP Piracy	BISTLock: Efficient IP Piracy Protection using BIST
J
Jitter Measurement	Rapid PLL Monitoring By a novel min-MAX Time-to-Digital Converter
JTAG	Multi-Level Access Protection for Future IEEE P1687.1 IJTAG Networks
K
key provisioning	Schmitt Trigger-Based Key Provisioning for Locking Analog/RF~Integrated~Circuits
Keyword	Hardware IP Protection Using Logic Encryption and Watermarking
Keyword_2	Hardware IP Protection Using Logic Encryption and Watermarking
Keyword_3	Hardware IP Protection Using Logic Encryption and Watermarking
Known-Good-Die Testing	Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs
L
Latch-based design	Test Challenges of Intel IA Cores
latent defects	Quick Analyses for Improving Reliability and Functional Safety of Mixed-Signal ICs
LDO Test	Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices
Limited Data	Learning A Wafer Feature With One Training Sample
Logic Diagnosis	Logic Fault Diagnosis of Hidden Delay Defects
Logic gates	Susceptibility Analysis of Logic Gates to Improve the Accuracy of Circuit Reliability Estimation
Logic Locking	BISTLock: Efficient IP Piracy Protection using BIST
Logic Timing Simulation	Logic Fault Diagnosis of Hidden Delay Defects
logical qubit	Introduction to Quantum Computation Reliability
loopback test	Cost-Effective Test Method that can screen out Unexpected Failure in High Speed Serial Interface IPs
Low Pin Count Test	Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs
low pin-count	IJTAG Through a Two-Pin Chip Interface
M
machine learning	High Speed Serial Links Risk Assessment in Industrial Post-Silicon Validation Exploiting Machine Learning Techniques Machine Learning based Performance Prediction of Microcontrollers using Speed Monitors Machine Intelligence for Efficient Test Pattern Generation Functional Criticality Classification of Structural Faults in AI Accelerators LAIDAR: Learning for Accuracy and Ideal Diagnostic Resolution A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns Online Fault Detection in ReRAM-Based Computing Systems by Monitoring Dynamic Power Consumption Automated Socket Anomaly Detection through Deep Learning TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning Knowledge Transferring for Diagnosis Outcome Preview with Limited Data
major-minor voltage regulator	Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction
manufacturing defects	Characterization, Modeling, and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs
memory model	Fail Memory Configuration Set for RA Estimation
memory polynomial (MP) model	Modeling Accuracy of Wideband Power Amplifiers with Memory Effects via Measurements
Memory repair	Memory repair logic sharing techniques and their impact on yield
memory test	Test and Diagnosis Solution for Functional Safety
Micropipeline	At-speed DfT Architecture for Bundled-data Design
min-max TDC	Rapid PLL Monitoring By a novel min-MAX Time-to-Digital Converter
Mixed-Signal	Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices
ML	Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization
MRAM	MBIST Supported Reliable eMRAM Sensing
Multi-pattern test generation	SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts
Multi-State Model	Unleashing the Power of Anomaly Data for Soft Failure Predictive Analytics
multi-thread	Functional Test Sequences for inducing Voltage Droops in a Multi-Threaded Processor
Multiple Abstraction Levels	Susceptibility Analysis of Logic Gates to Improve the Accuracy of Circuit Reliability Estimation
Multiple defects	High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips
Multiple Identical Cores	Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs
N
Natural language processing	Automated Assertion Generation from Natural Language Specifications
Neural Network	Machine Intelligence for Efficient Test Pattern Generation
neural networks	High Speed Serial Links Risk Assessment in Industrial Post-Silicon Validation Exploiting Machine Learning Techniques FAT: Training Neural Networks for Reliable Inference Under Hardware Faults
nonlinear distortion	Modeling Accuracy of Wideband Power Amplifiers with Memory Effects via Measurements
Null conventional logic (NCL) gates	A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic Gates
NVM	Assuring Security and Reliability of Emerging Non-Volatile Memories
O
On-line test	New Perspectives on Core In-field Path Delay Test
Online Monitor	Rapid PLL Monitoring By a novel min-MAX Time-to-Digital Converter
Online monitoring	Robust DfT Techniques for Built-in Fault Detection in Operational Amplifiers with High Coverage
Open and short defects	SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts
Operational Amplifiers	Robust DfT Techniques for Built-in Fault Detection in Operational Amplifiers with High Coverage
Optical Probing	SPARTA: A Laser Probing Approach for Trojan Detection
outlier detection	Advanced Outlier Detection Using Unsupervised Learning for Screening Potential Customer Returns
overproduction	Schmitt Trigger-Based Key Provisioning for Locking Analog/RF~Integrated~Circuits
P
P1687.1	Multi-Level Access Protection for Future IEEE P1687.1 IJTAG Networks Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices
P1687.2	Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices
path delay faults	Selecting Close-to-Functional Path Delay Faults for Test Generation
path selection	Selecting Close-to-Functional Path Delay Faults for Test Generation
Path Tracing	Logic Fault Diagnosis of Hidden Delay Defects
Path-delay test	New Perspectives on Core In-field Path Delay Test
PDN	Functional Test Sequences for inducing Voltage Droops in a Multi-Threaded Processor
Performance Hazard	Rapid PLL Monitoring By a novel min-MAX Time-to-Digital Converter
Performance Screening	Machine Learning based Performance Prediction of Microcontrollers using Speed Monitors
PFA	Using Volume Cell-aware Diagnosis Results to Improve Physical Failure Analysis Efficiency
Physical Unclonable Function (PUF)	A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic Gates
Physically Unclonable Function	Cross PUF Attacks on Arbiter-PUFs through their Power Side-Channel
pin-level fault	Functional Criticality Classification of Structural Faults in AI Accelerators
PMIC	Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices
post-silicon testing	Advanced Outlier Detection Using Unsupervised Learning for Screening Potential Customer Returns
post-silicon validation	High Speed Serial Links Risk Assessment in Industrial Post-Silicon Validation Exploiting Machine Learning Techniques
Power amplifier (PA)	Modeling Accuracy of Wideband Power Amplifiers with Memory Effects via Measurements
power delivery network	Functional Test Sequences for inducing Voltage Droops in a Multi-Threaded Processor
Power Side-Channel	Cross PUF Attacks on Arbiter-PUFs through their Power Side-Channel
power-on self-test	Test and Diagnosis Solution for Functional Safety
predistorter (PD)	Modeling Accuracy of Wideband Power Amplifiers with Memory Effects via Measurements
proactive noise mitigation	Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction
Process Variation	Logic Fault Diagnosis of Hidden Delay Defects
Processor	Functional Test Sequences for inducing Voltage Droops in a Multi-Threaded Processor
Q
Quadcopter	Concurrent Error Detection in Embedded Digital Control of Nonlinear Autonomous Systems Using Adaptive State Space Checks
Quality	A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices
Quantized Neural Networks	FAT: Training Neural Networks for Reliable Inference Under Hardware Faults
Quantum Circuit	qATG: Automatic Test Generation for Quantum Circuits
quantum computing	Introduction to Quantum Computation Reliability
quantum error correction	Introduction to Quantum Computation Reliability
quantum fault models	Introduction to Quantum Computation Reliability
R
Radiation Effects	Digital Design Techniques for Dependable High Performance Computing
Radiation hardening	Digital Design Techniques for Dependable High Performance Computing
Random forest	Knowledge Transferring for Diagnosis Outcome Preview with Limited Data
RCAD	Using Volume Cell-aware Diagnosis Results to Improve Physical Failure Analysis Efficiency
read operation	MBIST Supported Reliable eMRAM Sensing
Reconfigurable Scan Networks	Modeling Novel Non-JTAG IEEE 1687-Like Architectures Security Preserving Integration and Resynthesis of Reconfigurable Scan Networks
reducing test application time	Flip-flops fanout splitting in scan designs
redundancy analysis (RA)	Fail Memory Configuration Set for RA Estimation
redundancy structure	Fail Memory Configuration Set for RA Estimation
reference trim	MBIST Supported Reliable eMRAM Sensing
Reflection Coefficient	Design Optimization for N-port RF Network Analyzers under Noise and Gain Imperfections
Register replication	Flip-flops fanout splitting in scan designs
reliability	Assuring Security and Reliability of Emerging Non-Volatile Memories Concurrent detection of failures in GPU control logic for reliable parallel computing Introduction to Quantum Computation Reliability Die-to-Die Testing and ECC Error Mitigation in Automotive and Industrial Safety Applications A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices
Reliability Analysis	Susceptibility Analysis of Logic Gates to Improve the Accuracy of Circuit Reliability Estimation
repair rate	Fail Memory Configuration Set for RA Estimation
repair time	Memory repair logic sharing techniques and their impact on yield
ReRAM	Online Fault Detection in ReRAM-Based Computing Systems by Monitoring Dynamic Power Consumption
Residue Generator	A Unified Method of Designing Signature Analyzers for Digital and Mixed-Signal Circuits Testing
Resilient autonomous systems	Concurrent Error Detection in Embedded Digital Control of Nonlinear Autonomous Systems Using Adaptive State Space Checks
Response Compaction	A Unified Method of Designing Signature Analyzers for Digital and Mixed-Signal Circuits Testing
RF Testing	Design Optimization for N-port RF Network Analyzers under Noise and Gain Imperfections
risk assessment	High Speed Serial Links Risk Assessment in Industrial Post-Silicon Validation Exploiting Machine Learning Techniques
root-cause analysis	Unsupervised Root-Cause Analysis for Integrated Systems
RSFQ logic	Data-driven fault model development for superconducting logic
S
S11 Measurement	Design Optimization for N-port RF Network Analyzers under Noise and Gain Imperfections
Safe Failures	On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors
Safety	FAT: Training Neural Networks for Reliable Inference Under Hardware Faults New Perspectives on Core In-field Path Delay Test Die-to-Die Testing and ECC Error Mitigation in Automotive and Industrial Safety Applications
SAT-ATPG	SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts
Scan Chain Defects	Improved Chain Diagnosis Methodology with clock and control signal defect identification
scan compression design	Flip-flops fanout splitting in scan designs
Scan Distribution Architecture	Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs
Scan Fabric	Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs
Scan Testing	Logic Fault Diagnosis of Hidden Delay Defects
scan-based testing	X-Tolerant Tunable Compactor for In-System Test
Secure DFT	Security Preserving Integration and Resynthesis of Reconfigurable Scan Networks
Security	Assuring Security and Reliability of Emerging Non-Volatile Memories Multi-Level Access Protection for Future IEEE P1687.1 IJTAG Networks
self-labeling	Advanced Outlier Detection Using Unsupervised Learning for Screening Potential Customer Returns
Semi-supervised learning	LAIDAR: Learning for Accuracy and Ideal Diagnostic Resolution
severity	Functional Criticality Classification of Structural Faults in AI Accelerators
short-term current prediction	Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction
signal integrity	Novel Eye Diagram Estimation Technique to Assess Signal Integrity in High-Speed Memory Test
Signature Analyzer	A Unified Method of Designing Signature Analyzers for Digital and Mixed-Signal Circuits Testing
silicon area	Memory repair logic sharing techniques and their impact on yield
Silicon Health Prognosis	Unleashing the Power of Anomaly Data for Soft Failure Predictive Analytics
Simulation	Avionics Simulation Environment
Single Event Transient	Digital Design Techniques for Dependable High Performance Computing
SoC/SiP/NoC Test	Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs
soft error	Concurrent detection of failures in GPU control logic for reliable parallel computing
Soft errors	Digital Design Techniques for Dependable High Performance Computing
Soft Failure	Unleashing the Power of Anomaly Data for Soft Failure Predictive Analytics
Software test library	New Perspectives on Core In-field Path Delay Test
Software-based self-test	New Perspectives on Core In-field Path Delay Test
Speed Monitors	Machine Learning based Performance Prediction of Microcontrollers using Speed Monitors
statistical correlation	Functional Criticality Classification of Structural Faults in AI Accelerators
Statistical Learning	Unleashing the Power of Anomaly Data for Soft Failure Predictive Analytics
Steer-by-wire	Concurrent Error Detection in Embedded Digital Control of Nonlinear Autonomous Systems Using Adaptive State Space Checks
stress	Wafer Level Stress: Enabling Zero Defect Quality for Automotive Microcontrollers without Package Burn-In
structural fault	Functional Criticality Classification of Structural Faults in AI Accelerators
STT-MRAMs	Characterization, Modeling, and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs
stuck-at	Functional Criticality Classification of Structural Faults in AI Accelerators
supply-chain attacks	Schmitt Trigger-Based Key Provisioning for Locking Analog/RF~Integrated~Circuits
support vector machines	High Speed Serial Links Risk Assessment in Industrial Post-Silicon Validation Exploiting Machine Learning Techniques
Synthesis-APR	Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization
system margin validation	High Speed Serial Links Risk Assessment in Industrial Post-Silicon Validation Exploiting Machine Learning Techniques
T
test	Assuring Security and Reliability of Emerging Non-Volatile Memories
test application time	X-Tolerant Tunable Compactor for In-System Test
Test chip	High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips
Test compression	Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations
Test data volume estimation	Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations
Test design	Avionics Simulation Environment
Test Generation	Selecting Close-to-Functional Path Delay Faults for Test Generation qATG: Automatic Test Generation for Quantum Circuits
Test pattern count estimation	Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations
test points	Flip-flops fanout splitting in scan designs
test sequences	Functional Test Sequences for inducing Voltage Droops in a Multi-Threaded Processor
Test Time Reduction	Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs
Threshold M of N (THMN) gates	A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic Gates
Time-to-Digital Converter	Rapid PLL Monitoring By a novel min-MAX Time-to-Digital Converter
Transfer learning	Knowledge Transferring for Diagnosis Outcome Preview with Limited Data
Two-phase clocking	Test Challenges of Intel IA Cores
two-tier flow	Functional Criticality Classification of Structural Faults in AI Accelerators
U
under-kill	Cost-Effective Test Method that can screen out Unexpected Failure in High Speed Serial Interface IPs
unexpected failure	Cost-Effective Test Method that can screen out Unexpected Failure in High Speed Serial Interface IPs
unknown states	X-Tolerant Tunable Compactor for In-System Test
unsupervised learning	Advanced Outlier Detection Using Unsupervised Learning for Screening Potential Customer Returns Unsupervised Root-Cause Analysis for Integrated Systems Learning A Wafer Feature With One Training Sample
Untrusted Foundry	SPARTA: A Laser Probing Approach for Trojan Detection
V
Vmin	Functional Test Sequences for inducing Voltage Droops in a Multi-Threaded Processor
voltage droop	Functional Test Sequences for inducing Voltage Droops in a Multi-Threaded Processor
W
wafer defect map	TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning
wafer level burn-in	Wafer Level Stress: Enabling Zero Defect Quality for Automotive Microcontrollers without Package Burn-In
Wafer plot	Learning A Wafer Feature With One Training Sample
X
X-masking	X-Tolerant Tunable Compactor for In-System Test
Y
yield	MBIST Supported Reliable eMRAM Sensing Memory repair logic sharing techniques and their impact on yield Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization Improved Chain Diagnosis Methodology with clock and control signal defect identification
yield learning	High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips Using Volume Cell-aware Diagnosis Results to Improve Physical Failure Analysis Efficiency
Z
zero defect	Wafer Level Stress: Enabling Zero Defect Quality for Automotive Microcontrollers without Package Burn-In

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