ITC2020: INTERNATIONAL TEST CONFERENCE 2020

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Abdalwahab, Mahmoud	Modeling Novel Non-JTAG IEEE 1687-Like Architectures
Abraham, Jacob	Functional Test Sequences for inducing Voltage Droops in a Multi-Threaded Processor
Acharya, Rabin Yu	A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic Gates
Agrawal, Nidhi	Automated Socket Anomaly Detection through Deep Learning
Agrawal, Vishwani	Machine Intelligence for Efficient Test Pattern Generation
Ahn, Sang-Uck	Cost-Effective Test Method that can screen out Unexpected Failure in High Speed Serial Interface IPs
Amarnath, Chandramouli	Concurrent Error Detection in Embedded Digital Control of Nonlinear Autonomous Systems Using Adaptive State Space Checks
Anghel, Lorena	New Perspectives on Core In-field Path Delay Test
Aquino Guazzelli, Ricardo	At-speed DfT Architecture for Bundled-data Design
Aromando, John	Automated Assertion Generation from Natural Language Specifications
Atteya, Ahmed	Security Preserving Integration and Resynthesis of Reconfigurable Scan Networks
Avci, Muslum Emir	Design Optimization for N-port RF Network Analyzers under Noise and Gain Imperfections
Azimi, Sarah	Digital Design Techniques for Dependable High Performance Computing
B
Baby, Manu	IJTAG Through a Two-Pin Chip Interface
Benhebibi, Mohamed	Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices
Bhagavatheeswaran, Gayathri	Stress, Test, and Simulation of Analog IO Pads on Automotive ICs
Blanton, Shawn	LAIDAR: Learning for Accuracy and Ideal Diagnostic Resolution Knowledge Transferring for Diagnosis Outcome Preview with Limited Data High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips
Blott, Michaela	FAT: Training Neural Networks for Reliable Inference Under Hardware Faults
Boschi, Gabriele	Die-to-Die Testing and ECC Error Mitigation in Automotive and Industrial Safety Applications
Bosio, Alberto	A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns
Boujamaa, Mehdi	MBIST Supported Reliable eMRAM Sensing
Boullion, William	A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic Gates
Bramley, Richard	On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors
Brauchler III, David	Multi-Level Access Protection for Future IEEE P1687.1 IJTAG Networks
Buettner, Bernd	IJTAG Through a Two-Pin Chip Interface
C
Cantoro, Riccardo	New Perspectives on Core In-field Path Delay Test Machine Learning based Performance Prediction of Microcontrollers using Speed Monitors
Casarsa, Marco	Test and Diagnosis Solution for Functional Safety
Chakrabarty, Krishnendu	Online Fault Detection in ReRAM-Based Computing Systems by Monitoring Dynamic Power Consumption
Chakrabarty, Krishnendu	Functional Criticality Classification of Structural Faults in AI Accelerators Unsupervised Root-Cause Analysis for Integrated Systems BISTLock: Efficient IP Piracy Protection using BIST
Chang, I.-Y.	Using Volume Cell-aware Diagnosis Results to Improve Physical Failure Analysis Efficiency
Chatterjee, Abhijit	Fast EVM Tuning of MIMO Wireless Systems Using Collaborative Parallel Testing and Implicit Reward Driven Learning SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts Concurrent Error Detection in Embedded Digital Control of Nonlinear Autonomous Systems Using Adaptive State Space Checks
Chaudhuri, Arjun	Functional Criticality Classification of Structural Faults in AI Accelerators
Chen, Degang	Robust DfT Techniques for Built-in Fault Detection in Operational Amplifiers with High Coverage
Chen, Hao	A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices
Chen, Jun	Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction
Chen, Leon Li-Yang	TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning
Chen, Siyuan	BISTLock: Efficient IP Piracy Protection using BIST
Chen, Wei-Hao	Rapid PLL Monitoring By a novel min-MAX Time-to-Digital Converter
Cheng, Ken Chau-Cheung	TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning
Cheng, Wei	Cross PUF Attacks on Arbiter-PUFs through their Power Side-Channel
Cheng, Wu-Tung	Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations
Chhabra, Atul	Improved Chain Diagnosis Methodology with clock and control signal defect identification
Chillarige, Sameer	Improved Chain Diagnosis Methodology with clock and control signal defect identification
Cho, Keewon	Fail Memory Configuration Set for RA Estimation
Chou, Leon	TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning
Chowdhury, Sreeja	A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic Gates
Chuang, Chien-Hui	A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices
Colon-Bonet, Glenn	Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs
Coyette, Anthony	Quick Analyses for Improving Reliability and Functional Safety of Mixed-Signal ICs
Crouch, Alfred	Modeling Novel Non-JTAG IEEE 1687-Like Architectures
Côté, J-F	IJTAG Through a Two-Pin Chip Interface Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs
D
Danger, Jean-Luc	Cross PUF Attacks on Arbiter-PUFs through their Power Side-Channel
Danialy, Givargis	IJTAG Through a Two-Pin Chip Interface
Desiga-Orenday, Aaron	High Speed Serial Links Risk Assessment in Industrial Post-Silicon Validation Exploiting Machine Learning Techniques
Di, Jia	A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic Gates
Dobbelaere, Wim	Quick Analyses for Improving Reliability and Functional Safety of Mixed-Signal ICs
Dray, Cyrille	MBIST Supported Reliable eMRAM Sensing
Duan, Guangshan	On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors
Durgun, Gökhan	Avionics Simulation Environment
Dworak, Jennifer	Multi-Level Access Protection for Future IEEE P1687.1 IJTAG Networks
E
Eide, Geir	Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs
Engelke, Piet	IJTAG Through a Two-Pin Chip Interface
F
Fan, Jeff	Using Volume Cell-aware Diagnosis Results to Improve Physical Failure Analysis Efficiency
Fang, Chenlei	LAIDAR: Learning for Accuracy and Ideal Diagnostic Resolution Knowledge Transferring for Diagnosis Outcome Preview with Limited Data
Farahmandi, Farimah	SPARTA: A Laser Probing Approach for Trojan Detection
Felder, Andrew	A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic Gates
Fesquet, Laurent	At-speed DfT Architecture for Bundled-data Design
Forte, Domenic	A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic Gates
Foti, Dario	New Perspectives on Core In-field Path Delay Test
Fraser, Nicholas J.	FAT: Training Neural Networks for Reliable Inference Under Hardware Faults
Frederiksen, Steven	Automated Assertion Generation from Natural Language Specifications
G
Gambardella, Giulio	FAT: Training Neural Networks for Reliable Inference Under Hardware Faults
Ganji, Mona	Robust DfT Techniques for Built-in Fault Detection in Operational Amplifiers with High Coverage
Gao, Wei	Modeling Accuracy of Wideband Power Amplifiers with Memory Effects via Measurements
Gaudet, Jonathan	IJTAG Through a Two-Pin Chip Interface
Gelda, Khushal	MBIST Supported Reliable eMRAM Sensing
Geurkov, Vadim	A Unified Method of Designing Signature Analyzers for Digital and Mixed-Signal Circuits Testing
Gielen, Georges	Quick Analyses for Improving Reliability and Functional Safety of Mixed-Signal ICs
Girard, Patrick	A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns
Go, Byeongseon	Novel Eye Diagram Estimation Technique to Assess Signal Integrity in High-Speed Memory Test
Gomez, Jhon	Quick Analyses for Improving Reliability and Functional Safety of Mixed-Signal ICs
Goteti, Prashant	Unleashing the Power of Anomaly Data for Soft Failure Predictive Analytics
Grigoryan, Hayk	Die-to-Die Testing and ECC Error Mitigation in Automotive and Industrial Safety Applications
Gu, Xinli	Unsupervised Root-Cause Analysis for Integrated Systems
Guilley, Sylvain	Cross PUF Attacks on Arbiter-PUFs through their Power Side-Channel
Gummidipoondi Jayasankaran, Nithyashankari	Schmitt Trigger-Based Key Provisioning for Locking Analog/RF~Integrated~Circuits
Gupta, Sandeep	Data-driven fault model development for superconducting logic
Gupta, Sanya	SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts
H
Hamdioui, Said	Characterization, Modeling, and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs
Han, Dongmin	Novel Eye Diagram Estimation Technique to Assess Signal Integrity in High-Speed Memory Test
Han, Jing	Scalable Test AccessIEEE 1687-Based Testing Methodology for AI SoC
Harutyunyan, Gurgen	Die-to-Die Testing and ECC Error Mitigation in Automotive and Industrial Safety Applications Test and Diagnosis Solution for Functional Safety
Hashimoto, Masanori	Concurrent detection of failures in GPU control logic for reliable parallel computing Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction
He, Chen	Stress, Test, and Simulation of Analog IO Pads on Automotive ICs Wafer Level Stress: Enabling Zero Defect Quality for Automotive Microcontrollers without Package Burn-In Advanced Outlier Detection Using Unsupervised Learning for Screening Potential Customer Returns
Hellebrand, Sybille	Logic Fault Diagnosis of Hidden Delay Defects
Ho, Chee-Wah	Automated Socket Anomaly Detection through Deep Learning
Holst, Stefan	Logic Fault Diagnosis of Hidden Delay Defects
Hou, Kuan-Wei	A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices
Howard, Mark	A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic Gates
Hsia, Mao-Yuan	Using Volume Cell-aware Diagnosis Results to Improve Physical Failure Analysis Efficiency
Hsiao, Michael	Automated Assertion Generation from Natural Language Specifications
Hsieh, Cheng-Yun	qATG: Automatic Test Generation for Quantum Circuits
Hsu, Chu-Chun	Rapid PLL Monitoring By a novel min-MAX Time-to-Digital Converter
Hu, Hanbin	Advanced Outlier Detection Using Unsupervised Learning for Screening Potential Customer Returns
Hu, Jiang	Schmitt Trigger-Based Key Provisioning for Locking Analog/RF~Integrated~Circuits
Huang, Andrew Yi-Ann	TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning
Huang, Qicheng	LAIDAR: Learning for Accuracy and Ideal Diagnostic Resolution Knowledge Transferring for Diagnosis Outcome Preview with Limited Data
Huang, Shi-Yu	Rapid PLL Monitoring By a novel min-MAX Time-to-Digital Converter
Huang, Yanxiang	On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors
Huang, Yu	Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations
Huang, Yu	Scalable Test AccessIEEE 1687-Based Testing Methodology for AI SoC
Huch, Martin	Machine Learning based Performance Prediction of Microcontrollers using Speed Monitors
I
Ito, Kojiro	Concurrent detection of failures in GPU control logic for reliable parallel computing
Itsuji, Hiroaki	Concurrent detection of failures in GPU control logic for reliable parallel computing
J
Janiszewski, Wojciech	Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs
Jeong, Woosik	Fail Memory Configuration Set for RA Estimation Novel Eye Diagram Estimation Technique to Assess Signal Integrity in High-Speed Memory Test
Jing, Tao	Modeling Accuracy of Wideband Power Amplifiers with Memory Effects via Measurements
Juarez-Hernandez, Esdras	High Speed Serial Links Risk Assessment in Industrial Post-Silicon Validation Exploiting Machine Learning Techniques
Jung, Jinwook	BISTLock: Efficient IP Piracy Protection using BIST
K
Kaczmarek, Bartosz	Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs
Kalyanam, Vijay Kiran	Functional Test Sequences for inducing Voltage Droops in a Multi-Threaded Processor
Kampmann, Matthias	Logic Fault Diagnosis of Hidden Delay Defects
Kang, Sungho	Fail Memory Configuration Set for RA Estimation
Kang, Wooheon	Fail Memory Configuration Set for RA Estimation
Kar, Gouri Sankar	Characterization, Modeling, and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs
Karimi, Naghmeh	Cross PUF Attacks on Arbiter-PUFs through their Power Side-Channel
Karmakar, Rajit	Hardware IP Protection Using Logic Encryption and Watermarking
Kassab, Mark	Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs
Keim, Martin	IJTAG Through a Two-Pin Chip Interface Scalable Test AccessIEEE 1687-Based Testing Methodology for AI SoC Modeling Novel Non-JTAG IEEE 1687-Like Architectures MBIST Supported Reliable eMRAM Sensing
Khan, Mohammad Nasim Imtiaz	Assuring Security and Reliability of Emerging Non-Volatile Memories
Kilian, Tobias	Machine Learning based Performance Prediction of Microcontrollers using Speed Monitors
Kim, Hyun-Woo	Cost-Effective Test Method that can screen out Unexpected Failure in High Speed Serial Interface IPs
Kim, Hyung-Tae	Cost-Effective Test Method that can screen out Unexpected Failure in High Speed Serial Interface IPs
Kim, Young-Dae	Cost-Effective Test Method that can screen out Unexpected Failure in High Speed Serial Interface IPs
Kirischian, Lev	A Unified Method of Designing Signature Analyzers for Digital and Mixed-Signal Circuits Testing
Komarraju, Suhasini	Fast EVM Tuning of MIMO Wireless Systems Using Collaborative Parallel Testing and Implicit Reward Driven Learning
Kroeger, Trevor	Cross PUF Attacks on Arbiter-PUFs through their Power Side-Channel
Kumar, Arun	Die-to-Die Testing and ECC Error Mitigation in Automotive and Industrial Safety Applications
L
L'Esperance, Nicholai	Improved Chain Diagnosis Methodology with clock and control signal defect identification
Ladhar, Aymen	A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns
Ladnushkin, Maxim	Flip-flops fanout splitting in scan designs
Laisne, Michael	Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices Modeling Novel Non-JTAG IEEE 1687-Like Architectures
Lee, Chen-Shiun	TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning
Lee, Hayoung	Fail Memory Configuration Set for RA Estimation
Lee, Kuen-Jong	Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations
Lee, Mincent	A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices
Lee, Sanghoon	Schmitt Trigger-Based Key Provisioning for Locking Analog/RF~Integrated~Circuits
Lee, Seungtaek	Fail Memory Configuration Set for RA Estimation Novel Eye Diagram Estimation Technique to Assess Signal Integrity in High-Speed Memory Test
Leventhal, Ira	Automated Socket Anomaly Detection through Deep Learning
Li, James Chien-Mo	qATG: Automatic Test Generation for Quantum Circuits
Li, Jiun-Yun	qATG: Automatic Test Generation for Quantum Circuits
Li, Katherine Shu-Min	TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning
Li, Mingye	Data-driven fault model development for superconducting logic
Li, Peng	Advanced Outlier Detection Using Unsupervised Learning for Screening Potential Customer Returns
Li, Xin	Unsupervised Root-Cause Analysis for Integrated Systems
Liao, Zhiwei	SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts
Lin, Xijiang	Test Challenges of Intel IA Cores
Liu, Mengyun	Online Fault Detection in ReRAM-Based Computing Systems by Monitoring Dynamic Power Consumption
Liu, Yingdi	X-Tolerant Tunable Compactor for In-System Test
Liu, Zeye	High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips
Lopez-Meyer, Paulo	High Speed Serial Links Risk Assessment in Industrial Post-Silicon Validation Exploiting Machine Learning Techniques
Lu, Ligang	Scalable Test AccessIEEE 1687-Based Testing Methodology for AI SoC
Lylina, Natalia	Security Preserving Integration and Resynthesis of Reconfigurable Scan Networks
M
Ma, Haiying	Scalable Test AccessIEEE 1687-Based Testing Methodology for AI SoC
Mahurin, Eric	Functional Test Sequences for inducing Voltage Droops in a Multi-Threaded Processor
Malik, Anil	Improved Chain Diagnosis Methodology with clock and control signal defect identification
Marinissen, Erik Jan	Characterization, Modeling, and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs
Martone, Raffaele	Machine Learning based Performance Prediction of Microcontrollers using Speed Monitors
Mehta, Dhwani	SPARTA: A Laser Probing Approach for Trojan Detection
Meier, Reinhard	IJTAG Through a Two-Pin Chip Interface Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs
Meng, Fanjin	Scalable Test AccessIEEE 1687-Based Testing Methodology for AI SoC
Mhamdi, Safa	A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns
Milewski, Sylwester	X-Tolerant Tunable Compactor for In-System Test
Millican, Spencer	Machine Intelligence for Efficient Test Pattern Generation
Momtaz, Md	Concurrent Error Detection in Embedded Digital Control of Nonlinear Autonomous Systems Using Adaptive State Space Checks
Mrugalski, Grzegorz	X-Tolerant Tunable Compactor for In-System Test
Mukherjee, Nilanjan	X-Tolerant Tunable Compactor for In-System Test
Mysore, Naveen	Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs
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Nadeau-Dostie, Benoit	Memory repair logic sharing techniques and their impact on yield MBIST Supported Reliable eMRAM Sensing
Nam, Gi-Joon	BISTLock: Efficient IP Piracy Protection using BIST
Nandakumar, Bharath	Improved Chain Diagnosis Methodology with clock and control signal defect identification
Nandi, Shreyas	SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts
Natarajan, Suriyaprakash	SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts
Nguyen, Nguyen	Advanced Outlier Detection Using Unsupervised Learning for Screening Potential Customer Returns
O
Oh, Ghil-Geun	Cost-Effective Test Method that can screen out Unexpected Failure in High Speed Serial Interface IPs
Oh, Youngsu	Novel Eye Diagram Estimation Technique to Assess Signal Integrity in High-Speed Memory Test
Orlando, Peter	Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs
Ozev, Sule	Design Optimization for N-port RF Network Analyzers under Noise and Gain Imperfections
P
Pan, Renjian	Unsupervised Root-Cause Analysis for Integrated Systems
Pandey, Sujay	SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts
Pang, Man-Ting	Using Volume Cell-aware Diagnosis Results to Improve Physical Failure Analysis Efficiency
Pant, Pankaj	Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs
Peng, Hanson	Using Volume Cell-aware Diagnosis Results to Improve Physical Failure Analysis Efficiency
Pfannkuchen, Ulrike	IJTAG Through a Two-Pin Chip Interface
Pomeranz, Irith	Selecting Close-to-Functional Path Delay Faults for Test Generation
Portolan, Michele	New Perspectives on Core In-field Path Delay Test Modeling Novel Non-JTAG IEEE 1687-Like Architectures
Q
Qian, Haitao	Scalable Test AccessIEEE 1687-Based Testing Methodology for AI SoC
R
Racunas, Paul	On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors
Rajendran, Jeyavijayan	Schmitt Trigger-Based Key Provisioning for Locking Analog/RF~Integrated~Circuits
Rajski, Janusz	Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations X-Tolerant Tunable Compactor for In-System Test Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs
Rao, Siddharth	Characterization, Modeling, and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs
Rearick, Jeff	Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices Modeling Novel Non-JTAG IEEE 1687-Like Architectures
Redburn, Robert	Improved Chain Diagnosis Methodology with clock and control signal defect identification
Reddy, Sudhakar M.	Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations
Reimer, Jan Dennis	Logic Fault Diagnosis of Hidden Delay Defects
Rodrigues, Ricardo	Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs
Romain, Luc	Memory repair logic sharing techniques and their impact on yield
Roy, Soham	Machine Intelligence for Efficient Test Pattern Generation
S
Sagirkaya, Huseyin	Avionics Simulation Environment
Saikiran, Marampally	Robust DfT Techniques for Built-in Fault Detection in Operational Amplifiers with High Coverage
Sanabria-Borbón, Adriana C.	Schmitt Trigger-Based Key Provisioning for Locking Analog/RF~Integrated~Circuits
Sanchez, Hector	Stress, Test, and Simulation of Analog IO Pads on Automotive ICs
Sanchez-Martinez, Cesar A.	High Speed Serial Links Risk Assessment in Industrial Post-Silicon Validation Exploiting Machine Learning Techniques
Sartoni, Sandro	New Perspectives on Core In-field Path Delay Test
Saxena, Nirmal	On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors
Schaub, Keith	Automated Socket Anomaly Detection through Deep Learning
Schlichtmann, Ulf	Machine Learning based Performance Prediction of Microcontrollers using Speed Monitors
Schramm, Lori	IJTAG Through a Two-Pin Chip Interface MBIST Supported Reliable eMRAM Sensing
Schvittz, Rafael Budim	Susceptibility Analysis of Logic Gates to Improve the Accuracy of Circuit Reliability Estimation
Seo, Beom-Kyu	Cost-Effective Test Method that can screen out Unexpected Failure in High Speed Serial Interface IPs
Shan, Chuanhe	Learning A Wafer Feature With One Training Sample
Sharma, Manish	Using Volume Cell-aware Diagnosis Results to Improve Physical Failure Analysis Efficiency
Shin, Yeoun-Sook	Cost-Effective Test Method that can screen out Unexpected Failure in High Speed Serial Interface IPs
Shpiro, Uri	Test Challenges of Intel IA Cores
Singh, Adit	SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts
Singhal, Rahul	Scalable Test AccessIEEE 1687-Based Testing Methodology for AI SoC
Sinha, Arani	SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts
Song, Peilin	BISTLock: Efficient IP Piracy Protection using BIST
Sonza Reorda, Matteo	New Perspectives on Core In-field Path Delay Test
Spano, Elisa	Die-to-Die Testing and ECC Error Mitigation in Automotive and Industrial Safety Applications
Spence, Michael	Functional Test Sequences for inducing Voltage Droops in a Multi-Threaded Processor
Sprenger, Alexander	Logic Fault Diagnosis of Hidden Delay Defects
Squillero, Giovanni	Machine Learning based Performance Prediction of Microcontrollers using Speed Monitors
Stern, Andrew	SPARTA: A Laser Probing Approach for Trojan Detection
Su, Fei	Functional Criticality Classification of Structural Faults in AI Accelerators Unleashing the Power of Anomaly Data for Soft Failure Predictive Analytics
Sumikawa, Nik	Learning A Wafer Feature With One Training Sample
Sunter, Stephen	Quick Analyses for Improving Reliability and Functional Safety of Mixed-Signal ICs
Sánchez-Sinencio, Edgar	Schmitt Trigger-Based Key Provisioning for Locking Analog/RF~Integrated~Circuits
T
Tajik, Shahin	SPARTA: A Laser Probing Approach for Trojan Detection
Talukdar, Jonti	Functional Criticality Classification of Structural Faults in AI Accelerators
Tang, Huaxing	Using Volume Cell-aware Diagnosis Results to Improve Physical Failure Analysis Efficiency
Taouil, Mottaqiallah	Characterization, Modeling, and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs
Tehranipoor, Mark	SPARTA: A Laser Probing Approach for Trojan Detection
Thangamariappan, Vijay	Automated Socket Anomaly Detection through Deep Learning
Thornton, Mitchell	Introduction to Quantum Computation Reliability
Toba, Tadanobu	Concurrent detection of failures in GPU control logic for reliable parallel computing
Traynor, Stephen	Stress, Test, and Simulation of Analog IO Pads on Automotive ICs
Tsai, Chia-Heng	A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices
Tsai, Fong-Jyun	Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations
Tsai, Kun-Han	Test Challenges of Intel IA Cores
Tsai, Nova Chen-Yen	TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning
Tyszer, Jerzy	X-Tolerant Tunable Compactor for In-System Test
U
Uezono, Takumi	Concurrent detection of failures in GPU control logic for reliable parallel computing
V
Van Treuren, Brad	Modeling Novel Non-JTAG IEEE 1687-Like Architectures
Vanhooren, Ronny	Quick Analyses for Improving Reliability and Functional Safety of Mixed-Signal ICs
Venkataaman, Srikanth	Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization
Virazel, Arnaud	A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns
Vissers, Kees	FAT: Training Neural Networks for Reliable Inference Under Hardware Faults
Viveros-Wacher, Andres	High Speed Serial Links Risk Assessment in Industrial Post-Silicon Validation Exploiting Machine Learning Techniques
von Staudt, Hans Martin	Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices Modeling Novel Non-JTAG IEEE 1687-Like Architectures
W
Wang, Chih-Hao	Security Preserving Integration and Resynthesis of Reconfigurable Scan Networks
Wang, Fangzhou	Data-driven fault model development for superconducting logic
Wang, Li-C.	Learning A Wafer Feature With One Training Sample
Wang, Min-Jer	A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices
Wang, Sying-Jyan	TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning
Wee, Khen	Test Challenges of Intel IA Cores
Wen, Xiaoqing	Logic Fault Diagnosis of Hidden Delay Defects
Wen, Xin	Scalable Test AccessIEEE 1687-Based Testing Methodology for AI SoC
Wlodarczak, Bartosz	X-Tolerant Tunable Compactor for In-System Test
Wolinski, Michał	Quick Analyses for Improving Reliability and Functional Safety of Mixed-Signal ICs
Wu, Chen-Hung	qATG: Automatic Test Generation for Quantum Circuits
Wu, Cheng-Wen	A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices
Wu, Lizhou	Characterization, Modeling, and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs
Wunderlich, Hans-Joachim	Logic Fault Diagnosis of Hidden Delay Defects Security Preserving Integration and Resynthesis of Reconfigurable Scan Networks
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Xama, Nektar	Quick Analyses for Improving Reliability and Functional Safety of Mixed-Signal ICs
Xanthopoulos, Constantinos	Automated Socket Anomaly Detection through Deep Learning
Xiao, Joe	Automated Socket Anomaly Detection through Deep Learning
Y
Yang, Wu	Scalable Test AccessIEEE 1687-Based Testing Methodology for AI SoC Using Volume Cell-aware Diagnosis Results to Improve Physical Failure Analysis Efficiency
Ye, Chong-Siao	Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations
Yin, Ya	Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs
Yu, Yanyao	Wafer Level Stress: Enabling Zero Defect Quality for Automotive Microcontrollers without Package Burn-In
Yun, Jongsin	MBIST Supported Reliable eMRAM Sensing
Z
Zahid, Ussama	FAT: Training Neural Networks for Reliable Inference Under Hardware Faults
Zawada, Justyna	Test Challenges of Intel IA Cores
Zeng, Yueling	Learning A Wafer Feature With One Training Sample
Zhang, Min	Unleashing the Power of Anomaly Data for Soft Failure Predictive Analytics
Zhang, Zhaobo	Unsupervised Root-Cause Analysis for Integrated Systems
Zheng, Shi-Xuan	Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations
Zorian, Yervant	Test and Diagnosis Solution for Functional Safety

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