ABSTRACT. In this paper, we will present our HVST methodology on analog IO pads, as well as reliability simulators to help assess the stress coverage and aging effect on analog IOs. Silicon results on 16nm FinFET automotive microprocessor are discussed to demonstrate the effectiveness and efficiency of our methodology.

ABSTRACT. This paper shows how measuring the percentage of circuit elements subjected to sufficient stress during testing, especially across thin oxides, can be a criterion for reliability improvement of automotive ICs. The paper also shows how to more accurately compute a circuit’s ISO 26262 metrics by basing defect likelihoods on activity.

ABSTRACT. Accurate determination of the safe-fault failure rate of complex digital designs is an exascale problem. We present a novel measurement methodology and results which could have a profound impact on the performance and availability for GPUs in safety critical systems. We extend our analysis with a methodology for in-the-field estimation.

ABSTRACT. In this paper, we propose a new framework for cell-aware defect diagnosis of customer returns based on supervised learning. The proposed flow indistinctly deals with static and dynamic defects that may occur in real circuits. A Naive Bayes classifier is used to precisely identify defect candidates.

ABSTRACT. Hidden delay defects (HDD) are an important indicator of possible early-life failures. Faster-than-at-Speed Testing (FAST) screens for HDDs by observing outputs of sensitized non-critical paths. We present the very first fault diagnosis approach that is able to locate HDDs by analyzing FAST fail-logs. Experiments shows its performance and scalability.

ABSTRACT. This paper presents a fail memory configuration set for RA estimation, called as ITC’2020 RA Benchmarks. It enables objective RA estimations with respect to efficiency. The fail memory configuration set includes memory models with various redundancies and a fault generation algorithm with fault distribution which can be criteria for comparisons.

ABSTRACT. This work compares structural and functional approaches for the test of path delay faults in microprocessors. Typical test programs developed for in-field testing of stuck-at faults are evaluated using an ad-hoc framework built on top of commercial fault simulators, thus offering the possibility of improving their fault coverage.

ABSTRACT. We present a generic method for designing algebraic/arithmetic signature analyzers. The aliasing rate is estimated. The design technique is valid for an arbitrary number system. The proposed devices have low hardware complexity and low aliasing rate. The technique can also be used in error-control coding, cryptography and digital communication.

ABSTRACT. This paper describes a path selection procedure whose new feature is to consider the extent to which target path delay faults can be activated during functional operation in addition to the path length and detectability.

ABSTRACT. This paper presents a method of flip-flops fanout splitting by register replication in order to reduce test application time during an ATPG. Experimental results on several IP-designs show that the proposed method reduces test time up to 2 times with hardware costs not exceeding 2.5% of design area.

ABSTRACT. Two efficient methods to predict test pattern count and data volume with different input channel counts are presented. Experimental results show that the average error rates are less than 10%. Both methods can reduce the total ATPG time by more than 10X compared to currently used trial-and-error method.

ABSTRACT. Based on the parametric data of 360,000 IPDs collected from the wafer probing test, the proposed SQnet is trained to predict the IPDs which have low reliability. Keeping the overkill rate below 10%, our method can screen out 6 to 15X more bad dies than the existing industrial methods.

ABSTRACT. Diagnosis outcome can be predicted from the data collected from failing ICs, but sufficient training data is necessary for an accurate model. We construct a prior model from a correlated dataset and adapt it to limited training samples. The method can save training data when a suitable prior knowledge exists.

ABSTRACT. This paper discusses the automotive requirements of ISO 26262 standard and its implication on conventional test and diagnosis flows. It presents a safety-oriented manufacturing test and diagnosis solution meeting automotive system-on-chip (SoC) requirements. The implementation details, automotive features and experimental results are described showing the effectiveness of the proposed solution.

ABSTRACT. In this paper, we present a new wafer level stress methodology consisting of enhanced High Voltage Stress Test (eHVST), Wafer Level Burn-In (WLBI), and enhanced Advanced Outlier Limit (eAOL) screens, which can achieve Zero Defect quality for automotive microcontrollers without package BI.

ABSTRACT. We propose the use of adaptive time-varying checks on linearized state space representations of nonlinear systems for detecting errors in sensors, actuators and control software of autonomous systems in real time. The approach incurs small memory and computation overhead and is experimentally validated on quadcopter and automotive steer-by-wire systems.

ABSTRACT. The paper presents maXpress – an X-tolerant programmable compactor deploying a new scan chain selection mechanism capable of completely (as required by in-system test applications) masking X states within redefinable groups of scan chains and designated scan shift cycles. The paper also proposes an algorithm to automate maXpress control settings.

ABSTRACT. SSN is a bus-based scan data distribution architecture for SoCs. Enables simultaneous testing of any number of cores even with few IOs, fast test time, scalable identical core handling, with simplified planning and physical design.

ABSTRACT. This work explores an at-speed testing approach for bundled-data circuits, targeting the micropipeline design. By adding extra controllability points in the controllers and taking advantage of scan-chain structures, this work targets to generate/stall tokens in pre-defined parts of the circuit, enabling circuit verification through available scan chains.

ABSTRACT. A Deep Learning application for the detection of defective tester sockets. The proposed methodology relies on images like those used for manual inspection, that are commonly collected using AOI equipment. This work represents a practical example of the use of Machine Learning for achieving improved inspection-quality outcomes at lower cost.

ABSTRACT. We propose a machine learning based method targeted for accurate wafer defect map classification. The proposed method is referred to as TestDNA-E, as it applies ensemble learning based on improved TestDNA features. Experimental results show that the proposed method achieves high hit rate for each defect type and overall accuracy.

ABSTRACT. Testing electronic devices for well-known fault models is not sufficient for effective performance screening. We propose a complete methodology, from the extraction of reliable measures, through a machine-learning algorithm, down to post-processing steps to characterize the production data for quality. Experimental results demonstrate the feasibility of the proposed solution.

ABSTRACT. We propose a method which combines RCAD analysis and systematic cell information for volume diagnosis results for efficient yield learning and PFA process. The proposed method was validated on real silicon data from an advanced FinFET technology and successfully identified a systematic cell internal issue with dramatically improved PFA efficiency.