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Keynote (30 minutes)
Title: Reverse Engineering Visual Intelligence
The brain and cognitive sciences are hard at work on a great scientific quest — to reverseengineer the human mind and its intelligent behavior. Yet these field are still in their infancy.Not surprisingly, forward engineering approaches that aim to emulate human intelligence (HI)in artificial systems (AI) are also still in their infancy. Yet the intelligence and cognitive flexibilityapparent in human behavior are an existence proof that machines can be constructed toemulate and work alongside the human mind.I believe that these challenges of reverse engineering human intelligence will be solved bytightly combining the efforts of brain and cognitive scientists (hypothesis generation and dataacquisition), and forward engineering aiming to emulate intelligent behavior (hypothesisinstantiation and data prediction). As this approach discovers the correct neural networkmodels, those models will not only encapsulate our understanding of complex brain systems,they will be the basis of next-generation computing and novel brain interfaces for therapeuticand augmentation goals (e.g, brain disorders).In this session, I will focus on one aspect of human intelligence — visual object categorizationand detection — and I will tell the story of how work in brain science, cognitive science andcomputer science converged to create deep neural networks that can support suchtasks. These networks not only reach human performance for many images, but their internalworkings are modeled after— and largely explain and predict — the internal workings of theprimate visual system. Yet, the primate visual system (HI) still outperforms current generationartificial deep neural networks (AI), and I will show some new clues that the brain and cognitivesciences can offer.These recent successes and related work suggest that the brain and cognitive sciencescommunity is poised to embrace a powerful new research paradigm. More broadly, our speciesis the beginning of its most important science quest — the quest to understand humanintelligence — and I hope to motivate others to engage that frontier alongside us.
About the speaker
James DiCarlo is a Professor of Neuroscience, and Head of the Department of Brain andCognitive Sciences at the Massachusetts Institute of Technology. His research goal is toreverse engineer the brain mechanisms that underlie human visual intelligence. He and hiscollaborators have revealed how population image transformations carried out by a deep stackof neocortical processing stages -- called the primate ventral visual stream -- are effortlesslyable to extract object identity from visual images. His team uses a combination of large-scaleneurophysiology, brain imaging, direct neural perturbation methods, and machine learningmethods to build and test artificial neural network models of the ventral visual stream and itssupport of cognition and behavior. Such an engineering-based understanding is likely to leadto new artificial vision and artificial intelligence approaches, new brain-machine interfaces torestore or augment lost senses, and a new foundation to ameliorate disorders of the mind.
Link to James J. DiCarlo M.D., Ph.D., MIT
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Visionary Talk - TBD (30 minutes)
Top three papers selected from the review process as Distingushed papers.
11:30 | Learning A Wafer Feature With One Training Sample PRESENTER: Yueling Zeng ABSTRACT. We introduce an approach called Manifestation Learning to enable learning a wafer plot recognizer with one training sample. Using wafer probe test data from an automotive product line, this paper explains the learning approach, its feasibility and limitation. |
11:50 | Characterization, Modeling, and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs PRESENTER: Lizhou Wu ABSTRACT. This paper discovers a new unique defect: Synthetic Anti-Ferromagnet Flip (SAFF) in STT-MRAMs and applies the device-aware test (DAT) approach to develop accurate and realistic fault models presenting the way the defect manifests itself at the functional level. Two different test solutions are also covered in this paper. |
12:10 | Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices PRESENTER: Hans Martin von Staudt ABSTRACT. This paper demonstrates the principles of test generation for a simple Power Management Integrated Circuit (PMIC) using the analog extensions of the PDL of the P1687.2 standard. Retargetting from block to chip level and from there to an industrial ATE is demonstrated with serial communication via I²C. |
11:30 | Concurrent detection of failures in GPU control logic for reliable parallel computing PRESENTER: Hiroaki Itsuji ABSTRACT. This paper proposes a software-based method that concurrently detects GPU control-logic failures in running application while maintaining its throughput. The achieved throughput and detectable failures by the proposed approach are investigated with fault injection simulations. |
11:45 | Functional Criticality Classification of Structural Faults in AI Accelerators PRESENTER: Arjun Chaudhuri ABSTRACT. We analyze the functional criticality of structural faults in a systolic array-based AI inferencing accelerator. We show that a majority of pin-level faults are functionally benign. We present a two-tier machine-learning based method for evaluating the criticality of gate-level and pin-level faults and utilize generative adversarial networks for minimizing misclassifications. |
12:00 | Automated Assertion Generation from Natural Language Specifications PRESENTER: Steven Frederiksen ABSTRACT. We implement a natural language processing system that converts natural language specification sentences to a temporal logic inspired intermediate representation. Our implementation improves on the state of the art through the use of commonsense reasoning and frame semantics to allow for more sentence flexibility and future extensibility. |
12:15 | Machine Intelligence for Efficient Test Pattern Generation PRESENTER: Soham Roy ABSTRACT. An artificial neural network (ANN) is trained using ATPG trials, and when used in an ATPG tracing subroutine, ATPG requires fewer backtracks compared to conventional heuristics. |
11:30 | SPARTA: A Laser Probing Approach for Trojan Detection PRESENTER: Andrew Stern ABSTRACT. Integrated circuits fabricated at untrusted foundries are vulnerable to hardware Trojan insertion. SPARTA, a non-destructive laser probing approach, detects sequential Trojans by comparing clock activity within an IC with the original clock tree design. Using electro-optical frequency mapping and image processing techniques, all modifications on a 28nm device are identified. |
11:50 | A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic Gates PRESENTER: Domenic Forte ABSTRACT. We propose a novel weak Asynchronous RESet (ARES) PUF that exploits random start-up characteristics of Threshold M of N Null Conventional Logic (NCL) gates. Threshold 2 of 2 (TH22) and 4 of 4 (TH44) gates are used as test cases for evaluation and comparison validated by simulation and silicon results |
12:10 | Schmitt Trigger-Based Key Provisioning for Locking Analog/RF~Integrated~Circuits PRESENTER: Adriana C. Sanabria-Borbón ABSTRACT. We propose a Schmitt trigger-based key provisioning technique for Analog/RF performance locking. It enables the design of distinct user keys for individual chip instances and has a constant area overhead regardless of key size. |
13:00 | FAT: Training Neural Networks for Reliable Inference Under Hardware Faults PRESENTER: Giulio Gambardella ABSTRACT. Quantized neural networks (QNNs) deployment is being evaluated for safety-critical applications, thus requiring failure-free behaviour with faulty hardware. This work presents a methodology called FAT, which models error during training, making QNNs resilient to faults. Experiments show that by injecting faults during training, QNNs exhibits higher error tolerance during inference. |
13:20 | Online Fault Detection in ReRAM-Based Computing Systems by Monitoring Dynamic Power Consumption PRESENTER: Mengyun Liu ABSTRACT. We propose an online fault-detection method for ReRAM-based computing systems; the proposed method monitors the dynamic power consumption of ReRAM crossbars and determines the occurrence of faults when changepoints are detected. To estimate the percentage of faulty cells in ReRAM crossbars, we train a predictive model using machine-learning techniques. |
13:40 | Advanced Outlier Detection Using Unsupervised Learning for Screening Potential Customer Returns PRESENTER: Hanbin Hu ABSTRACT. To screen out rare outliers, several well-known unsupervised learning techniques are reviewed in this paper for multiple post-silicon testing datasets. We propose to train a robust unsupervised model by self-labeling the training data via a set of transformations and using the labeled data to train a classifier through supervised training. |
13:00 | Multi-Level Access Protection for Future IEEE P1687.1 IJTAG Networks PRESENTER: David Brauchler III ABSTRACT. New endeavors, such as IEEE P1687.1, aim to extend IJTAG access to ports other than JTAG, exposing a device to additional local and remote attackers. To protect devices, we propose a lightweight and low-cost protocol to authenticate users that offers solutions to access control, key distribution, and secrets stored on-chip. |
13:20 | Modeling Novel Non-JTAG IEEE 1687-Like Architectures PRESENTER: Michael Laisne ABSTRACT. This paper discusses how IP can be successfully controlled and observed by modelling the interfaces and controlling data flow using RVF (Relocatable Vector Format) and callbacks. The paper proposes an automated tool flow for retargeting the tests and provides example implementations on several specialized designs including I2C and TPSP. |
13:40 | Security Preserving Integration and Resynthesis of Reconfigurable Scan Networks PRESENTER: Natalia Lylina ABSTRACT. Reconfigurable scan networks (RSN) facilitate test and diagnosis but may introduce security violations due to side-channels. The presented re-synthesis approach considers all violations simultaneously, thereby obtaining a compliant RSN with a small number of changes. |
13:00 | Avionics Simulation Environment PRESENTER: Huseyin Sagirkaya ABSTRACT. Avionics systems tests are necessary to verify robustness of the design since avionics are necessarily safety critical equipment of an aircraft.Test environments includes hardware, software and wiring solutions. The functional behavior models of avionics in the laboratory environment leverage success of the integration process. |
13:15 | Data-driven fault model development for superconducting logic PRESENTER: Sandeep Gupta ABSTRACT. Superconductive technology recently receives high attention due to its ultra-high performance and ultra-low power consumption. Herein, we propose a data-driven method to build fault models specific for identifying SA0/SA1 faults and other superconductive-specific faults including overflow, pulse escape and pattern-sensitive. Our method successfully analyzes 99.38\% of 12,500 failing simulation results. |
13:30 | BISTLock: Efficient IP Piracy Protection using BIST PRESENTER: Siyuan Chen ABSTRACT. BISTLock, a logic-locking technique that utilizes built-in self-test (BIST) to isolate functional inputs in locked mode, is proposed to prevent IP piracy. It is shown to be secure against existing attacks and imposes minimal overhead. |
13:45 | Cross PUF Attacks on Arbiter-PUFs through their Power Side-Channel PRESENTER: Trevor Kroeger ABSTRACT. The security primitives known as PUFs are deployed to preserve security. Using Machine Learning techniques, we investigate the possibility of cross PUF attacks in which a particular PUF’s power fingerprints can be used to break another PUF’s security; including in the presence of noise, temperature variations and aging misalignments. |