ABSTRACT. We introduce an approach called Manifestation Learning to enable learning a wafer plot recognizer with one training sample. Using wafer probe test data from an automotive product line, this paper explains the learning approach, its feasibility and limitation.

ABSTRACT. This paper discovers a new unique defect: Synthetic Anti-Ferromagnet Flip (SAFF) in STT-MRAMs and applies the device-aware test (DAT) approach to develop accurate and realistic fault models presenting the way the defect manifests itself at the functional level. Two different test solutions are also covered in this paper.

ABSTRACT. This paper demonstrates the principles of test generation for a simple Power Management Integrated Circuit (PMIC) using the analog extensions of the PDL of the P1687.2 standard. Retargetting from block to chip level and from there to an industrial ATE is demonstrated with serial communication via I²C.

ABSTRACT. This paper proposes a software-based method that concurrently detects GPU control-logic failures in running application while maintaining its throughput. The achieved throughput and detectable failures by the proposed approach are investigated with fault injection simulations.

ABSTRACT. We analyze the functional criticality of structural faults in a systolic array-based AI inferencing accelerator. We show that a majority of pin-level faults are functionally benign. We present a two-tier machine-learning based method for evaluating the criticality of gate-level and pin-level faults and utilize generative adversarial networks for minimizing misclassifications.

ABSTRACT. We implement a natural language processing system that converts natural language specification sentences to a temporal logic inspired intermediate representation. Our implementation improves on the state of the art through the use of commonsense reasoning and frame semantics to allow for more sentence flexibility and future extensibility.

ABSTRACT. An artificial neural network (ANN) is trained using ATPG trials, and when used in an ATPG tracing subroutine, ATPG requires fewer backtracks compared to conventional heuristics.

ABSTRACT. Integrated circuits fabricated at untrusted foundries are vulnerable to hardware Trojan insertion. SPARTA, a non-destructive laser probing approach, detects sequential Trojans by comparing clock activity within an IC with the original clock tree design. Using electro-optical frequency mapping and image processing techniques, all modifications on a 28nm device are identified.

ABSTRACT. We propose a novel weak Asynchronous RESet (ARES) PUF that exploits random start-up characteristics of Threshold M of N Null Conventional Logic (NCL) gates. Threshold 2 of 2 (TH22) and 4 of 4 (TH44) gates are used as test cases for evaluation and comparison validated by simulation and silicon results

ABSTRACT. We propose a Schmitt trigger-based key provisioning technique for Analog/RF performance locking. It enables the design of distinct user keys for individual chip instances and has a constant area overhead regardless of key size.

ABSTRACT. As today's technologies continuously scale down, circuits become increasingly more vulnerable to radiation-induced soft errors in nanoscale VLSI technologies. This research work is focused on the development of design techniques for high-reliability modern VLSI technologies, applicable to large industrial circuits such as EUCLID space mission project. 

ABSTRACT. At the end of Silicon roadmap, keeping the leakage power in tolerable limit has become one of the biggest challenges. Several promising Non-Volatile Memories (NVMs) offering high-density, high speed, and competitive reliability/endurance while eliminating leakage issues are being investigated. On one hand, the above-desired properties make emerging NVM suitable candidates to assist or replace conventional memories in memory hierarchy as well as to infuse compute capability to eliminate Von-Neumann bottleneck. On the other hand, their unique characteristics such as high and asymmetric read/write current and persistence bring new threats to data security while compute-capability imposes new fundamentally different security challenges. Some of these memories are already deployed in full systems and as discrete chips. Therefore, it is utmost important to investigate the security issues of NVMs spanning the application space. This work makes pioneering contributions to this challenge through a holistic approach- from devices to circuits and systems using a combination of design and test methodologies to develop secure and resilient NVMs. The proposed attacks and countermeasures are validated on test boards using commercial NVM chips. Finally, this research has been tied to education by converting the test boards to design a modular and reproducible self-learning cybersecurity kit which has been piloted to train graduate and undergraduate students and K-12 teachers.

ABSTRACT. Quantized neural networks (QNNs) deployment is being evaluated for safety-critical applications, thus requiring failure-free behaviour with faulty hardware. This work presents a methodology called FAT, which models error during training, making QNNs resilient to faults. Experiments show that by injecting faults during training, QNNs exhibits higher error tolerance during inference.

ABSTRACT. We propose an online fault-detection method for ReRAM-based computing systems; the proposed method monitors the dynamic power consumption of ReRAM crossbars and determines the occurrence of faults when changepoints are detected. To estimate the percentage of faulty cells in ReRAM crossbars, we train a predictive model using machine-learning techniques.

ABSTRACT. To screen out rare outliers, several well-known unsupervised learning techniques are reviewed in this paper for multiple post-silicon testing datasets. We propose to train a robust unsupervised model by self-labeling the training data via a set of transformations and using the labeled data to train a classifier through supervised training.

ABSTRACT. New endeavors, such as IEEE P1687.1, aim to extend IJTAG access to ports other than JTAG, exposing a device to additional local and remote attackers. To protect devices, we propose a lightweight and low-cost protocol to authenticate users that offers solutions to access control, key distribution, and secrets stored on-chip.

ABSTRACT. This paper discusses how IP can be successfully controlled and observed by modelling the interfaces and controlling data flow using RVF (Relocatable Vector Format) and callbacks. The paper proposes an automated tool flow for retargeting the tests and provides example implementations on several specialized designs including I2C and TPSP.

ABSTRACT. Reconfigurable scan networks (RSN) facilitate test and diagnosis but may introduce security violations due to side-channels. The presented re-synthesis approach considers all violations simultaneously, thereby obtaining a compliant RSN with a small number of changes.

ABSTRACT. Avionics systems tests are necessary to verify robustness of the design since avionics are necessarily safety critical equipment of an aircraft.Test environments includes hardware, software and wiring solutions. The functional behavior models of avionics in the laboratory environment leverage success of the integration process.

ABSTRACT. Superconductive technology recently receives high attention due to its ultra-high performance and ultra-low power consumption. Herein, we propose a data-driven method to build fault models specific for identifying SA0/SA1 faults and other superconductive-specific faults including overflow, pulse escape and pattern-sensitive. Our method successfully analyzes 99.38\% of 12,500 failing simulation results.

ABSTRACT. BISTLock, a logic-locking technique that utilizes built-in self-test (BIST) to isolate functional inputs in locked mode, is proposed to prevent IP piracy. It is shown to be secure against existing attacks and imposes minimal overhead.

ABSTRACT. The security primitives known as PUFs are deployed to preserve security. Using Machine Learning techniques, we investigate the possibility of cross PUF attacks in which a particular PUF’s power fingerprints can be used to break another PUF’s security; including in the presence of noise, temperature variations and aging misalignments.

ABSTRACT. This work proposes models capable of analyzing logic gates susceptibility in different abstraction levels. Three methods are proposed based on transistor arrangement, stick diagram, and layout of the logic gates. The main goal of these methods is to insert the design information of logic gates on circuit reliability analysis.

ABSTRACT. Logic encryption is a popular Design-for-Security(DfS) solution that offers protection against the potential adversaries in the third-party fab labs and end-users. However, over the years, logic encryption has been a target of several attacks, especially Boolean satisfiability attacks. This paper exploits SAT attack's inability of deobfuscating sequential circuits as a defense against it. We propose several strategies capable of preventing the SAT attack by obfuscating the scan-based Design-for-Testability (DfT) infrastructure. Unlike the existing SAT-resilient schemes, the proposed techniques do not suffer from poor output corruption for wrong keys. This paper also offers various probable solutions for inserting the key-gates into the circuit that ensures protection against numerous other attacks, which exploit weak key-gate locations. Along with several gate-level obfuscation strategies, this paper also presents a Cellular Automata (CA) guided FSM obfuscation strategy to offer protection at a higher abstraction level, that is, RTL-level. For all the proposed schemes, rigorous security analysis against various attacks evaluates their strengths and limitations. Testability analysis also ensures that none of the proposed techniques hamper the basic testing properties of the ICs. We also present a CA-based FSM watermarking strategy that helps to detect potential theft of the designer's IP by any adversary.

ABSTRACT. A brief background in quantum computing is provided. Next, quantum error sources, fault models, and decoherence is discussed. Physical qubits, logical qubits, and quantum error correction is introduced to enhance the reliability of quantum computations.