ABSTRACT. A new machine learning based diagnosis method is proposed for improving both accuracy and resolution. Semi-supervised learning is deployed to use unlabeled data to augment model training. Also, a defect-level learning procedure uses characteristics from similar defects to further improve resolution. Experiments involving virtual and silicon datasets demonstrate significant improvements.

ABSTRACT. We propose a two-stage unsupervised root-cause analysis method. In Stage-I, a decision-tree model is trained to roughly cluster the data. In Stage-II, frequent-pattern mining is applied to precisely clustering so that each cluster represents only a few root causes. Industry cases demonstrate that the proposed approach outperforms the state-of-the-art method.

ABSTRACT. This paper presents a predictive analytics methodology using a continuing stream of anomaly data to tackle soft failure testing challenges, within a proposed silicon health prognosis framework. Statistical machine learning techniques are applied to infer failure evolution and the interference effects. Failure prediction results can be used for safety mitigation.

ABSTRACT. We propose a novel test generation for quantum circuits with low test cost. We use gradient descent to generate test patterns and chi-square test to make decision. Experimental results on IBM-Q system show that test costs of our proposed technique are orders of magnitude smaller than traditional random benchmark test.

ABSTRACT. We develop voltage-droop inducing functional test sequences targeting a wide range of power distribution network frequencies. We generate high and low power sequences that create symmetric and asymmetric sequences with hardware thread synchronization, pipeline delays and high power. We describe simulation and silicon results on a multi-threaded Qualcomm® Hexagon™ Processor.

ABSTRACT. The detection of subtle open and short defects within standard cell instances of a design often requires the use of multi-pattern tests. We propose an SAT-based scan test generation approach that comprehends interleaved launch-on-capture and launch-on-shift test application methods and demonstrates coverage improvements on benchmark circuits.

ABSTRACT. We first present a parallel testing scheme for testing Massive-MIMO transceiver arrays. Second, we propose a tuning scheme for the entire MIMO array using reinforcement learning. Yield improvement is demonstrated by simulation experiments.

ABSTRACT. Fault detection techniques reduce manufacturing cost by detecting faulty devices early in the test sequence. We propose a robust DfT technique to identify faulty op amps with 95% fault-coverage. Our method is digital thus circumventing expensive analog testing and can be used for power-on self-test and online health-monitoring after deployment.

ABSTRACT. This paper proposes a proactive method for mitigating emergent supply noises by introducing major-minor voltage regulator and lightweight current predictor. The method reduces the noise margin over 40 mV, also compensates the average voltage drop.

ABSTRACT. IJTAG requires 4 or 5 chip-level pins to drive a TAP controller. Not all our products have so many pins. In this paper we describe an IEEE P1687.1-based solution that drives a TAP from a 2-pin interface (a clock and a bidirectional dataIO), while maintaining a fully automated IJTAG flow.

ABSTRACT. Reduced validation plans for post-Silicon system margin validation still consume a significant amount of time and resources and are prone to subjective bias by the engineer comparing data against the base product. In this work, we present an efficient methodology based on Machine Learning to make an automatic risk assessment.

ABSTRACT. In HSSI, it can cause unexpected issues that cannot screen fail chips, even if one of the differential positive and negative signals is abnormal status. This paper proposes a cost effective test method can screen unexpected failure without measurement performance degradation assisted by simple circuit modification and additional test sequence.

ABSTRACT. Complex AI SoCs are integrating a large number of on-chip and off-chip memories, cores and interfaces (JTAG, 1500), as well as security measures and Design-For-Test structures. In this case-study paper, we demonstrate using IEEE 1687-2014 to integrate all these different components into a single, unifying methodology for fast silicon bring-up.

ABSTRACT. Traditional scan chain diagnosis methodology only identifies the failing scan flops in a device and doesn’t provide any information on the possible origin of failure. This paper proposes an approach to diagnose defects on clock and control signal lines which helps in improving chain diagnosis resolution and accuracy.

ABSTRACT. We propose a framework to co-optimize Yield along with PPA through synthesis-APR by learning from silicon to create predictive models. Simulation results across three different IPs show projected yield improvements of 11-17% with no area and performance / timing penalty but with static and dynamic power penalty.

ABSTRACT. Various test vehicles that aim to identify yield detractors are essential for maturing a new semiconductor process before high volume production. In this work, a third dimension is added to ensure efficient diagnosis of multiple defects within a high defect-density environment. Experiments demonstrate a significant improvement in perfect diagnoses.

ABSTRACT. In this paper, die-to-die testing scenario is considered, and a methodology is described for mitigating the effects of errors by using well-known Error Correcting Codes (ECC). An advanced ECC solution is then presented along with the infrastructure needed for effectively testing DRAMs, including soft errors and permanent faults.

ABSTRACT. We present a rapid min-MAX period monitoring scheme for PLLs. This new monitor is unique in this ability to process an input clock signal continuously, while recording both the minimum and maximum clock cycle times, so as to detect elusive online performance hazards.

ABSTRACT. In this paper, an accurate modeling approach to wideband power amplifiers with memory effects is presented. Modeling accuracy is improved by interpolating the measured data from a low sampling rate of 40 MHz to high data rates with different interpolation factors based on the propagation delay of the actual PA.

ABSTRACT. We present an analytical model for noise and gain imperfections in N-port network analyzers. Based on this model, we propose method for design optimization and compare the optimized analyzer with existing techniques.

ABSTRACT. The structural test of Intel server cores contains two unique properties: the latch-based scan structure with two-phase clocking scheme, and reusing of the functional clocks to keep the structural test performance similar to the functional. The special design rule checks (DRCs) and ATPG to handle Intel cores are presented.

ABSTRACT. This paper presents a novel tool to analyze the atypical Shmoo plot extracted from ATE using the loopback method, to prove the possibility of analyzing signals in a real test environment. The analysis tool produces an eye diagram from the extracted Shmoo plot to determine the signal quality status.

ABSTRACT. Techniques for sharing memory repair logic amongst memories are described. The techniques allow to reduce silicon area and loading time of repair information upon power up. The impact on yield is predicted using two different methods based on defect density and clustering or past silicon experience.

ABSTRACT. It is a challenge in MRAM to set an optimal reference value required to reliably differentiate “1” and “0” states. In this paper, we are suggesting a fully automated trim process to adjust reference to ideal value by leveraging existing MBIST (Memory Built-in Self-Test) resources.