ITC 2017: INTERNATIONAL TEST CONFERENCE 2017

A
Abotbol, Yehonatan	Advanced Functional Safety Mechanisms for Embedded Memories and IPs in Automotive SoCs
Agarwal, Nitin	Low-Cost Dynamic Error Detection in Linearity Testing of SAR ADCs
Aitken, Rob	Opportunities in Machine Learning and Test
Al-Ars, Zaid	Transition Fault Testing for Offline Adaptive Voltage Scaling
Ales, Mike	Functional vs. Defect-based Testing in Context of Analog Mixed-Signal Blocks
Amrutur, Bharadwaj	Safety Analysis for Integrated Circuits in the Context of Hybrid Systems
Amyeen, Enamul	Test Reordering for Improved Scan Chain Diagnosis Using an Enhanced Defect Diagnosis Procedure Diagnosis Part 2
Arai, Masayuki	Layout-aware 2-Step Window-based Pattern Reordering for Fast Bridge/Open Test Generation
Arnold, Keith	An Immodest Proposal to Bridge Test and Design Data for SoC and IP Yield
Au, Albert	Reducing Memory BIST ATE Test Time Through a Data-ready Observation Port modeled in IJTAG
B
Babighian, Pietro	Systematic Defect Detection Methodology for Volume Diagnosis: A Data Mining Perspective
Barman, Arun Kumar	An On-Chip ADC BIST Solution and the BIST-enabled Calibration Scheme
Beckler, Matthew	Evaluation of Transition-X Fault Model for On-Chip Diagnosis of Multiple Defects GPU-Accelerated Fault Dictionary Generation for the TRAX Fault Model
Benhassain, Ahmed	ITC-India Best Paper: Cognitive Approach to Support Dynamic Aging Compensation
Bergendal, Henrik	Technique to Test Hierarchical Designs with Multiple Design Levels
Bhagat, Hardik	Automatic Solution to Frame-Clock-Domain Groupings for Efficient At-Speed Structural Testing
Bhalerao, Sourabh	Single-Pin Test Control for Big A, little d Devices
Blanton, Ronald	Front-End Layout Reflection for Test Chip Design Diagnosis Part 1
Blanton, Shawn	Evaluation of Transition-X Fault Model for On-Chip Diagnosis of Multiple Defects GPU-Accelerated Fault Dictionary Generation for the TRAX Fault Model
Bodhe, Shraddha	Test Reordering for Improved Scan Chain Diagnosis Using an Enhanced Defect Diagnosis Procedure
Boschi, Gabriele	Advanced Functional Safety Mechanisms for Embedded Memories and IPs in Automotive SoCs
Bravaix, Alain	ITC-India Best Paper: Cognitive Approach to Support Dynamic Aging Compensation
Butler, Kenneth	Accurate ADC Testing with Significantly Relaxed Instrumentation Including Large Cumulative Jitter
C
Cacho, Florian	ITC-India Best Paper: Cognitive Approach to Support Dynamic Aging Compensation
Calhoun, Ben	Modeling Trans-Threshold Correlations for Reducing Functional Test Time in Ultra-Low-Power Systems
Carulli, John	Systematic Defect Detection Methodology for Volume Diagnosis: A Data Mining Perspective
Castillejo, Armand	Transition Fault Testing for Offline Adaptive Voltage Scaling
Chaganti, Shravan K	A Low-Cost Jitter Separation and ADC Spectral Testing Method Without Requiring Coherent Sampling
Chakrabarty, Krishnendu	Software-based Online Self-Testing of Network-on-Chip using Bounded Model Checking Run-Time Hardware Trojan Detection Using Performance Counters Securing Chip-Scale Microbiology and Biochemistry: Attacks and Countermeasures for Microfluidic Biochips
Chakrabarty, Krishnendu	Changepoint-based Anomaly Detection in a Core Router System Symbol-based Health-Status Analysis in a Core Router System
Chakravadhanula, Krishna	Advancing Test Compression to the Physical Dimension High-Throughput Multiple Device Diagnosis System
Chatterjee, Abhijit	Concurrent Built-in Test and Tuning of Beamforming MIMO Systems Using Learning-assisted Performance Optimization Advanced Test Methods for Mixed-Signal Circuits: Specification vs. Defect-based Test
Chatterjee, Procheta	Testing TSVs for Micro-void and Pinhole Defects Using OTA
Chen, An	Opportunities in Emerging Technologies for Hardware Security
Chen, Chi	Highly Reliable and Low-Cost Symbiotic IOT Devices and Systems
Chen, Degang	Accurate ADC Testing with Significantly Relaxed Instrumentation Including Large Cumulative Jitter A Low-Cost Jitter Separation and ADC Spectral Testing Method Without Requiring Coherent Sampling An On-Chip ADC BIST Solution and the BIST-enabled Calibration Scheme A Comparator-based Method for Decomposition of Random and Data-dependent Jitter in High-Speed Data Links
Chen, Degang	Accurate and Robust Spectral Testing with Relaxed Instrumentation Requirements
Chen, Jwu E	The Rainbow Transformed from a Set of Uniform-Defect Wafer Maps
Chen, Kaitlyn	Reducing Memory BIST ATE Test Time Through a Data-ready Observation Port modeled in IJTAG
Chen, Tao	An On-Chip ADC BIST Solution and the BIST-enabled Calibration Scheme
Chickermane, Vivek	Advancing Test Compression to the Physical Dimension
Chillarige, Sameer	High-Throughput Multiple Device Diagnosis System
Clark, Cj	IEEE 1149.10-2017: Mapping JTAG and Scan onto Serial I/O Such As SERDES and SPI
Contreras, Gustavo	Hardware Trojan Detection Through Information Flow Security Verification
Cote, Jf	Reducing Memory BIST ATE Test Time Through a Data-ready Observation Port modeled in IJTAG
Coyette, Anthony	Nonintrusive Detection of Defects in Mixed-Signal Integrated Circuits Using Light Activation
Cron, Adam	Interstitial DFT in SpeedCore™ A Method to Debug LBIST-Mode SSA/TF Silicon Failure Accurately Using Scan-Through-TAP (STT) Mode
Crouch, Al	Increasing IJTAG Bandwidth and Managing Security through Parallel Locking-SIBs Quo Vadis IJTAG.1? IEEE P1687.1: Accessing 1687 Networks via Non-TAP Interfaces
Cunningham, Paul	Advancing Test Compression to the Physical Dimension
D
Danialy, Givargis	Scaling Interactive IJTAG Debug Beyond the Desktop to ATE
Davidson, Scott	A Third of a Century of ATPG Benchmarks
Debaud, Philippe	Transition Fault Testing for Offline Adaptive Voltage Scaling
Devadze, Sergei	Marginal PCB Assembly Defect Detection on DDR3/4 Memory Bus Doing more with ITC'2016 IEEE 1687 Benchmarks: Ecosystem and PDLs
Devanathan, V.R.	A Hierarchical, Power-safe, Parallel Memory Self-Test Architecture for In-Field Test
Deyati, Sabyasachi	Concurrent Built-in Test and Tuning of Beamforming MIMO Systems Using Learning-assisted Performance Optimization
Ding, Xiaoan	Cross-Layer Refresh Mitigation for Efficient and Reliable DRAM Systems: A Comparative Study
Dobbelaere, Wim	Nonintrusive Detection of Defects in Mixed-Signal Integrated Circuits Using Light Activation Testing for Latent Defects in the Analog: Does the Spec. Matter?
Dong, Yan	Maximizing Scan Pin and Bandwidth Utilization with a Scan Routing Fabric
Du, Boyang	Fault-tolerant Electronic System Design
Duan, Yan	A Comparator-based Method for Decomposition of Random and Data-dependent Jitter in High-Speed Data Links
Dupaix, Brian	Test Opportunities to Reduce Time and Expertise Required to Assess (TERA) for Trust
Dworak, Jennifer	Increasing IJTAG Bandwidth and Managing Security through Parallel Locking-SIBs
E
Eason, Mark	Single-Pin Test Control for Big A, little d Devices
El Alam, Sam	Delay Fault Testing Using Cloud Testing Service
Elnaggar, Rana	Run-Time Hardware Trojan Detection Using Performance Counters
Emna, Farjallah	Improvement of the Tolerated Raw Bit-Error Rate in NAND Flash-based SSDs with the Help of Embedded Statistics
Engels, Daniel	Increasing IJTAG Bandwidth and Managing Security through Parallel Locking-SIBs
Esen, Vahap Baris	Nonintrusive Detection of Defects in Mixed-Signal Integrated Circuits Using Light Activation
F
Fan, Kevin	Multisite PMIC Fast Trimming with Pattern-based Search Function
Foley, David	Part 1: Demystifying Automotive Safety and Security for Semiconductor Developer
Forte, Domenic	Hardware Trojan Detection Through Information Flow Security Verification Upgrade/Downgrade: A Perspective on Challenges and Opportunities in Overcoming the Legacy System Issue
Foutz, Brian	Advancing Test Compression to the Physical Dimension
Frucht, Tal	Hierarchical Hybrid EDT-LBIST System
Fynan, Phillip	Front-End Layout Reflection for Test Chip Design
G
Gallagher, Patrick	BIST On-demand Using Distributed On-Chip Programmable Data Streams
Garrity, Doug	An On-Chip ADC BIST Solution and the BIST-enabled Calibration Scheme
Geiger, Randal	An On-Chip ADC BIST Solution and the BIST-enabled Calibration Scheme
Gielen, Georges	Nonintrusive Detection of Defects in Mixed-Signal Integrated Circuits Using Light Activation
Giles, Grady	Maximizing Scan Pin and Bandwidth Utilization with a Scan Routing Fabric
Giri, Chandan	Testing TSVs for Micro-void and Pinhole Defects Using OTA
Gu, Xinli	Changepoint-based Anomaly Detection in a Core Router System Symbol-based Health-Status Analysis in a Core Router System
Gupta, Saurabh	Increasing IJTAG Bandwidth and Managing Security through Parallel Locking-SIBs
H
Hamze, Kassem	Development of a Production-worthy ATE Test Screen for a Unique Device Fail Signature
Harutyunyan, Gurgen	Part 2: An Effective Functional Safety Solution for Automotive Systems-on-Chip
Harutyunyan, Gurgen	Advanced Functional Safety Mechanisms for Embedded Memories and IPs in Automotive SoCs
Hashizume, Masaki	Online Electrical Interconnect Test Method Utilizing IEEE 1149.1 Architecture
Holst, Stefan	Analysis and Mitigation of IR-Drop-Induced Scan Shift-Errors
Hong, Shuo-Lian	A Run-Pause-Resume Silicon Debug Technique with Cycle Granularity for Multiple Clock Domain Systems
Hsiao, Michael S.	RTL Functional Test Generation Using Factored Concolic Execution
Hu, Jiang	Thwarting Analog IC Piracy via Combinational Locking
Huang, Shi-Yu	A Cloud-based Methodology for Online PVTA Monitoring
Huang, Yu	The Emerging Applications of Machine Learning in Testing
Huard, Vincent	ITC-India Best Paper: Cognitive Approach to Support Dynamic Aging Compensation
Hung, Hsin-Wei	Highly Reliable and Low-Cost Symbiotic IOT Devices and Systems
Hutner, Marc	Scaling Interactive IJTAG Debug Beyond the Desktop to ATE Taming of the Shmoo
I
Ichiyama, Kiyotaka	A Jitter Separation and BER Estimation Method for Asymmetric Total Jitter Distributions
Inuyama, Shingo	Layout-aware 2-Step Window-based Pattern Reordering for Fast Bridge/Open Test Generation
Ishida, Masahiro	A Jitter Separation and BER Estimation Method for Asymmetric Total Jitter Distributions
Iwasaki, Kazuhiko	Layout-aware 2-Step Window-based Pattern Reordering for Fast Bridge/Open Test Generation
J
Jacobs, Todd	A VMIN Temperature Shift Outlier Screen for Cold Test Elimination
Jain, Abhishek	ITC-India Best Paper: Cognitive Approach to Support Dynamic Aging Compensation
Jain, Archana	Development of a Production-worthy ATE Test Screen for a Unique Device Fail Signature
Jain, Mayank	An On-Chip ADC BIST Solution and the BIST-enabled Calibration Scheme
Jain, Nimit	Low-Cost Dynamic Error Detection in Linearity Testing of SAR ADCs
Jayakumar, Greeshma	Automatic Solution to Frame-Clock-Domain Groupings for Efficient At-Speed Structural Testing
Jean-Marc, Armani	Improvement of the Tolerated Raw Bit-Error Rate in NAND Flash-based SSDs with the Help of Embedded Statistics
Jeong, Jae Woong	Built-in Self-Test for Stability Measurement of Low-Dropout Regulator
Jiang, Jianhui	Software-based Online Self-Testing of Network-on-Chip using Bounded Model Checking
Jin, Shi	Changepoint-based Anomaly Detection in a Core Router System Symbol-based Health-Status Analysis in a Core Router System
Jin, Xiankun	An On-Chip ADC BIST Solution and the BIST-enabled Calibration Scheme
Jung, Byunghoo	Concurrent Built-in Test and Tuning of Beamforming MIMO Systems Using Learning-assisted Performance Optimization
Jutman, Artur	Marginal PCB Assembly Defect Detection on DDR3/4 Memory Bus Doing more with ITC'2016 IEEE 1687 Benchmarks: Ecosystem and PDLs
K
Kajihara, Seiji	Analysis and Mitigation of IR-Drop-Induced Scan Shift-Errors
Kale, Sumant	A Hierarchical, Power-safe, Parallel Memory Self-Test Architecture for In-Field Test
Kapur, Rohit	Diagnosing Multiple Faulty Chains with Low-Pin Convolution Compressor Using Compressed Production Test Set
Kawagoe, Koshi	Analysis and Mitigation of IR-Drop-Induced Scan Shift-Errors
Keezer, David	Self-Test and Self-Repair Method for FPGAs
Keim, Martin	Quo Vadis IJTAG.1? Reducing Memory BIST ATE Test Time Through a Data-ready Observation Port modeled in IJTAG
Knowles, Matthew	Scaling Interactive IJTAG Debug Beyond the Desktop to ATE
Kochte, Michael A.	Analysis and Mitigation of IR-Drop-Induced Scan Shift-Errors
Kogan, Tal	Advanced Functional Safety Mechanisms for Embedded Memories and IPs in Automotive SoCs Hierarchical Hybrid EDT-LBIST System
Kramer, David	An On-Chip ADC BIST Solution and the BIST-enabled Calibration Scheme
Kroul, Itay	Advanced Functional Safety Mechanisms for Embedded Memories and IPs in Automotive SoCs
Kumar, Kuldip	Diagnosing Multiple Faulty Chains with Low-Pin Convolution Compressor Using Compressed Production Test Set
Kumar, Rishi	Diagnosing Multiple Faulty Chains with Low-Pin Convolution Compressor Using Compressed Production Test Set
Kumar, Vinay	A Method to Debug LBIST-Mode SSA/TF Silicon Failure Accurately Using Scan-Through-TAP (STT) Mode
Kundu, Subhadip	Diagnosing Multiple Faulty Chains with Low-Pin Convolution Compressor Using Compressed Production Test Set
L
Laisne, Michael	Single-Pin Test Control for Big A, little d Devices Quo Vadis IJTAG.1?
Lee, Kuen-Jong	A Run-Pause-Resume Silicon Debug Technique with Cycle Granularity for Multiple Clock Domain Systems
Lemanski, Mike	Development of a Production-worthy ATE Test Screen for a Unique Device Fail Signature
Levy, Sharon	A VMIN Temperature Shift Outlier Screen for Cold Test Elimination
Li, Guoliang	Maximizing Scan Pin and Bandwidth Utilization with a Scan Routing Fabric
Li, Huawei	Software-based Online Self-Testing of Network-on-Chip using Bounded Model Checking
Li, Mike Peng	A Comparator-based Method for Decomposition of Random and Data-dependent Jitter in High-Speed Data Links
Li, Yanjing	Cross-Layer Refresh Mitigation for Efficient and Reliable DRAM Systems: A Comparative Study
Liang, Hsing-Chung	The Rainbow Transformed from a Set of Uniform-Defect Wafer Maps
Liang, Xi	Cross-Layer Refresh Mitigation for Efficient and Reliable DRAM Systems: A Comparative Study
Lin, Bing-Yang	Highly Reliable and Low-Cost Symbiotic IOT Devices and Systems
Lin, Ching-Ju	The Rainbow Transformed from a Set of Uniform-Defect Wafer Maps
Lin, Xijiang	On Applying Scan-based Structural Test for Designs with Dual-Edge Triggered Flip-Flops
Liu, Zeye	Front-End Layout Reflection for Test Chip Design
Lu, Shyue-Kung	Online Electrical Interconnect Test Method Utilizing IEEE 1149.1 Architecture
Luigi, Dilillo	Improvement of the Tolerated Raw Bit-Error Rate in NAND Flash-based SSDs with the Help of Embedded Statistics
Lukas, Christopher	Modeling Trans-Threshold Correlations for Reducing Functional Test Time in Ultra-Low-Power Systems
M
Maheshwari, Naman	Frequency-Scaled Segmented (FSS) Scan Architecture for Optimized Scan-Shift Power and Faster Test Application Time
Makris, Yiorgos	Automated Die Inking: A Pattern Recognition-based Approach Enhanced Lithographic Hotspot Detection Through Design of Experiments
Malik, Anil	High-Throughput Multiple Device Diagnosis System
Marcelino, Seif	Improvement of the Tolerated Raw Bit-Error Rate in NAND Flash-based SSDs with the Help of Embedded Statistics
McDowall, Steven	Taming of the Shmoo
Meehl, Dale	Advancing Test Compression to the Physical Dimension
Meier, Reinhard	Reducing Memory BIST ATE Test Time Through a Data-ready Observation Port modeled in IJTAG
Meixner, Anne	An Immodest Proposal to Bridge Test and Design Data for SoC and IP Yield
Meyer, David	ITC-India Best Paper: Cognitive Approach to Support Dynamic Aging Compensation
Mhira, Souhir	ITC-India Best Paper: Cognitive Approach to Support Dynamic Aging Compensation
Milano, Louis	Advancing Test Compression to the Physical Dimension
Milewski, Sylwester	Full-Scan LBIST with Capture-per-Cycle Hybrid Test Points
Mittal, Rajesh	Frequency-Scaled Segmented (FSS) Scan Architecture for Optimized Scan-Shift Power and Faster Test Application Time
Miyase, Kohei	Analysis and Mitigation of IR-Drop-Induced Scan Shift-Errors
Morris, William	A VMIN Temperature Shift Outlier Screen for Cold Test Elimination
Mukherjee, Nilanjan	Full-Scan LBIST with Capture-per-Cycle Hybrid Test Points
Muldrey, Barry	Concurrent Built-in Test and Tuning of Beamforming MIMO Systems Using Learning-assisted Performance Optimization
N
Nadeau-Dostie, Benoit	Reducing Memory BIST ATE Test Time Through a Data-ready Observation Port modeled in IJTAG
Nahiyan, Adib	Hardware Trojan Detection Through Information Flow Security Verification
Narayanan, Prakash	Frequency-Scaled Segmented (FSS) Scan Architecture for Optimized Scan-Shift Power and Faster Test Application Time
Naresh, Nikita	Frequency-Scaled Segmented (FSS) Scan Architecture for Optimized Scan-Shift Power and Faster Test Application Time
Naudet, Sylvie	ITC-India Best Paper: Cognitive Approach to Support Dynamic Aging Compensation
Neerkundar, Vidya	Technique to Test Hierarchical Designs with Multiple Design Levels Productivity Gains with Hierarchical DFT Methodology for Physically Flat Design – A Case Study
Nero, Matthew	Some Considerations on Choosing an Outlier Method for Automotive Product Lines Kernel-based Clustering for Quality Improvement and Excursion Detection
O
Odintsov, Sergei	Marginal PCB Assembly Defect Detection on DDR3/4 Memory Bus
Ozev, Sule	Built-in Self-Test for Stability Measurement of Low-Dropout Regulator
P
Pan, Yan	Systematic Defect Detection Methodology for Volume Diagnosis: A Data Mining Perspective
Pandey, Sujay	DFM-aware Fault Model and ATPG for Intra-Cell and Inter-Cell Defects
Papameletis, Christos	Advancing Test Compression to the Physical Dimension
Parekhji, Rubin	Safety Analysis for Integrated Circuits in the Context of Hybrid Systems Low-Cost Dynamic Error Detection in Linearity Testing of SAR ADCs
Parthasarathy, Chittoor	ITC-India Best Paper: Cognitive Approach to Support Dynamic Aging Compensation
Phelps, Jonathan	Productivity Gains with Hierarchical DFT Methodology for Physically Flat Design – A Case Study
Pinto, Sonal	RTL Functional Test Generation Using Factored Concolic Execution
Pokharel, Mallika	Multicycle At-Speed Test
Pomeranz, Irith	Selecting Target Bridging Faults for Uniform Circuit Coverage POSTT: Path-oriented Static Test Compaction for Transition Faults in Scan Circuits Test Reordering for Improved Scan Chain Diagnosis Using an Enhanced Defect Diagnosis Procedure
Pradeep, Wilson	Frequency-Scaled Segmented (FSS) Scan Architecture for Optimized Scan-Shift Power and Faster Test Application Time
Prasanth, V	Safety Analysis for Integrated Circuits in the Context of Hybrid Systems Part 1: Demystifying Automotive Safety and Security for Semiconductor Developer
R
Rabenu, Amihay	Hierarchical Hybrid EDT-LBIST System
Rahaman, Hafizur	Testing TSVs for Micro-void and Pinhole Defects Using OTA
Rajanarayanan, Raghuraman	Interstitial DFT in SpeedCore™
Rajendran, Jeyavijayan	Supply-Chain Risks in Additive Manufacturing
Rajski, Janusz	Full-Scan LBIST with Capture-per-Cycle Hybrid Test Points
Ravi, Srivaths	Part 1: Demystifying Automotive Safety and Security for Semiconductor Developer
Rearick, Jeff	Use Models for Extending IEEE 1687 to Analog Test Maximizing Scan Pin and Bandwidth Utilization with a Scan Routing Fabric Doing more with ITC'2016 IEEE 1687 Benchmarks: Ecosystem and PDLs
Reiter, Heinz	Automated Die Inking: A Pattern Recognition-based Approach
Robertazzi, Raphael	Analytical Test of 3D Integrated Circuits
Romain, Luc	Reducing Memory BIST ATE Test Time Through a Data-ready Observation Port modeled in IJTAG
Roy, Surajit Kumar	Testing TSVs for Micro-void and Pinhole Defects Using OTA Design-for-Test and Test Optimisation for 3D SOCs
S
Sadi, Mehdi	Hardware Trojan Detection Through Information Flow Security Verification
Saluja, Kewal	Exploiting Path Delay Test Generation to Develop Better TDF Tests for Small Delay Defects
Sanabria-Borbon, Adriana	Thwarting Analog IC Piracy via Combinational Locking
Sanchez-Sinencio, Edgar	Thwarting Analog IC Piracy via Combinational Locking
Sanyal, Alodeep	DFM-aware Fault Model and ATPG for Intra-Cell and Inter-Cell Defects
Sarson, Peter	Automated Die Inking: A Pattern Recognition-based Approach Use Models for Extending IEEE 1687 to Analog Test A/MS Benchmark Circuits for Comparing Fault Simulation, DFT, and Test Generation Methods
Schaumont, Patrick	Fault Injection Attacks and their Mitigation in Embedded Processors
Scheurman, Micheal	Analytical Test of 3D Integrated Circuits
Schmaltz, Alan	DFM-aware Fault Model and ATPG for Intra-Cell and Inter-Cell Defects
Schneider, Eric	Analysis and Mitigation of IR-Drop-Induced Scan Shift-Errors
Schulze, John	Maximizing Scan Pin and Bandwidth Utilization with a Scan Routing Fabric
Scott, David	Advancing Test Compression to the Physical Dimension
Shaheen, Hanna	Advanced Functional Safety Mechanisms for Embedded Memories and IPs in Automotive SoCs
Shan, Chuanhe	Some Considerations on Choosing an Outlier Method for Automotive Product Lines Systematic Defect Detection Methodology for Volume Diagnosis: A Data Mining Perspective
Sharma, Ramesh	Reducing Memory BIST ATE Test Time Through a Data-ready Observation Port modeled in IJTAG
Shi, Congyin	Thwarting Analog IC Piracy via Combinational Locking
Shimanouchi, Masashi	A Comparator-based Method for Decomposition of Random and Data-dependent Jitter in High-Speed Data Links
Siatkowski, Sebastian	Some Considerations on Choosing an Outlier Method for Automotive Product Lines
Singh, Adit	Exploiting Path Delay Test Generation to Develop Better TDF Tests for Small Delay Defects
Singh, Sharjinder	High-Throughput Multiple Device Diagnosis System
Singh, Virendra	Exploiting Path Delay Test Generation to Develop Better TDF Tests for Small Delay Defects
Singhal, Ayush	DFM-aware Fault Model and ATPG for Intra-Cell and Inter-Cell Defects
Sinha, Arani	DFM-aware Fault Model and ATPG for Intra-Cell and Inter-Cell Defects
Sivaram, A.T	Delay Fault Testing Using Cloud Testing Service
Smith, Wesley	Taming of the Shmoo
Solecki, Jedrzej	Full-Scan LBIST with Capture-per-Cycle Hybrid Test Points
Srivastava, Ankush	Exploiting Path Delay Test Generation to Develop Better TDF Tests for Small Delay Defects
Sterpone, Luca	Fault-tolerant Electronic System Design
Subbarayan, Arul	Delay Fault Testing Using Cloud Testing Service
Sumikawa, Nik	Kernel-based Clustering for Quality Improvement and Excursion Detection
Sumikawa, Nikolas	Some Considerations on Choosing an Outlier Method for Automotive Product Lines
Sunter, Steve	IEEE Analog Test Coverage and Access: A New Study Group for Longstanding Problems A/MS Benchmark Circuits for Comparing Fault Simulation, DFT, and Test Generation Methods
Swenton, Joe	High-Throughput Multiple Device Diagnosis System
T
Tahoori, Mehdi	Run-Time Hardware Trojan Detection Using Performance Counters
Tehranipoor, Mark	Hardware Trojan Detection Through Information Flow Security Verification
Thinakaran, Rajavelu	Accurate ADC Testing with Significantly Relaxed Instrumentation Including Large Cumulative Jitter Low-Cost Dynamic Error Detection in Linearity Testing of SAR ADCs
Tian, Shurong	Analytical Test of 3D Integrated Circuits
Tseng, Shu-Mei	Highly Reliable and Low-Cost Symbiotic IOT Devices and Systems
Tsertov, Anton	Doing more with ITC'2016 IEEE 1687 Benchmarks: Ecosystem and PDLs
Tshagharyan, Grigor	Part 2: An Effective Functional Safety Solution for Automotive Systems-on-Chip
Tyberg, Christy	Analytical Test of 3D Integrated Circuits
Tyszer, Jerzy	Full-Scan LBIST with Capture-per-Cycle Hybrid Test Points
V
Valentin, Gherman	Improvement of the Tolerated Raw Bit-Error Rate in NAND Flash-based SSDs with the Help of Embedded Statistics
Vanhooren, Ronny	Nonintrusive Detection of Defects in Mixed-Signal Integrated Circuits Using Light Activation
Venkataraman, Srikanth	Test Reordering for Improved Scan Chain Diagnosis Using an Enhanced Defect Diagnosis Procedure Diagnosis Part 3
Vittal, Rahul	Hardware Trojan Detection Through Information Flow Security Verification
von Staudt, Hans Martin	Single-Pin Test Control for Big A, little d Devices
W
Walker, Duncan	Multicycle At-Speed Test
Wang, Jiafan	Thwarting Analog IC Piracy via Combinational Locking
Wang, Li-C.	Some Considerations on Choosing an Outlier Method for Automotive Product Lines Kernel-based Clustering for Quality Improvement and Excursion Detection Systematic Defect Detection Methodology for Volume Diagnosis: A Data Mining Perspective
Wen, Xiaoqing	Analysis and Mitigation of IR-Drop-Induced Scan Shift-Errors
Wilcox, Steev	Advancing Test Compression to the Physical Dimension
Winemberg, Leroy	Some Considerations on Choosing an Outlier Method for Automotive Product Lines Built-in Self-Test for Stability Measurement of Low-Dropout Regulator
Wingfield, James	Maximizing Scan Pin and Bandwidth Utilization with a Scan Routing Fabric
Wisnesky Ii, Carl	BIST On-demand Using Distributed On-Chip Programmable Data Streams
Wood, Tim	Maximizing Scan Pin and Bandwidth Utilization with a Scan Routing Fabric
Wordeman, Matt	Analytical Test of 3D Integrated Circuits
Wu, Cheng-Wen	Highly Reliable and Low-Cost Symbiotic IOT Devices and Systems
Wu, Hsinho	A Comparator-based Method for Decomposition of Random and Data-dependent Jitter in High-Speed Data Links
Wu, Ya-Syuan	The Rainbow Transformed from a Set of Uniform-Defect Wafer Maps
Wunderlich, Hans-Joachim	Analysis and Mitigation of IR-Drop-Induced Scan Shift-Errors
X
Xama, Nektar	Nonintrusive Detection of Defects in Mixed-Signal Integrated Circuits Using Light Activation
Xanthopoulos, Constantinos	Automated Die Inking: A Pattern Recognition-based Approach
Xu, Li	Accurate ADC Testing with Significantly Relaxed Instrumentation Including Large Cumulative Jitter A Low-Cost Jitter Separation and ADC Spectral Testing Method Without Requiring Coherent Sampling
Y
Yabui, Daisuke	Online Electrical Interconnect Test Method Utilizing IEEE 1149.1 Architecture
Yahya, Farah	Modeling Trans-Threshold Correlations for Reducing Functional Test Time in Ultra-Low-Power Systems
Yang, Jingchi	Self-Test and Self-Repair Method for FPGAs
Yasuji, Oyama	Delay Fault Testing Using Cloud Testing Service
Yilmaz, Ender	Built-in Self-Test for Stability Measurement of Low-Dropout Regulator
Yotsuyanagi, Hiroyuki	Online Electrical Interconnect Test Method Utilizing IEEE 1149.1 Architecture
Z
Zandrahimi, Mahroo	Transition Fault Testing for Offline Adaptive Voltage Scaling
Zawada, Justyna	Full-Scan LBIST with Capture-per-Cycle Hybrid Test Points
Zhang, Ying	Software-based Online Self-Testing of Network-on-Chip using Bounded Model Checking
Zhang, Zhaobo	Changepoint-based Anomaly Detection in a Core Router System Symbol-based Health-Status Analysis in a Core Router System
Zhuang, Yuming	Accurate ADC Testing with Significantly Relaxed Instrumentation Including Large Cumulative Jitter Accurate and Robust Spectral Testing with Relaxed Instrumentation Requirements
Zorian, Yervant	Advanced Functional Safety Mechanisms for Embedded Memories and IPs in Automotive SoCs Part 2: An Effective Functional Safety Solution for Automotive Systems-on-Chip

Disclaimer | Powered by EasyChair Smart Program