ABSTRACT. Evaluation and Optimization of the MOS Interface in SiC Power DMOSFETs

Medium-voltage SiC DMOSFETs are used in the rapidly-expanding EV market. Since 2017, Tesla has installed more than 150 million 650-V SiC DMOSFETs in 3.4 million EVs, and the worldwide EV market is projected to exceed 50 million vehicles per year by 2030 [1]. In the medium-voltage regime, SiC MOSFETs are limited primarily by their channel and substrate resistances. Substrate resistance can be reduced by mechanical thinning, but the channel resistance is fundamentally limited by the low mobility of electrons in the inversion layer. Encouraging results were recently reported using processes that minimize oxidation of SiC [2-5] so as to reduce the sub-oxide transition layer at the MOS interface. However, these studies were conducted on p-type epilayers with Al gate electrodes and a low- temperature (400°C) ohmic contact anneal, whereas power DMOSFETs are formed with polysilicon gates on ion-implanted base regions with a high-temperature (900-1000°C) ohmic contact anneal. The goal of this work is to evaluate and optimize these minimal-oxidation processes in MOS structures that are consistent with the fabrication of commercial power DMOSFETs, and to explore other important parameters such as oxide breakdown field, bias-temperature instability, and charge-to-breakdown.

We investigate four different oxide deposition techniques: thermal oxidation (the current standard), 750°C oxidation of an LPCVD silicon film ("poly-ox"), plasma-enhanced chemical vapor deposition (PECVD) at 400°C, and atomic layer deposition (ALD) at 250°C. We include a 1350°C pre-deposition anneal in H2 to reduce surface roughness and two post-deposition nitridation processes: a 1175°C NO anneal (the current standard), and a 1400°C pure-N2 anneal. Parameters measured include threshold voltage, oxide breakdown field, bias-temperature instability, charge-to-breakdown, interface state density, and channel mobility. Fig. 1 shows the process variations in our study, Fig. 2 illustrates the test structures, and Fig. 3 shows measurements of bias-temperature instability, oxide breakdown field, and field-effect mobility on a control sample oxidized at 1100°C in dry O2 and annealed at 1175°C in nitric oxide (NO). More data and a comparison of the various splits will be reported at the conference.

In the course of our experiments we became aware of potential errors in data interpretation in the C–ψS technique [6] for measuring interface state density. These errors [7,8] are of concern because they make comparison of reports from different groups problematic. A major source of error is determining the additive constant in the Berglund technique for surface potential, which can lead to substantial errors in interface state density, as illustrated in Fig. 4. Another error is the tendency to underestimate the true oxide capacitance using measurements in accumulation. This is caused by stretch-out of the CV curve due to interface states near the conduction band, making it difficult to reach full accumulation without damaging the oxide. Small errors in oxide capacitance can have a strong effect on the measured interface state density. We will briefly discuss these issues and suggest possible solutions [8] in our presentation.

This work is supported by grants from the PowerAmerica Institute at North Carolina State University, the II-VI Foundation, and ARPA-E.

ABSTRACT. Quantum technologies are moving swiftly from the laboratory to commercial applications. Quantum communication in particular has made great strides from research to deployment. However, the range and speed of such systems is limited because classical amplification of light signals cannot be used in a quantum channel. The performance of quantum communication links therefore requires a “quantum repeater”, a device which can store and relay fragile quantum information.

Vanadium in SiC has emerged as a strong candidate for the creation of such a device. It has a strong optical transition at a wavelength compatible with optical fiber networks, a long-lived electron spin which can act as a quantum memory, and is hosted in a material that is available with high quality at an industrial scale.

I will present the work performed in the EU project “QuanTELCO”, a collaboration aimed at developing control and interfacing methods for quantum repeaters based on vanadium. The project has resulted in remarkable advances in our understanding of this system, the control of its electron spin, and the development of photonic interfaces for quantum networks. Furthermore, we have shown that vanadium can be used as an extremely sensitive probe for the crystalline structure and electronic properties of the silicon carbide host.

ABSTRACT. An intense demand for highly efficient silicon carbide (SiC) power MOSFETs for use in electric vehicles and many other power conversion applications is driving a fast pace of development in the SiC industry. Yet the industry is currently grappling with the dual problems of an undersupply of SiC substrates to the market and a pressure for lower cost products from customers, particularly the automotive OEMs. Costs will be reduced as 200 mm substrates continue be adopted, as each fabrication run delivers 80 % more die than a 150 mm process. Furthermore, die yield as a percentage of the substrate will be driven up by fast-declining defect densities, and the compatibility of 200 mm substrates with modern, fully automated processes, removing more humans from the line. At the device level, the currency of cost reduction is specific on-resistance (R_ON,SP), the unit area resistivity of a device technology obtained by multiplying the MOSFET’s on-resistance (R_DS,ON) by its active area (A_ACTIVE). Reducing a MOSFET’s cell pitch or reducing any of the major resistances shown in Fig. 1, from the substrate (R_Subs), drift region (R_Drift), channel (R_Ch), JFET region (R_JFET) or drain contact (R_C), will reduce R_ON,SP, driving down the die size of a given product. The reduction in chip size delivers more devices per wafer, while a given micropipe or BPD density writes off a smaller percentage of devices, driving up die yield as a percentage. For Rohm, their transition from Gen 3 to Gen 4 in early 2022 resulted in a R_ON,SP reduction of as much as 40 % [1], which would reduce the active area (A_ACTIVE) of a given rated device by approximately 20 %, after thermal resistance is factored in [2]. In this presentation, we shall summarise the path already taken towards R_ON,SP reduction before we explore the technologies that look set to drive down SiC costs further, beginning with innovations at the substrate level, then for each of the device resistances. We shall then translate these innovations into a cost reduction roadmap.

ABSTRACT. Silicon Carbide (SiC) semiconductor technology can help maximize the efficiency of power systems and simultaneously reduce their size, weight, and cost as compared to legacy silicon-based systems. Demand and market size projections for SiC based systems continue to grow significantly. Recent forecasts predict that the SiC device market will grow beyond $6 billion by 2027 from $1 billion in 2021 [1]. A detailed understanding of the incorporation of dopant nitrogen atoms from N2 gas during physical vapor transport (PVT) growth of SiC is required to achieve high performance, low resistivity n+ SiC substrates for power device applications [2]. In this report we show how mapping of resistivity ρ in wafers can shed light on local growth conditions, which are very difficult-to-study in situ. We consider both thermodynamic quantities (absolute temperature T and partial pressure pN₂) and geometric characteristics of the growth surface relevant to growth kinetic parameters, namely atomic terrace width t and atomic step velocity v. Specifically, we show how an elevation map of the growth surface can be reconstructed from the spatially-resolved measurement of resistivity in a SiC wafer. Thermodynamics empowers us to form an equation describing equilibrium value of resistivity ρ∞ dependence on T and pN₂. From the equation of nitrogen incorporation into SiC:

N₂(g) ⇄ 2 N_sub_C (s), K = [N_sub_C]²/ pN₂

and the Van ‘t Hoff equation (ln K = ΔS/R – ΔH/RT ) we built the following ρ∞(T, pN₂) formula with two adjustable parameters A and B related to ΔS and ΔH of the above reaction respectively. Here we assume that resistivity is solely determined by the concentration of dissolved nitrogen atoms, i.e. ρ∞ ∝ 1/[N_sub_C]:

ln ρ∞ = ln A – 0.5 ln pN₂ – B/T

If only thermodynamics were needed to predict the local observed resistivity, we would not see a sharply defined zone of substantially lower resistivity in the basal plane (b.p.) facet area. This area is visible as an oval on the right side of the resistivity maps of wafers made from boules grown off-axis, as shown in Fig.1. Apparently, the local geometry of the growth front is affecting nitrogen incorporation in the growing crystal. If we assume that a faster moving atomic step is less careful about rejecting impurity atoms of nitrogen from being incorporated into the growing SiC crystal, we can infer the following. For a given normal growth front velocity, i.e. the rate of growth of SiC crystal perpendicular to the growth surface, more nitrogen gets incorporated in areas with lower inclination angle α and thus lower magnitude of gradient of elevation z , i.e. |∇z|, where z is measured with respect to the basal plane (as opposed to a plane perpendicular to the boule growth direction), since higher terrace width t in these areas makes the steps move faster in order to yield the same normal growth front velocity [3]. Fig. 2 shows a simulation of a resistivity map produced by analytically calculating |∇z| where the normal to the basal plane is tilted by an angle θ with respect to the growth axis. The growth front was simulated by a body of revolution around the growth axis with an even-powers-only polynomial radial profile. One can run this calculation backward and calculate the growth front shape z(x,y) from the deficit of resistivity Δρ = ρ∞ – ρ, where ρ is the observed local value of resistivity. Apparently, Δρ vanishes with increasing |∇z| as the velocity of the atomic steps vanishes, and the grown crystal approaches equilibrium. We can assume this trend is described by exponential decay equation Δρ = Δρ_sub_b.p. exp(–|∇z|/τ), with the maximum Δρ observed at the b.p. facet where |∇z| ≈ 0. To arrive at z(x,y) we have to integrate the predicted |∇z| = –τ ln(Δρ / Δρ_sub_b.p) over the area of the resistivity map. The decay constant τ can be refined by ensuring that the calculated z(x,y) for a wafer close to the dome end of a boule matches the observed z(x,y). The latter can be obtained, for example, by 3D scanning the as-grown boule’s dome and making sure the surface is aligned in space to place the b.p. facet at the z = 0 plane. Knowledge of the growth front shape obtained by the above analysis of wafers from different parts of a boule reveals fine details of the temperature distribution evolution during the growth and thus paves the way to perfecting this distribution at all stages of growth and thus improving the crystal quality.

[1] Power SiC 2022, Yole Development in Compound Semiconductor, News Article on 3/31/2022. [2] D.M. Hansen, G.Y. Chung, and M.J. Loboda, in Materials Science Forum, Vol. 527, p. 59-62. Trans Tech Publications Ltd. (2006). [3] K. Yokomoto, M. Yabu, T. Hashiguchi, N. Ohtani; J. Appl. Phys., 7 Oct 2020, 128 (13), p.

ABSTRACT. SiC material has attracted more and more attention over the years and led to significant industrial breakthrough in power electronic applications [1].

Wafer surface polishing and planarization are critical in order to obtain a good quality epi-ready surface which is mandatory for the development of power devices. Efficient SiC chemical-mechanical polishing (CMP) has been proven to be a key manufacturing step for SiC wafer mass-production. Indeed SiC Si-face removal rate is limited compared to other semiconductors due to its high hardness and chemical inertness [2]. Dedicated slurries with enhanced surface oxidation effect of Si-face are needed to improve both CMP throughput and surface quality required for industrial devices reliability, performance and cost effectiveness.

Years of experience on hard material polishing at Saint-Gobain Surface Conditioning has led to innovative solutions in CMP slurries for SiC, positioning us as a long lasting partner of the SiC industry [3]. Over the years the SiC product line was extended, now covering wafering from slicing to surface finishing & final cleaning. Our ambition for product development has always been to provide best-in-class products in terms of performance and cost of ownership. Saint-Gobain Surface Conditioning unique vertically integrated manufacturing organization combines formulation expertise and material science knowledge to transform raw materials into engineered abrasive nanoparticles and chemical compounds leading to our current SiC proprietary slurries offering.

Our product development objective is to deliver consistent performance with reliable supply and stringent quality control enabling state of the art surface solutions for the industry. Key requirements for Si-face SiC CMP high volume manufacturing includes to combine important removal rate efficiency, minimal surface impurities, Angstrom level roughness coupled with uniform and consistent results. ClasSiC 2000 series have been developed with this in mind to provide solutions for each different process manufacturing configurations in the SiC industry.

We will present in this study 6” SiC polishing results obtained with ClasSiC 2000 series slurries in CMP production ready conditions on an industrial single wafer polisher. Slurry related removal rate and surface roughness performance will be presented. We will discuss additionally of the influence of the polishing parameters on ClasSiC 2000 slurry behavior. (Fig.1)