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09:00-10:30 Session 6: Plenary I
Technology and Business Development of SiC MOSFET: Retrospect and Prospect

ABSTRACT. A new era in power electronics has been ushered in by the commercial introduction of silicon carbide (SiC) MOSFETs in a variety of power electronic systems, including power supplies, renewable energy, transportation, heating, robotics, and electric utility transmission/distribution. Among these, they are on the verge of being widely used in electric vehicles (EVs) and are attracting a great deal of attention. The utilization of SiC power devices in these systems can enable significant energy saving and the size reduction of such systems due to much lower power-loss devices compared to conventional silicon (Si) power devices. Such higher power conversion efficiency enables longer driving range or substantial reduction in battery capacity for the same driving range in EV powertrain applications. In December 2010, the first SiC MOSFETs were launched to the market by ROHM Co., Ltd. Since then, many companies have started mass production of SiC MOSFETs, and the market is expected to grow to about $5 billion by 2025. This paper reviews the progress of SiC MOSFET device technology [1-4] and its challenges for business development. It also discusses related technologies such as various simulation technologies and module technologies, which are essential for further growth. In addition, it should be noted that scientific understanding, especially in the areas of defect behavior in the SiC epi layer and SiC substrate, threshold voltage instability, channel electron mobility behavior, and high integrity of the gate insulator growth process, would be increasingly important and necessary for the further development of SiC power devices.

Accelerating SiC Mass Commercialization
11:00-12:30 Session 7A: Devices 1: Novel devices and integration concepts
Real-Time UV Imaging using 4H-SiC 64 Pixels CMOS Image Sensors
500°C Operation of 4H-SiC SRAM
Concept and technology for full monolithic MOSFET and JBS vertical integration in multi-terminal 4H-SiC power converters
Normally-off 1200V Silicon Carbide JFET Diode with Low VF
11:00-12:30 Session 7B: Defects 1: Extended defects in SiC materials I
Location: Ulisse
Study on quantification of correlation between current density and UV irradiation intensity, leading to bar shaped 1SSF expansion
3-dimensional observation of dislocations in 4H-SiC using focused light birefringence
Wafer-level identification of stacking faults in 4H-SiC epilayers and accurate analysis of overlaid complex structures by high-speed photoluminescence and HR-STEM
PRESENTER: Moonkyong Na
Estimation of Influence on Carbon Vacancy regarding 4H-SiC Substrate grown by HTCVD method
14:00-15:20 Session 8: Plenary II
The golden age of SiC: Turning the potential of SiC into opportunities for energy conversion applications

ABSTRACT. Silicon carbide (SiC) has emerged as a viable alternative to silicon in power electronics due to its superior physical properties. With the increasing demand for efficient power electronics and conversion systems driven by the need to combat climate change, ICSCRM 2023 provides an excellent opportunity to focus on some of the aspects SiC technology. This paper discusses the challenges faced by device and package designers involving SiC technology, including the need for improved performance, scalability, reliability, and volume manufacturing to meet market demand. The advantages of planar SiC MOSFET technology over trench technology are highlighted and the optimization of the MOSFET intrinsic body diode and package materials are discussed. The transition to 200mm wafers and strategies to minimize the effects of low doping in SiC monocrystals are also presented, along with the potential for bipolar degradation and the need to reduce basal plane dislocations in SiC wafers.

SmartSiC™: a greener, faster and better technology for SiC

ABSTRACT. For 30 years, Soitec has been designing and manufacturing semiconductor engineered substrates. Soitec is addressing markets for three key megatrends such as 5G/6G, Electrical Vehicles (EVs) and Artificial Intelligence. We foresee EVs to become a significant new growth driver by capturing the two main trends in this market: the Digitalization of the car, and the Electrification of mobility.

By 2030, more than 45 million of cars sold will be EVs. Thanks to its performances, by 2025 it is expected that more than 50% of EVs will use Silicon Carbide (SiC) in their power electronics systems. Silicon Carbide brings several advantages over silicon when it comes to power electronic devices. These include a higher breakdown voltage, higher operating temperature, and higher thermal conductivity that helped imposing SiC as preferred option for inverter for leading EVs. Although amazing progress has been demonstrated past 15 years regarding silicon carbide substrate properties and processing, major limitations remain for a straightforward transition to large volume.

Smart-Cut™ applied to SiC, generating SmartSiC™ engineered substrates aims to accelerate silicon carbide adoption and brings best of SiC by combining high conductivity ultra-flat pSiC and high quality layer of mSiC for device. Performance wise, this unique vertical structure allows a boost in electrical performance and efficiency of power devices such as MOSFETs and diodes. It brings as well flatness and process simplifications advantages that will be discussed. On sustainability front, SmartSiC™ is a greener route to volume by targeting CO2 footprint equivalent to silicon wafers, mostly thru vast reuse of donor wafers, obtained at very high thermal budget, for more than 10 SmartSiC wafers for each donor. This route is also lowering risk lowering capex intensity and speeding 200mm SiC wafers introduction by two years. All these performances had been demonstrated for manufacturing and triggered the decision for a new fab in Soitec with first production in September 2023. .

The presentation at ISCRM 2023 Naples opening session will describe the SmartSiC process and latest results on wafers and devices and how SmartSiC™ is enabling major impacts on SiC business.

16:00-18:00 Session 10A: Poster Session Mo.A
Location: Nettuno
SiC crystal growth behavior via physical vapor transport method dependent on mass transport of sublimed vapor in the SiC source (invited poster)
Peculiar behaviors of the step-terrace structure formed by single bilayer steps on the (000−1) surface
Quality improvement of SiC substrate surface with using non-abrasive CMP slurry
Evidence of twin mediated growth in the CVD of <110> oriented polycrystalline SiC
Effect of the Source Composition on PVT SiC in Graphite and TaC Coated Crucibles
Growth of 6 inches V-doped semi-insulating SiC single crystals using V-doped SiC powder as a source via PVT method
Design optimization of insulating materials for 4H-SiC crystal Ingot growth
Dislocation behaviors during the initial stage of physical vapor transport growth of 4H-SiC on an off-oriented seed crystal
Temperature-Dependent Hall Coefficient in Band Conduction Region for Heavily Al-Doped 4H-SiC
Low-resistivity (1mOhm-cm) 3C-SiC grown by hot-filament CVD
Channeling, Lateral Range and Diffusion Simulation Capabilities for Ion Implantation Recipe Design
A Meister solution for optimized grinding of laser split silicon carbide surfaces

ABSTRACT. The growing demand for silicon carbide (SiC) epitaxy-ready wafers outstrips the current manufacturing capacity. As the cost of prime wafers is mainly driven by the substrate, manufacturers strive to minimize material loss during production. Laser splitting of SiC boules into wafers has emerged as an effective solution for reducing kerf loss. However, the resulting surface morphology, characterized by parallel peaks and valleys along the laser ablation lines and striations from crack propagation, presents challenges for subsequent grinding processes, with a total thickness variation (TTV) of 20 to 60 µm. Meister Abrasives AG has developed customized CleanCut grinding wheel, which is based on their proven Ceramet hybrid vitrified-metal bond technology for rough grinding, with low wheel wear rates. Coupled with the company's UltraFine 6 (UF6) wheel, which uses ultra-fine vitrified bond grinding technology to achieve CMP-ready surfaces on pre-ground substrates, the overall throughput of the grinding and polishing process can be significantly increased. In a study comparing laser-split SiC to diamond- or slurry-based wire-wafered substrates, Meister found similar results in terms of surface roughness, wheel wear ratio, and low grinding force, with stress on the wafer minimized during thinning. This innovative combination of CleanCut DIA and UF6 DIA technologies provides a cost-effective and fast solution for SiC manufacturers to produce epitaxy-ready prime wafers with polish-grade surfaces, meeting the growing demand for high-quality SiC substrates in the semiconductor industry.

Submicron Hyperion Diamond for Silicon Carbide Wafer Polishing

ABSTRACT. Submicron Hyperion Diamond for Silicon Carbide Wafer Polishing Timothy Dumm1, Jacob Palmer1, Thomas Draskovic1 1) Hyperion Materials & Technologies Inc., 6325 Huntley Road, Columbus, OH USA E-mail: timothy.dumm@hyperionmt.com (corresponding author)

Due to the extreme hardness of silicon carbide, diamond is a natural choice for processing through the various steps needed to achieve a wafer that is epi-ready. Hyperion diamond is a unique, patented[1] diamond powder that was developed specifically for lapping and polishing hard materials like sapphire and silicon carbide. As shown in Fig. 1., this diamond is manufactured such that each particle contains micro spikes that enhance the material removal rate and surface finish in a lapping or polishing process. In the past 10 years, it has become an industry standard for lapping silicon carbide surfaces down to the CMP step. As shown in Fig. 2., unlike regular monocrystalline or polycrystalline diamond, the Hyperion diamond increases material removal rate while maintaining or even reducing the surface roughness of the wafer surface. Recently, Hyperion diamond was produced in sizes below 1 micron mean size. This diamond was incorporated into a polishing slurry and tested on a Revasum 6EZ polisher. Results from these tests show that the diamond slurry using Hyperion diamond achieved material removal rates are equal or higher than chemistry-based slurries and surface finishes are close to epi-ready. A unique attribute of the diamond polish is that it uses a slurry vehicle which is comprised of very benign, environmentally friendly chemicals having a neutral pH. The Hyperion diamond polish can alternatively be used to close the gap between a final lapping or fine grinding step so that the use of chemical-based CMP slurries is minimized. For example, a lapped 6-inch silicon carbide wafer having a surface roughness value of 1.1nm was polished with a 0.5um Hyperion diamond slurry using a single wafer CMP polishing machine. In a 15 minute polishing cycle, 1.7um of thickness was removed from the Si side and the resulting surface roughness was 0.3nm based on AFM analysis. Fig 3 shows the images of pre and post polished wafer surfaces using a 3D optical surface profilometer. We continue to develop the diamond polish to further extend its ability to rapidly reduce surface roughness and eliminate subsurface damage from prior mechanical processes. We expect that there will be significant value in utilizing such a product within existing processes.

[1] US Patents 9,982,176; 9,758,708; 9,382,463 and 8,927,101.

HYPREZ Wafering Solutions: A Novel Approach for Grinding to Clean CMP Solution

ABSTRACT. Engis, a world leader in superabrasive finishing systems, is offering a complete HYPREZ® wafering solution to the emerging silicon carbide industry. Engis builds and services machines to be used with HYPREZ accessories and consumables, which provide a novel approach to prepare 150mm epi-ready SiC wafers with minimal subsurface grinding damage and faster planarization by CMP. Wafering solutions in SiC have been developed by Engis for grinding and polishing SiC wafers sliced by diamond slurry wire saw, laser split, and diamond embedded wire saw. Overall processing times are reduced by minimizing TTV and surface roughness of wafers between grinding and polishing. Engis CMP solutions take advantage of reduced polishing times to obtain ideal surfaces with subnanometer roughness and low material removal. HYPREZ coarse and fine HYGRIND wheels were evaluated by grinding 6” SiC wafers at various conditions with resulting performance shown in Table I. Wheel performance was compared by measuring material removed on the wafer and material lost from wheel teeth (wafer wear/wheel wear). Grinding load was observed as a percentage of the rated spindle power generating torque as shown in Fig. 1. SiC process of record coarse wheels have grind ratios around 2-3 with medium grind load (~20%) and fine wheels have grind ratios around 0.1-0.3 with low grind loads (~12%). HYGRIND wheels achieved low wafer thickness variation, <1um TTV as shown by Fig. 2, and low surface roughness, 1-2nm Ra as shown by Fig. 3, while maintaining average grind ratios of 3 and 0.5 for coarse and fine wheels, respectively. It was determined that wheels with stronger bonding had better performance with higher power grinding parameters, such as higher feed rate and lower wheel speed. This is contrasted by softer wheels, which performed better at lower feed rates and higher speeds. It was also determined that tooth area has a large effect on grinding performance and is directly linked to maximum grind ratio. Incoming wafer surfaces were also seen to have a large effect on grinding performance between smoother and rough surfaces, but HYGRIND wheels maintained consistent performance across all incoming wafer conditions. Grinding throughput is further increased by automated cassette-to-cassette handling of the Engis multi-spindle grinding system (HYPREZ EAG Model, Fig. 4). Overall, HYGRIND wheels demonstrated similar performance compared to benchmark wheels offered with Engis grinding systems. The HYPREZ EJW-610 CMP machine with Engis PA2014 slurry in Fig. 5 were used to obtain ideal epi-ready surfaces from SiC wafers thinned by HYGRIND fine wheels. SiC wafers with <1um TTV, 1-2nm Ra, and <50nm Rt were polished to a surface roughness <0.5nm Ra, as shown in Fig. 6, within 1 hour after removing only 0.7 um material by CMP process. The benchmark processing time by HYPREZ CMP planarization to remove 1-5um of subsurface damage from process of record fine grinding has been at least 3 hours of polishing. Grinding with HYGRIND fine wheels effectively reduced CMP planarization time because of the highly uniform surface with minimal deep scratching and low flatness. The novelty of Engis SiC processing is this ‘Grind-to-CMP’ capability of HYPREZ wafering solutions.

Comparative optical metrologies of implanted SiC wafers
Keypoints for the development of polycrystalline SiC as quasi-substrate for the fabrication of SiC wafers
High-temperature α-spectroscopy with 4H-SiC based sensors
Vertical current transport in monolayer MoS2 heterojunctions with 4H-SiC fabricated by sulfurization of ultra-thin MoOx films
16:00-18:00 Session 10B: Poster Session Mo.B
Location: Foyer Sirene
Complementary two dimensional carrier profiles of 4H-SiC MOSFETs by Scanning Spreading Resistance Microscopy and Scanning Capacitance Microscopy Patrick Fiorenza (invited poster)
Carrier transport mechanism of NiAl contacts on n-type 4H-SiC
Suppressing leakage currents in 3C-SiC/Si devices through the fabrication of suspended structures
Fast Estimation of the Lateral Fidelity of Ion Implantation in 4H-SiC through Calibration to JFET Transfer Characteristics in TCAD
Development of silicide formation process on p-type SiC by laser annealing
Effect of substrate heating on low contact-resistance formation by excimer laser doping for 4H-SiC
Bilayer metal oxide high-κ dielectrics for high-performance SiC power MOSFETs
Lift-Off Process for Patterning of Sputter-Deposited Thick Metal Stacks Suitable for High Temperature Applications on 4H-SiC
Influence of Active Area Etching Method on the Integrity of Gate Oxide on 4H-SiC
The Effect of Nitrogen Plasma Treatment Process on Ohmic Contact Formation to n-type 4H-SiC
Improving HfO2 thick films for SiC Power Devices by Si, Y and La Doping
Spectroscopic investigation of the secondary electron doping contrast on 4H-SiC
Electrical characterization of 200 mm 4H-SiC-on-polycristalline SiC wafers bonding interface
Fabrication of SiO2/4H-SiC MOS devices by sputter deposition of SiO2 followed by high-temperature CO2-post deposition annealing
Influence of Carbon Capping Materials during High Temperature Annealing on Surface, Defects and Dopant Profile in SiC
Demonstrating SiC in Situ Rounded Trench Processing Technologies for Future Power Trench MOSFET Applications
Negative gate voltage Idss behavior of ion implantation effect on epi SF defects with high voltage SIC MOSFET
Hydrogen pressure dependence of step height on vicinal carbon-face 4H-SiC during in-situ etching
First demonstration of SiC transistor utilizing 2D electron gas in 3C/4H-SiC heterostructure
SiC MOSFET gate oxide quality improvement method in furnace thermal oxidation with lower pressure control
16:00-18:00 Session 10C: Poster Session Mo.C
Location: Foyer Ulisse
Trap distribution in 4H-SiC MOSFETs analyzed by a 3-level charge pumping technique (invited poster)
Threshold voltage variation of SiC trench MOSFETs during TDDB stress
Investigation of electrical performance degradation of 4H-SiC MOSFETs under high temperature and high gate bias stresses
Influence of material properties on ruggedness evaluation of package architectures for SiC power devices
Excellent Avalanche Capability in SiC Power Device With Positively Beveled Mesa Termination
Investigation of threshold voltage instability and bipolar degradation in 3.3 kV SiC-MOSFETs with embedded SBD and intrinsic body diode
Body diode reliability of 4H-SiC MOSFETs as a function of epitaxial process parameters
Avalanche ruggedness of 1.7 kV SiC MOSFETs for auxiliary power supply in motor drives
Failure-to-Open Short Circuit Failure Mode of SiC Power MOSFETs: 2-D Electro-Thermo-Mechanical Modeling
Gate Oxide Instability in Commercial SiC MOSFETs under Oxide Screening Electric Fields Stress
Threshold voltage drift mechanism in SiC MOSFETs under AC gate stress
Power cycling of SiC MOSFETs packaged in different module’s solutions
Analysis of TID effects through gamma-ray irradiation experiments
Total ionizing dose (TID) Effects on the 1.2 kV SiC MOSFETs under Proton Irradiation
16:01-18:00 Session 11: Poster Session Mo.D
Location: Le Ginestre
Density control of single-photon sources formed at a SiO2/SiC interface (invited poster)
SiC Sample-and-Hold Circuit for SiC CMOS Image Sensors
Gate resistance integration in SiC MOSFETs: performance simulations under different implementation methods
A Physics-based Model for Inversion Layer Mobility in SiC MOSFETs
A 1200V Low Forward Voltage Drop Silicon Carbide Diode with Trenched Junction-Pinched Barrier Rectifier Structure (TBR)
Investigation of Parasitic PN Junction Turn-on in 4H-SiC TMBS with P-Shielding
Effect evaluation and modeling of p-type contact resistance of SiC MOSFET on switching characteristics
Stress fields distribution and simulation in 3C-SiC resonators.
Junction-Controlled-Diode-Embedded SiC-MOSFET for Improving Third Quadrant and Turn-on Characteristics
Study of parasitic effects in SiC MOSFET switching circuits by comparing measurement and simulation
A Geometry-Scalable Physically-Based SPICE Compact Model for SiC MPS Diodes Including the Snapback Mechanism
Frequency investigation of SiC MOSFETs C-V curves with biased Drain
Device modeling of 4H-SiC pin-photodiodes with shallow implanted Al-emitters for VUV sensor applications
Single event effects in 3.3 kV 4H-SiC MOSFETs due to MeV ion impact
Accuracy of Split C-V Characterization of SiC Power MOSFETs
Fabrication of 6500 V SiC MOSFETs and Applications in the Solid State Transformer
High Accuracy SPICE Model of 3rd Quadrant Behavior on Both Planar and Trench SiC Power MOSFET
Comparative Performance Evaluation of High-Voltage Bidirectional, Conventional and Superjunction Planar DMOSFETs in 4H-SiC
Coupled non-destructive methods, Kelvin Force Probe microscopy and µ-Raman to characterize doping in 4H-SiC power devices
A Voltage Adjustable Diode Integrated SiC Trench MOSFET With Barrier Control Gate
18:00-18:30 Session 12: Industrial Keynote
Driving Clean Energy Adoption and Sustainability: The Pivotal Role of Silicon Carbide Power Electronics Technology

ABSTRACT. With the pressing challenges of climate change, pollution, and resource depletion, there is a growing sense of urgency to address the underlying issues. Silicon carbide (SiC), a wide-bandgap semiconductor material, presents unique properties that make it a crucial enabler for the transition to clean energy sources, enhancing energy efficiency and reducing greenhouse gas emissions. This keynote explores the pivotal role of the semiconductor technologies industry in driving this transformative change, focusing specifically on SiC. The presentation begins by examining the technology and industry status of SiC, highlighting its contributions to clean energy and sustainability across product, application, and system levels. Furthermore, the keynote reviews various approaches to achieve carbon neutrality in the industry, including energy efficiency measures, process and supply chain optimization, circular economy practices, and employee engagement. Concluding the keynote, the future outlook and emerging trends of SiC technology are outlined, underscoring its essential role in driving the adoption of clean energy and contributing to a more sustainable future. Overall, this keynote aims to inspire and inform attendees about industry’s commitment to utilizing SiC materials and power electronics for a greener and more sustainable world.

18:30-20:30 Session 13A: Industrial Session A
LPE + ASM – Combination powers SiC growth

ABSTRACT. Abstract

Title: LPE + ASM – Combination powers SiC growth

Presenter: Silvio Preti

LPE was acquired by ASM in 2022, bringing together two long-time epitaxy equipment suppliers with powerful synergies to address the fast growing SiC devices market and the emerging 200mm SiC wafer industry inflection.

Combining LPE’s SiC epitaxy technology with ASM’s expertise in silicon epitaxy for power devices will improve on-wafer performance, tool productivity and total cost of ownership, driving customer roadmaps towards more efficient next-generation power electronics.

Leveraging ASM global operations including sales, product development, manufacturing & supply chain capability will accelerate value creation for SiC device manufacturers. 

Our 150 and 200mm SiC epitaxy tools for volume production are based on a single wafer crossflow hot wall reaction chamber architecture and deliver excellent film quality, uniformity, and repeatability. 

SiC epi fabrication – 150 & 200 mm G10-SiC epitaxy platform
Trace element analysis of purified graphite material

ABSTRACT. Graphite and carbon materials, such as synthetic graphite, graphite felt, or carbon fiber composite materials are key enablers to produce semiconductor materials. The unique combination of adjustable physical properties makes this class of material unreplaceable in that industry. Beside the outstanding physical properties low concentrations of metallic and non-metallic impurities in the ppb-range is of outmost importance. With ICP-OES (Inductively Coupled Plasma – Optical Emission Spectroscopy) a powerful analytical instrument is available to detect such impurities at low concentrations. Yet, methodology of mobilization of impurities and their transfer into the plasma requires special sample preparation procedures and techniques.

4H-SiC substrates using the Fast Sublimation Growth Process

ABSTRACT. Silicon Carbide has been adopted by the power semiconductor industry in the last few years. Nowadays MOSFETs and other power devices fabricated on SiC substrates are widely used in many applications such as Electric Vehicles (EV), power plants, transportation, etc. However, while SiC devices are on the forefront of performance, wafer defects are still of great concern. Even though the quality of SiC wafers has been significantly improved, SiC devices are still limited by defects to small footprint, low voltage, and low current densities to comply with demands for high reliability and yields.

KISAB has introduced an innovative SiC growth technology to the industry which can produce silicon carbide substrates with reduced defect densities for use in higher voltage class power devices. The growth method so called Fast Sublimation Growth Process Monocrystalline (FSGP-M) provides perfectly uniform temperatures across the seed and the source material, and uniform supply of growth species. These two growth conditions ensure an even growth rate over the whole substrate surface during the entire growth process. As a result, basal plane dislocations are eliminated through the entire crystal without increasing the threading dislocation density.

The company has developed and taken into operation a highly automated production system for the growth of 150mm and 200mm 4H-SiC substrates. The application of FSGP-M in SiC crystal growth substantially reduces the carbon footprint by using less energy and consumables. Currently, 150mm materials are produced and shipped to several power device manufacturers for device fabrication evaluation, while the 200mm crystals are in the development stage and will be released to the market by the end of 2023.

Screen UV Laser Anneal Technology for next generation of SiC Devices

ABSTRACT. Ultimate control of thermal budget, both in time and in depth, is made possible by combining surface-selective anneal enabled by UV laser, and control of heat diffusion enabled by tuning the irradiation duration in the µs timescale.

Such technology opens a new space between sub-melting standard techniques, such as furnace anneal or flash lamps anneal, and nanosecond melting UV laser anneal.

SiC power devices have emerged as a breakthrough technology for a wide range of applications, from inverter for automotive to fast charging stations. Fabricating low resistance ohmic contact with good reliability and mechanical performances is still challenging, and UV µs LA is shown to lead to uniform and continuous formation of NixSiy films. Finally, crystal curing and dopant activation after ion implantation followed by laser anneal, in a cost-effective and protective capping-less integration, is a major step forward and opens new routes for SiC power MOSFETs.

PRESENTER: Poshun Chiu

ABSTRACT. The paper presents the potential direction of leading automotive OEMs development of next generation of SiC-based powertrain, along with the innovation of 8-inch platform and massive wafer capacity expansion worldwide. The two major factors could lead to the reformation of SiC eco-system. INTRODUCTION As the SiC device market surpassed $1 billion in 2022, the automotive industry plays a significant role in driving SiC device market growth, while adoption in various applications continues to accelerate. Leading automotive OEMs have announced their objective to implement new SiC solutions, which will have a major impact on SiC device demand. On the supply side, the innovation of 8-inch platform provides the momentum to scale the production to fulfill demand n previously limited in their access to SiC devices. And 6-in wafer is expected to remain as the mainstream platform, due to the massive capacity expansion by multiple players. These recent trends could reshape SiC ecosystem in the coming decade. MAJOR OEMS PLAN FOR NEW GENERATION OF SIC DEVICES In March 2023, Tesla communicated on their new generation of SiC-based powertrain to use 75% less SiC, which also required innovation in system design and device. Tesla may approach this challenge in several ways. Option 1 is to apply higher level of integration in their next generation of powertrain, to replace the current discrete-like solution, which was developed in the mid-2010s. Option 2 is to match the requirement of power ranges in their coming models, which are more cost competitive, and less demanding in performance, thereby requiring less SiC content. Option 3 could involve the implementation of a hybrid solution, combining SiC with other technologies, such as IGBT. It would require innovation in topology and system integration. The next move of major OEM would impact the demand for SiC, however, it does not change the trend of applying SiC in 800V EVs to provide higher efficiency and to enable high-speed charging. 8-INCH SIC WAFER AS A NEW APPROACH TO SCALE When Wolfspeed started initial production of 8-inch SiC wafers in 2022, it showed an innovative step to scale production on the supply’s side. As of 2023, there are multiple device manufacturers who unveiled their plans to build 8-inch SiC wafer facility in the coming years. The first fab is located in the US, but the footprint of 8-inch fab will be mainly based in Asia, according to players’ plans. However, with the complexity of 8-inch SiC platform, the challenges remain to be overcome, such as low yield at crystal growth, geometry uniformity and higher cost. 6-INCH SIC WAFER REMAINS COMPETITIVE Innovation of 8-inch SiC waferturns a new page in the SiC market, opening the potential for higher device yield and lower cost, thanks to scaling effect. On the other hand, 6-inch platform will remain as the mainstream, due to established eco-system and the engagement of many market players. According to Yole’s estimation, 6-inch accounts for more than 90% of SiC market as of Q1-2023, and the share will remain at close to 80% by 2028. With the massive capacity build-up in China, the global wafer capacity will exceed the demand by a factor of 3. With the potential of 6-inch SiC wafer to gain cost competitiveness, device manufacturers will be able to achieve lower cost at device level to penetrate different applications, such as industrial and renewable energy sectors. CONCLUSION Both demand and supply sides show strong interests in growing SiC to the next level of maturity. SiC needs to be cost-competitive and also accessible to various applications beyond EVs. OEMs are elaborating the benefits of SiC in high efficiency and high voltage capability. New generation of power module requires a higher level of integration. SiC wafer and device manufacturers are scaling up the supply, by implementing the innovative 8-inch platform. Meanwhile, 6-inch SiC remains the mainstream, with more mature supply chain and massive capacity expansion on-going. SiC supply chain will be reshaped correspondingly.

Noncontact High Throughput, High Precision, Electrical Metrology for Wide Bandgap Semiconductors based on Corona Charge Photoneutralization Kinetics
WBG Semiconductor Industry Status and Prospects
In-line characterization of SiC epitaxial layers using high resolution surface photovoltage spectroscopy (HR-SPS)
Application of advanced characterization techniques to SmartSiC™ product for substrate-level device performance optimization
SmartSiC™ substrate: increasing SiC MOSFETs current density from device to module level
How to improve power device / module development efficiency

ABSTRACT. Power modules are employed in various applications such as Electric Vehicles (EV), solar power inverters, trains, home appliances, and aircraft, because of their ease of design, high energy density, reliability, etc. Wide Bandgap (WBG) device based power modules are already available taking advantage of their fast-switching operation, making the whole power electronic module smaller and more efficient. In order to efficiently develop WBG power modules, accurate intrinsic characterization is critical from static to dynamic. However, the dynamic characterization of WBG power modules poses some challenges due to its fast-switching operation, half-bridge structure, residual parasitic, or application specific technology trends. The challenges include but are not limited to the followings.

1. Power modules typically have higher power density than discrete power devices incorporating multiple FET chips to increase current. High current such as 400A is necessary for some EV applications where SiC devices are being used to increase voltage and to reduce charging time. Therefore, a high current with high bandwidth is required. 2. Most power electronics applications require half-bridge structures as the basis for inverters and converters. While it is necessary to perform the measurement on the low-side and high-side devices to characterize half-bridge modules, the voltage potential at the junction between the high-side device source and low-side device drain in a half-bridge configuration dynamically changes with large voltage swings at each switching event. This makes the measurement of high-side FET very challenging, especially for small gate voltages. 3. While it is inevitable to have residual or stray parasitic components in the power module due to its structure, fast transition such as high di/dt or high dv/dt interacts with stray capacitance or stray inductance to distort switching waveforms. Having additional parasitics such as insertion inductance of current sensor, stray capacitance, and inductance due to cables, cable locations, connectors, interface board layout, and so on causes further waveform fidelity problems.

There are a few more challenges for WBG power module characterization such as safety concerns, temperature dependency, usability, and so on. To overcome these challenges, the use of right tools and technologies is critical. In this paper, critical factors and technologies for accurate dynamic characterizations are discussed. Two new technologies are developed specially to solve the aforementioned challenges. While it is important to minimize parasitics in the test setup and timing misalignment of signals, we apply RF compensation to eliminate the influence and fluctuation from the parasitic inductance of the current sensor. Fig. 1 shows unwanted characteristics variation caused by inconsistency of current sensors, which is eliminated after applying RF compensation. Fig. 2 shows measurement results of high-side Vgs signal using two different optically isolated probes. One is a commercially available and popular optical isolated probe and the other is a newly developed optically isolated probe by minimizing the noise floor. Owing to the high CMMR of isolated probes, both probes show excellent waveforms without having the effect of a common mode signal. But the noise shows a big difference between these two probes. Details of these two technologies as well as solutions and techniques to overcome WBG power module characterization will be covered in the final paper.

Advanced Carbon film for high-voltage power, high-performance SiC devices
650 V SiC Power MOSFETs with Statistically Tight VTH Control and RDS,ON of 1.92 mΩ-cm2
PRESENTER: Jaehoon Park
Diamond Grit Size Effects on Grinding of Silicon Carbide Wafers

ABSTRACT. Silicon carbide is a crucial material used to produce power devices and RF communication chips for electric vehicles and 5G telecommunications. However, the wafering processes required to shape it from boule to epi-ready polished wafers demand extensive process knowledge and expertise. Slicing from the boule can be done by multi wire saw or laser processes, followed by surface grinding and CMP processes. Among these processes, grinding is becoming more challenging to meet customer demands for improved surface finish and reduced costs, especially for 8-inch wafer processes. This paper aims to provide a fundamental understanding of Silicon carbide wafer grinding in terms of diamond sizes and related grinding mechanisms. This knowledge will help process and manufacturing engineers to solve and improve the high-volume manufacturing of Silicon carbide wafers.

Centrotherm High Temperature Annealing and Oxidation Furnaces

ABSTRACT. Centrotherm High Temperature Annealing and Oxidation Furnaces

P. Schmid1) 1) Centrotherm international AG, Württemberger Str. 31, 89143 Blaubeuren, Germany E-mail: patrick.schmid@centrotherm.de

With SiC industry going mainstream the demand for SiC specific production tools is strongly growing. Along with the volume increase, comes the transition from 150 mm to 200 mm wafers to reduce manufacturing cost and improve productivity. For this reason, there is a strong demand for 200 mm capable equipment which ideally supports good 150 mm / 200 mm bridging flexibility, high productivity and reliability at small foot print. With c.Activator200 and c.Oxidator200, centrotherm provides a state of the art 200 mm vertical furnace set for high temperature activation annealing up to 2000°C and high temperature gate oxidation up to 1500°C including a wider range of pre and post annealing capabilities in various ambient. Both tools are build on same platform and on production proven all metal free core heating cassette technology. The furnaces are optimized for high productivity, small footprint, good uniformity, bridging on the fly and high thermal budget capability. The tools are available with open cassette, SMIF and manual handling versions, as shown in fig .1 to support a wider range of requirements, ranging from manual R&D and prototyping lines to fully automated production lines. The excellent thermal budget capability of the c.Activator systems with up to 1900 °C long time (continuous) operation and 40 min at 2000 °C is shown in fig. 2. This enables a wide process window as required for R&D and new applications and supports good stability under typical production annealing conditions. The excellent center furnace flat zone temperature homogeneity of ± 0.32 °C shown in Fig. 3. Together with the good temperature stability, this ensures tight and stable process results. Many systems are running already successfully in 150 mm and 200 mm SiC production lines at leading SiC manufacturers worldwide.

Rapid industrialization of SiC trench technologies

ABSTRACT. Efficiency requirements in automotive electric drives have enabled a breakthrough for SiC-based MOSFETs [1]. These wide-band-gap semiconductors facilitate the design of more compact and efficient inverters, which make it possible to increase the vehicle range by more than 6% with the same battery size [2-3]. Robert Bosch has been delivering SiC MOSFETs in series production since 2021 both for internal projects and as bare dies and discrete devices for the external market. The Bosch SiC technology was developed using a trench layout and is based on more than 20 years of experience with trench etching [4,5]. We will present a technology roadmap. Bosch’s Gen2 (also based on SiC-trench technology) will be released in 2023 with a focus on reduction of Rds,on, a better switching performance and a better efficiency (WLTP cycles). Gen3 and Gen4 development projects have already started and will be introduced into the market within this decade. We will show the benefits of Bosch’s vertical integration. Activities include the development and production of SiC wafers, MOSFET chips, Power modules, and inverters. We expect the market for SiC chips to grow by 30 percent per year on average. In order to support this demand and for having a better regional coverage, Bosch has decided to acquire assets of TSI Semiconductors in Roseville, USA [6]. We will motivate and demonstrate how this acquisition and further investments at both the Roseville and Reutlingen plants will lead to a significant extension of Bosch’s global SiC chip portfolio; we expect to deliver first chips produced on 200mm SiC wafers in 2024 (Reutlingen) and 2026 (Roseville), respectively.

[1] P. Friedrichs, “SiC MOSFETs”. In: Advances in Semiconductor Technologies: Selected Topics Beyond Conventional CMOS, pp.295-320 [2] M. Boesing, D. Schweiker, “Design Aspects in SiC MOSFET based High Performance Automotive and Commercial Vehicle Inverters”. In: Proceedings of the PCIM Europe Conference. May 2023 [3] K. Heyers, S. Schwaiger, C. Banzhaf, M. Grieb, „SiC-Trench-MOSFETs for automotive drive application”, in Bauelemente der Leistungselektronik und ihre Anwendungen 2017 - 7. ETG-Fachtagung. [4] F. Laermer, A.Schilp (1996). “Method of anisotropically etching silicon” (U.S. Patent No. 5,501,893). U.S. Patent and Trademark Office. [5] A. Trautmann, C.Banzhaf (2013). “Method for Structuring Silicon Carbide” (German Patent No. DE102012200236). [6] https://www.bosch-presse.de/pressportal/de/en/rising-demand-for-sic-chips-bosch-plans-to-acquire-u-s-chipmaker-tsi-semiconductors-253824.html

18:30-20:30 Session 13B: Industrial Session B
Location: Ulisse
Atomic Diffusion Bonding using nitride films and oxide films

ABSTRACT. We demonstrated atomic diffusion bonding (ADB) of wafers at room temperature using nitride and oxide films. High surface free energy at the bonded interface was achieved for as-bonded wafers using these films with high electrical resistivity. These properties of bonded wafers using nitride and oxide films are useful for new electrical devices.

High-speed, high-resolution, non-contact resistivity and anomaly imaging of boules and wafers

ABSTRACT. With global electrification needs forecasted at 1000 TW-units per year in the next decade, the demand for faster power electronic devices in the form of wide bandgap (WBG) materials is poised for exponential growth. Material innovations, process improvements and supply chain optimization are all functioning in tandem to facilitate the accelerated commercialization of advanced power electronic devices. A key step in this complex process is material testing which is mandatory at different stages of semiconductor manufacturing. This paper introduces the advancements in material testing, characterization and imaging of wide bandgap materials.

WBG power electronic devices are key drivers of emerging high-value products in automotive, IT and data center, grid infrastructure, electric motor drives and aerospace. SiC and GaN have clearly proved to be more efficient, lighter, smaller power electronic devices operating at high frequencies and at elevated temperatures. With different processing methods introduced by the material makers, testing and qualifying the bulk materials at an early stage helps in identifying the effects and defects before they become critical to wafer and, eventually, device performance. This includes facet detection and characterization in boules and wafers as well as identifying zones with high defect density. Non-contact eddy current technology provides this early stage detection, layer monitoring and process control through electrical characterization method.

The incumbent method to electrically test ingots and boules is four-point-probe (4PP). However, SiC surface characteristic and often its high resistivity lead to imprecise results. Additionally, the limitation of 4PP is obvious that it is a contact measurement method and could potentially induce imprints and bring contamination or damage to the SiC material itself. GaN and other WBG materials, although have different properties, face the same testing challenges.

This paper presents the state-of-the-art electrical characterization methods and shares insights of the advancements in eddy current imaging technique that provides high-resolution resistivity mapping of SiC and GaN boules and wafers entirely in non-contact mode. It additionally explores the testing of processed 150 mm and 200 mm wafers in high-speed mode at 5,000 measurement points per minute by automatic loading of cassettes and scanning of individual single wafers by an innovative floating-wafer technology.

Novel Silicon Carbide (SiC) Chemical Mechanical Planarization (CMP) Solutions for Enhanced Performance and Cost of Ownership

ABSTRACT. With the continued growth in adoption of 150mm and 200mm Silicon Carbide (SiC) wafers for power device fabrication, the need for higher material removal rate (MRR), lower surface roughness (~ 1A), no scratches, and more uniform surface topography are becoming critical. In this presentation, we will share how our portfolio of slurries, pads, and cleaning chemistries enables customers to start with a high-yield process and reduce process development times. This end-to-end solutions approach addresses the critical needs around high removal rate coupled with excellent surface quality and defectivity. Higher removal rates are typically achieved by either more aggressive process conditions (downforce and revolutions per minute (RPMs)) or increasing both the abrasive percentage in the slurry and chemical action from the oxidizer. This leads to scratching and particle-related residue defectivity, in addition to the shortening of pad life due to particle buildup, waste buildup, and increased wear. To address these challenges, novel abrasive systems comprising of a harder core with a softer shell were developed to deliver very high material removal rates utilizing a low solids percentage while minimizing sub-surface damage (no scratches). Additionally, pad design using proprietary thermoplastics are utilized to maintain the high removal rate without scratches. The thermoplastic pad asperity tip softens as the polishing temperature increases, providing scratch benefits while still maintaining higher removal rates due to the bulk hardness. Due to reversible phase change with temperature, these pads also maintain consistent removal rates throughout pad life. Cleaning chemistry based on compatibility with both the types of abrasives used (charge), and oxidizing systems (reducing agent and precipitated polishing products) were developed to further reduce residue defects. Novel surfactants and dispersing agents were developed based on the interaction with slurry abrasives and polishing by-products. Furthermore, fundamental mechanisms around factors controlling surface roughness were investigated to achieve ultra-low roughness (~1A). In this presentation, we will share the preliminary findings around the nature of oxidizers and abrasives and their impact on surface roughness.

Ion Implantation Application Overview and Product Requirements for SiC Wafers and Devices

ABSTRACT. While silicon (Si) is a foundation for semiconductor technology and present electronic devices, wide bandgap compound semiconductor materials have attracted considerable interest over the past few years owing to a rising demand for high power applications. Among those promising wide bandgap materials, silicon carbide (SiC) is one of the leading candidates with products in several industries. Nevertheless, our knowledge of SiC is far from mature. Different properties from Si and device designs create a different set of process challenges that consequently drives development of specific manufacturing equipment to meet the requirements. Because of limited dopant diffusion, doping in SiC is typically realized by epitaxy [1, 2] or ion implantation [3]. Non-uniform doping profile is not uncommon in epitaxial SiC [4] and needs to be improved for optimum device performance and yield. Ion implantation, on the other hand, is a well control process with precise dose control and accurate depth profiling. The process unavoidably generates undesirable crystal damage and defects, which can be detrimental to device performance. Defect removal is usually difficult and almost always requires very high temperature treatment. In this presentation, major implant related SiC challenges are reviewed. Implant applications and product requirements are highlighted. These include wafer handling, process uniformity, particle, and metal performance. Applied Materials VIISta® SiC ion implantation platforms, capabilities, and add-on functionalities are presented to offer viable solutions for SiC wafer and device fabrication.

[1] U. Forsberg, Ö. Danielsson, A. Henry, M. K. Linnarsson, and E. Janzén, J. Cryst. Growth 236, 101 (2002). [2] U. Forsberg, Ö. Danielsson, A. Henry, M. K. Linnarsson, and E. Janzén, J. Cryst. Growth 253, 340 (2003). [3] A. Hallén and M. Linnarsson, Surf. Coat. Technol. 306, 190 (2016). [4] E. Balkas, Y. Khlebnikov, R. T. Leonard, M. Conrad, T. Kuhr, A. Powell, J. H. Lee, and S. Bubel, Abstract of International Conference on Silicon Carbide and Related Materials (ICSCRM 2022).

How process scaling offers maximum flexibility of SiC wafering along the complete process chain
Sonic Lift-off to Enable Substrate Reuse of Wide Bandgap Semiconductors
Streamlining SiC Boule Fabrication - Optimized Wafer Ready Material
Analysis of Key Factors in High Aspect Ratio Etching of SiC Gate Trench with SF6/O2 Inductively Coupled Plasma
New Generation SiC MPS Diodes with Low Schottky Barrier Height
Total SiC Polishing Process Optimization for Cost of Ownership
Rapid Diamond Mechanical Polishing of SiC Substrates using the IRINO-PRO-C Structured Composite Polishing Pad
Enabling Next Generation WBG Semiconductors Using CVD Technology
Testing challenges for latest SiC devices

ABSTRACT. SiC technology is experiencing tremendous growth at this moment, but at the same time, it poses unique challenges on the manufacturing cycle in general and on the testing process in particular. Among these challenges, we see the need to design a signal path with minimal stray inductance. This is critical to minimize voltage overshoots during commutation, but represents a time-consuming and costly process. We will see how a precise software modeling of all the elements along the connection chain can help the design process, allowing an accurate simulation of all the relevant conditions, and shortening the time required from several weeks to a couple of days. A second critical challenge is to ensure high voltage testing for SiC KGD devices. The absence of a molded package around the Silicon, combined with the increasingly high breakdown voltage of these products, requires a careful design of the contact elements in order to avoid arcing which could prevent the devices from reaching the desired testing voltage. We will show how these technological challenges can be solved by the means of standard ATE equipment, with innovative test methodologies.

Answers to SiC wafer and device production challenges

ABSTRACT. ACCRETECH, combines the words ACCRETE, meaning “to grow and fuse together” and TECHNOLOGY. We seek to gather global, cutting-edge technologies, overcome challenges and precipitate growth. As a global supplier of equipment for edge grinding, high rigid wafer grinding, chemical mechanical polishing (CMP), wafer probing and wafer dicing, ACCRETECH works in the field of next generation SiC power devices. After separating wafers from the ingot, wafers have sharp edges which are rounded with a diamond cutter during the wafer edge grinding process. The wafers are optimally prepared with round and smooth polished edges for subsequent process steps. ACCRETECH newly developed a grinding unit for better rotational precision of the spindle and profile sharpness, which makes the tool suitable for various wafer materials such as SiC, GaAs, GaN etc. [1] Approaching issues and needs that come along with the characteristics of SiC, GaN, sapphire and others, ACCRETECH developed tools to grind these materials that are considered to be hard-to-cut-materials (hard and brittle). Sophisticated ACCRETECH grinders for fully automated single wafer or boule grinding guarantee high quality surfaces, at short process time and high accuracy. [2] Once entering the FEOL device manufacturing, our long experience with hard material made us understand the demands for having successfully developed the right SiC CMP technology to increase chip performance and power efficiency. SiC wafer surface quality is critically important as any defects on the surface of the wafer will migrate through the subsequent layers. To produce uniform wafers with the highest quality surfaces, CMP using a dedicated polishing head for SiC and End Point Detection (EPD) for high precision, repeatability and highest surface quality gives the best answer. Processing with 3 polishing tables and 2 polishing heads is ideal for mass production. Options for higher removal rate, single- or double side polishing, measurement of material removal and wafer breakage detection are available among others. [3] An example of removal rates is shown in Fig.1. Polish grinding allows thinning and defect removal. Pre-grinding, fine grinding, and polishing are carried out simultaneously on individual stages before cleaning and unloading. Once loaded, the wafer will not be removed. Both side processing is possible in sequence. [4] The task of wafer dicing machines is to separate the wafer into chips. Mechanical blade dicers cut the wafers using fine dicing blades. Our semi and fully automatic ACCRETECH blade dicers are available for all common wafer sizes. In addition to an easy-to-use set-up and user-friendly software, their excellent properties include high processing speed and a very compact layout. With the smallest fully automatic blade dicers in the world including dual facing spindles, ACCRETECH is setting new standards for small footprint and high-efficiency. Specifically developed ACCRETECH dicing blades as shown in Fig. 2 enable SiC wafer dicing with high quality and high throughput. [5] Wafer probers are machines which are required for electrically testing of individual chips on the wafer. The prober therefore undertakes the fully automatic loading and handling of the wafer while ensuring the best positioning accuracy. A full test cell consists of a wafer prober, a test unit and a probe card. ACCRETECH probers allow not only to work with the highest precision using latest technology, but also to ensure maximum capacity and productivity. [6] With our tools for many critical manufacturing steps in SiC and GaN processing (Fig.3), ACCRETECH (Europe) GmbH, located in Munich / Germany, is your leading partner to provide answers for SiC wafer and device production challenges.

SiC Power Device Manufacturing “EFIITRON” ion implanter for Advanced SiC Drift Zone Doping

ABSTRACT. For modern vertical Silicon-Carbide (SiC) power devices accurate custom-tailored doping of voltage sustaining layers is a key issue with respect to device performance and chip cost. Conventional epitaxial doping suffers from large doping variations of up to 20% (N) [1], which entails cost-performance issues, imposes limitations for optimization and complicates wafer diameter scaling. mi2-factory GmbH from Jena, Germany has developed the so-called “Energy Filter for Ion Implantation (EFII)” [2,3,4,5] technology, which transforms a monoenergetic beam into a beam with a well-defined broad energy range. Using the energy-filter technology for SiC drift-zone doping requires availability of suitable high-energy ion implanation equipment. We will give an outlook to key features of our novel “EFIITRON” ion implanter equipment, which combines high energy ion implantation and energy-filter technology. “EFIITRON” is optimized for SiC applications using the energy-filter technology.

“EFIITRON” enables advanced drift-layer doping e.g. fabrication of box profiles up to about 10µm in SiC. “EFIITRON” is by its nature highly precise (<3%) and allows both for custom-tailored deep Al and N profiles. EFII technology is easily scalable to 200mm, where also excellent doping homogeneity is expected. We will also give a further outlook on applications, like formation of p-type pillar-like structures, which form the basis for fabrication of SiC-Superjunction-MOSFETs and novel SiC epitaxial-free engineered substrates.

[1] Wolfspeed materials catalogue, https://assets.wolfspeed.com/uploads/2020/12/materials_catalog.pdf [2] Csato, Krippendorf, Akhmadaliev, v.Borany, Rüb et al, Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms 365 (2015): 182-86. [3] Guseva, Akhmadaliev, Csato, Rueb et al, 22nd International Conference on Ion Implantation Technology, September 16th-21st, 2018, Würzburg, Germany [4] Agnostelli, Sea, et al. GEANT4—a simulation toolkit. Nuclear instruments and methods in physics research section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2003, 506. Jg., Nr. 3, S. 250-303. [5] Homepage mi2-factory, www.mi2-factory.com, 2022

Improvement of SiC film thickness and wafer thickness uniformity by ion beam trimming