ABSTRACT. Chip resistors are integral components of electronic devices, including Active Implantable Medical Devices. This work, as part of RECOME project, is focusing on developing a methodology for defining accelerated life test plans to qualify chip resistors as per the mission profile of AIMDs. This will be done by combining design of experiments and accelerated life tests associated with failure mechanisms. Defining test protocols, such as thermal cycling, will be a critical component of this work.

ABSTRACT. Foldable displays have many moving parts and can face different environments. These conditions lead to potential interactions between diverse failure mechanisms and stresses, making reliability assurance a significant challenge. Ensuring reliability while considering all these potential failure mechanisms and stresses is very challenging. This paper introduces a method for comprehensively evaluating the reliability and lifespan of foldable displays. First, potential failure modes associated with foldable displays were identified, and corresponding influencing factors were determined. In addition to the fundamental stress factor of repetitive folding, temperatures, humidity, and temperature changes were chosen as influencing factors. To assess the influence of these factors on the display performance, two levels of stress severity were selected. Using these three factors and two stress levels, experiments were conducted using the design of experiments (DOE) method. The test results intuitively revealed the principal effects of each stress factor on the final quality and performance of the display. We found that low temperatures and temperature changes can affect the catastrophic failure of the display panel, and the number of folds impacts the degradation of the hinge parts. The proposed DOE-based evaluation method can be used to ensure the comprehensive reliability of foldable displays.

ABSTRACT. In this paper, a machine learning method is proposed implementing the Principal Component Analysis to study the statistical EEPROM endurance degradation. This technique is firstly applied to an UV irradiated memory array. Then, the Density Based Spatial Clustering of Applications with Noise and the Gaussian Mixture Model are presented to extract the minority population of cells. The reliability test study demonstrated the ability of the proposed technique to correlate electrical parameters to forecast the quality and performance of a memory array. Compared to the classical threshold voltage (Vth) analysis, this method is more effective for predicting which population will experience greater degradation.

ABSTRACT. This paper presents a condition monitoring system for predicting failures of power converters in humid environments by detection of moisture-induced structural changes on printed circuit boards. To this end, probable failure mechanisms and possible condition monitoring concepts are presented. Subsequently, a condition monitoring concept is developed that targets electrochemical migration as a dominant failure mechanism, detecting potential failures by using comb structures as condition indicators or canaries. A suitable circuit is designed, consisting of a high voltage supply for inducing electrochemical migration and a transimpedance amplifier to measure surface insulation resistance, using a minimum number of common components and PCB space. The circuit is realized as a prototype and subjected to characterization and long-term measurements.

ABSTRACT. The improvement of the LED technology has allowed more functionalities and better performances in automotive lighting systems, however, etendue of the source is still a critical issue leading manufacturers to reduce the emitting surface area and increase the current density, thus causing possible issues with reliability. With this work we report on the degradation of state-of-the-art automotive grade commercial LEDs. Samples were subjected to constant current stress at different current values and temperature. An initial step stress has been carried out up to currents 1.6 times higher with respect to absolute maximum current, followed by a long-term stress at different baseplate temperature for a duration of up to 4500 h. Results indicate that LEDs suffer both from gradual performance decrease and catastrophic degradation as a result of combination of high current – high temperature operation.

ABSTRACT. In this paper, a new aging equivalent model based on Arrhenius plots, able to be exploited for aging evaluation, is presented, showing early simulation results. In addition, a test bench for Li-Ion batteries aging and characterization has been presented, together with early measurements results for model validation.

ABSTRACT. GaN's advantages over conventional semiconductors make it an excellent candidate for deployment in the transportation area. This work attempts to develop a simple-to-manufacture, one-sided DC/DC GaN-based Buck converter and prove its feasibility through the use of a multiphysics optimization of the chosen topology. In order to improve the design, the Ansys "Q3D tool" is used to estimate parasitic elements, which are then included in an electrical model in the waveform viewer software "LTspice" to assess their effects on the switching node signal "Vsw" of the half bridge structure. The overshoots and ringings will be examined next by comparing the measured and simulated converter’s Vsw and the output signals. In addition, this study gives an analysis of current density in the layout, as well as the heat distribution in the converter circuit. Closer measurement results to simulation are presented in the primary outcomes, highlighting the effectiveness of the converter layout optimization topology

ABSTRACT. This paper presents a comparison on cycling strategies for lithium-ion batteries. Furthermore, an evaluation of two cycling strategies is conducted on an experimental study on LG 21700 lithium-ion battery. The investigation focused on examining the capacity degradation on batteries subjected to two cycling protocols, conducted at an ambient temperature of 0°C and stress factors depend on actual capacity instead of nominal capacity. The capacity losses were estimated after cycling and were found to be 27% for protocol 1, and 20% for protocol 2.This paper also presents the impact of discharging current and the depth of discharge on capacity utilization to support the development of optimized cycling protocols for practical applications

ABSTRACT. This work presents an overview on the power distribution design requirements in automotive power distribution systems, with focus on wire harness protections. While standard melting fuses are still widely used in automotive power distribution systems, the complexity of the future automotive platforms can be enabled only by replacing melting fuses with electronic protections. This paper will analyse the typical design requirements in terms of wire protection, which electronic protections concepts are available and how a safe wire protection can be ensured.

ABSTRACT. Solid tantalum capacitor is an excellent component because of its higher capacitance within the lower volume, which makes it widely used for microwave circuits, signal and power devices. The degradation of insulation performance is the most common failure mode. In this paper, a new model for leakage current degradation is proposed. This model is based on experimental measurement analysis and microscopic structure analysis, providing precise prediction values without long-term degradation tests.

ABSTRACT. Electrical connectors are important components in electrical systems, responsible for the transmission and control of electrical signals. In the process of use, frictional wear occurs between the pins and sockets of the contactor in an electrical connector. This phenomenon results in an increase in contact resistance, which can further lead to system failures, so it is critical to ensure the stability of the performance of the contactor. In this paper, a commonly used specification of wire-spring contacts is investigated. Firstly, its mechanical properties were analysed, and then the contact component was vibration tested under different vibration conditions at room temperature to obtain the wear forms of the contact component under various vibration conditions. Finally, based on the parameters obtained from the experiments, a physical model of frictional wear failure was established for this contact component model, and the contact failure time as a function of vibration stress was obtained.

ABSTRACT. As the applications of inverters in daily life become more viral, target which aims at increasing the power density of the device is gaining higher importance and has become a new trend and hotspot in research. In order to achieve the goal, a high switching frequency technique is necessary to be used. However, this leads a consequence of the low efficiency of the device. That’s when the soft-switching method shows its advantage. Meanwhile, gallium nitride (GaN) devices are easier to be applied in the circuit. This paper will briefly introduce a design based on GaN devices and soft-switching technology in an off-grid solar power generation system.

ABSTRACT. Here, a novel compact model for BTI degradation is presented correlating the time law of degradation with voltage stress. Voltage induced charge traps shift the VTH, decreasing the probability of new charge creation. The result is a moderation of voltage stress at the Si-SiO2 interface with time. The voltage and time components are directly derived from the power law, V^-gamma which shows a time dependence given by a∙t^1/n. A linear regression fit of degradation data is correlated with Weibull distribution statistics to make a high precision measurement of the n-root time law in BTI

ABSTRACT. The impact of metal contacts on the electrical properties of SiN dielectric film in MEMS capacitors is investigated. The investigation is performed employing MIM and MEMS capacitors with Au and Ni contacts. A resistive switching like behavior is monitored in the case of Ni contacts. This behavior is attributed to the presence of deep traps in SiN and the effect of different metal contacts as revealed from Thermally Stimulated Depolarization Current assessment. Recommendations will be provided in the final paper.

ABSTRACT. A large difference in Time-to-Failure in Metal – Ferroelectric – Insulator - Semiconductor (MFIS) devices in response to Interrupted and Uninterrupted Constant Voltage Stressing was found, which underscores the significance of stress interruption on the physical mechanisms occurring in the device. However, the effect of interruptions during stressing in MFIS devices is relatively unexplored. This work aims to pave the way for the development of stressing schemes for the evaluation of Ferroelectric devices with closer adherence to practical operating conditions.

ABSTRACT. This article presents a reliability study on conventional 650V SiC MOSFETs subject to carrot-like defects under High Temperature Reverse Bias (HTRB) stress. The instabilities of some parameters are monitored, and the drift analysis of the most critical one is presented. The analysis of the electrical characteristics on samples subjected to HTRB shows an evident difference between devices with and without defects.

ABSTRACT. In circuit assembly, thermal design optimization is a critical process to enhance thermal performance through optimal component layouts. This process is becoming increasingly indispensable due to the escalating demand for compact and highly reliable devices. Notably, component parameter degradation can lead to a higher temperature and thus accelerate degradation as a self-accelerating effect. In this paper, we propose a thermal design optimization method considering the component degradation self-acceleration effect. Based on the practical mission profile, an electrical model is established to obtain capacitor power loss. Additionally, a high-resolution analytical thermal model is employed to calculate the temperature of capacitors under the dynamic ambient temperature profile. The degradation is accumulated based on the capacitor temperature, which updates the power loss as the degradation self-accelerating effect. The component layout with the lowest initial temperatures does not necessarily result in the longest lifetime. Hence, the optimization objective is focused on maximizing the lifetime rather than minimizing the initial temperature. To demonstrate the practicality of the proposed method, a case study involving electrolytic capacitors utilized in a boosted motor drive system is presented. The proposed method can effectively enhance reliability and reduce manufacturing costs.

ABSTRACT. Scanning Acoustic Microscopy (SAM) is a widely used tool for inspecting the internal structure of modern semiconductor devices. The Synthetic Aperture Focusing Technique (SAFT) has been qualified for complex samples with interfaces and bond wires at various depths, ensuring acceptable inspection times. This paper introduces a method to estimate suitable reconstruction parameters for unknown samples. The evaluation of reconstruction quality is performed by calculating image metrics while varying the reconstruction parameters. The required accuracy of parameters for a successful reconstruction is determined. Additionally, a semi-supervised parameter estimation approach is presented. The examinations were conducted on a PSSO36-like plastic molded package.

ABSTRACT. Reliability holds paramount importance in equipment operation, as the presence of defects can substantially undermine its dependability. this paper proposes an edge repair algorithm based on the approximation principle of circles, and then uses the least square method to fit the ellipse parameters of effective edge points, so as to realize the detection of defect ellipse holes and effective parameter extraction. Finally, the effectiveness of this method is verified by experiments. The measurement accuracy exceeded 9μm, and the angle error accuracy surpassed 0.15°.

ABSTRACT. Silver sintering is the state-of-the-art technology for highly reliable chip - substrate interconnects. The power cycling reliability, however, strongly depends on the thermal and mechanical properties of the sintered bond line, both of which are governed by the magnitude and the homogeneity of the porosity in sinter layer. This dependency is investigated and discussed in this paper. Power cycling tests were performed on sintered samples having different porosities and / or porosity distributions after which the samples were subjected to failure analysis. It is concluded that - within the tested ranges - the sinter layer porosity and its distribution is not limiting the power cycling capability.

ABSTRACT. SiC Mosfet is a technology in development for power electronics and especially for automotive applications. Aging of the gate oxide with HTGB stress on a commercial device permits a better understanding of the failure mechanism occurring on the device. Electrical characterization, Raman extraction, Atomic Force Microscope associated with a “resiscope” and XPS-Auger analyses help us to understand the composition of the oxide design and how we can proceed for better reliability. An electrical modification related to an atomic variation is detected through an oxidation process realized in two steps. Further analyses will be carried out on other devices for comparison.

ABSTRACT. Sintered Cu joints may experience reduced reliability due to oxidation during the operation of wide-band semiconductor devices. This study investigates the evolution and failure modes of sintered Cu joints aged at different temperatures in air. Sintered Cu joints undergo varying degrees of oxidation when exposed to different aging temperatures and times, leading to changes in their failure modes. Ductile fracture between Cu particles dominates the fracture mode of slightly oxidized aged joints, where the oxide is only coated on the outside of the sintered body. The oxides in the mildly oxidized aged joints fill the pores of the initial sintered body and convert the connection between the Cu particles into a connection between the oxides. This change results in a brittle fracture on the connecting layer. Severe oxidized joints undergo a complete replacement of the Cu particle connection with a Cu oxide connection. When the strength of the connection layer exceeds that of the chip connection, fractures occur in the chip connection. Understanding the various mechanisms of Cu oxidation and joint failure modes will expand the potential for Cu sintering in wide bandgap devices and guide enhancements in their long-term reliability.

ABSTRACT. Thermal interface materials (TIMs) play a crucial role in managing thermal resistance from the junction to the ambient in power modules, impacting thermal loading and reliability performance. However, in many cases, the thermal impedance of the TIMs is simplistically assumed as a constant, leading to unrealistic thermal stress analysis and uncertainty in predicting the lifetime of power converters. This paper investigates thermal trends for TIMs based on experimental characterizations conducted under thermal cycling conditions. This allows for more accurate reliability prediction of lifetime as well as to provide a means to develop maintenance schedules for ensuring sufficient thermal performance over the operating lifetime.

ABSTRACT. This paper presents a novel approach based on physical failures instead of electrical failures for PBO delamination and RDL corrosion detection. Moreover, most effective reliability stress to generate such failure mechanisms are presented through theory and experimental trials. This study can serve as a guideline for selecting the best reliability stress to detect PBO delamination or RDL corrosion issues in future qualifications.

ABSTRACT. The measurement of quasi-static undesired switching in flip-flop output using laser voltage techniques is critical due to the low frequencies involved, which are often incompatible with most laser voltage probing systems. Additionally, a minimum signal repeatability is required to trigger the signal for accurate measurement. To overcome these limitations and achieve a full characterization, this study utilizes the fault simulation techniques. The objective of this work is to build a model of the failing flip-flop that matches laser voltage probing measurements, providing a deeper understanding of the failure mechanism of this cell.

ABSTRACT. Both the state of health (SoH) and remaining useful lifetime (RUL) estimation of power modules can play a key role in maintenance strategy and control optimization. Common solutions that evaluate only the on-state voltage (V_{ce}) suffer from estimation uncertainty especially at early lifetime stages. The paper proposes a data fusion (DF) algorithm using two common degradation precursors, V_{ce} and thermal resistance as well as a degradation model. The algorithm prioritizes individual precursors based on both accelerated degradation tests analysis and sensor model . The performed simulations indicate the accuracy improvement at both early and late lifetime stages.

ABSTRACT. The effect of Drain Field Plate design and 2DEG density on dynamic-RON of 650 V p-GaN gate AlGaN/GaN HEMTs is investigated in this work. Devices presenting three different AlGaN barrier and p-GaN layer design have been tested by means of Capacitance-Voltage measurements, Static VDS stress and Pulsed I-V characterization. C-V measurements allowed the extraction of 2DEG density, while Static VDS stress and Pulsed I-V put in evidence the partial recovery of the dynamic-RON at high VDS,stress, potentially explained by impact ionization generated holes that partially compensates negatively ionized Carbon acceptors in the GaN Buffer. This hypothesis is in line with the trends observed for different 2DEG density and different drain field-plate designs, suggesting that a higher electric field under the drain terminal can significantly reduce RON-degradation at high voltages, due to an easier holes generation through impact ionization.

ABSTRACT. As the key interconnecting structure of high-performance 3D chips, through‑silicon via (TSV) is of great significance to improve chip packaging efficiency and computing performance. However, under the increasingly complex and severe service environment, the failure mechanism of TSV is increasingly becoming a key problem hindering the development of 3D chips in the future. In this study, based on the crystal plasticity theory, the mechanical behavior evolution mechanism of TSV under thermal cycling load is explored by constructing a plasticity constitutive considering thermal expansion coefficient and temperature correlation grain plasticity parameters. Results show that the mean Cu grain area increases from 55.42μm2 to 65.74μm2 after thermal cyclic loading, and mean misorientation angle decreases from 41.34 degrees to 35.53 degrees correspondingly. The stability at the grain boundary is lower than that inside the grain, and the peak value of different indicator corresponds to different slip system. This study can be regard as the basis for the reliability research in extreme service environments, and has certain reference significance for promoting the development of 3D chips.

ABSTRACT. Bias temperature instability impacts parallel SiC MOSFETs, particularly in SiC module applications where MOSFETs are turned off with negative voltage. In this paper, 400 hours positive and negative high temperature gate bias stress (p-HTGB & n-HTGB) tests have been performed at -40°C and 175°C on 5 parallel connected SiC MOSFETs. The individual VTH shift for each of the 5 devices and the module VTH shift have been characterised. The results show that p-HTGB stress yields higher peak module VTH shifts compared to n-HTGB (21.32% at 40 °C and 29.405% at 175°C). For recovery times in the order of milliseconds, the magnitude of the peak VTH shift shows a negative temperature coefficient for p-HTGB and a positive temperature coefficient for n-HTGB. Using the maximum positive gate voltage stated on the datasheet, a peak average VTH shift of 1452 mV is observed at -40°C, whereas the permanent average VTH shift is 54 mV (~1/27). However, at 175°C, a peak shift of 1033 mV is measured while the permanent shift is 201 mV (~1/5). These findings emphasize important considerations for assessing BTI in parallel connected devices.

ABSTRACT. In this paper, single particle irradiation effect experiment is carried out to analyze single-event effect (SEE) of commercial 4H-SiC power MOSFETs. The degradation relationship between current-voltage characteristics and reverse bias voltages under irradiation environment is proposed. The result shows that increase of on-resistance is the cause of the current-voltage degradation. The mechanism of single particle damage under different bias voltages is discussed based on the on-resistance theory, which draw a conclusion that damage of epitaxial layer after single particle irradiation is the main reason for the degradation of on-resistance.

ABSTRACT. In this paper, we investigate the packaging aging of SiC MOSFETs under current-limited short circuits as DC solid-state power controllers (DC-SSPCs). The characteristics of low on-resistance and high operating junction temperature(TJ) for SiC MOSFETs make it an ideal power device for DC-SSPCs. During the process of removing the short circuit fault, the short circuit current will be limited to a lower value by DC-SSPCs for a long time, then cut off. This results in TJ inside the SiC MOSFET, causing reliability problems. At present, the SiC MOSFET short circuit(SC) reliability research mainly focuses on the electro-thermal mechanism of SiC MOSFETs under SCs for high-frequency converters(HFCs).The packaging stress and aging mechanism of SiC MOSFETs under the current-limited short circuit is still unclear. SPICE-based and FEM-based simulation are performed to analyze the package stress of the SiC MOSFET under the CL-SC for DC-SSPCs and the SC for HFCs. The results show that the bonding wire lifted-off and the edge delamination and the void in the middle of the solder layer are more prone to be induced under the CL-SC, which is different from the SC for high-frequency converters. This provide important reference for the reliability evaluation of SiC MOSFET for the DC-SSPC.

ABSTRACT. The authors proposed in-depth experimentation and physical analysis showing the extreme robustness capability of low-voltage GaN HEMT in single and repetitive short-circuit. A 2DEG pinch-off behavior is analyzed depending on VDS voltage and charges’ trapping / de-trapping relaxation time. A new drain–gate leakage-current mechanism at turn-off is suggested to explain the ultimate thermal-runaway failure-mechanism.

Preference submission : Poster Session.

ABSTRACT. For the first time, a structural physical modeling of the Intermediate-Layer-Dielectric (ILD) cracking in a planar-gate SiC MOSFET under short-pulse short-circuit is proposed. This new approach is based on Rankine's damage energetic description, relying on the SiO2 mechanical properties. Using a complete 2D high-temperature range electrothermal-metallurgical and elastoplastic-mechanical SiC MOSFET model, Rankine's sub-model is successfully implemented. The first results allow the extraction of crack penetration depth in a single pulse, prefiguring the average critical cycles number estimation to a possible complete destructive ILD fracture.

ABSTRACT. We present an extensive analysis of the impact of drain-source current off-state leakage on the dynamic on-resistance of GaN HEMTs with p-GaN gate. We analyzed two wafers with epitaxial layers grown under different conditions, having different off-state leakage. We demonstrate that the wafer with lower off-state leakage shows a large dynamic Ron instability. Based on current transient measurements, this difference is explained by considering that a larger leakage (still below the nA) through the unintentionally-doped channel layer can ease the generation of positive charge at the bottom of the buffer, with consequent compensation of the dynamic Ron effect. The methodology presented in this paper constitutes a rapid and effective approach to evaluate the conductivity of the GaN channel layer, and its contribution to device stability.

ABSTRACT. The research delves into the impact of gate oxide layer thicknesses on latent gate oxide damage in Silicon carbide (SiC) power metal oxide semiconductor field effect transistors (MOSFETs) during heavy-ion irradiation, employing a combination of experiments and technical computer-aided design (TCAD) simulations. SiC materials and devices hold significant promise for aerospace applications owing to their high thermal conductivity, temperature tolerance, and resistance to harsh conditions. Nonetheless, SiC power devices often encounter single event effects (SEE) induced by high-energy particles such as heavy ions, compromising their efficacy in space environments. The study exposes SiC MOSFETs with gate oxide thicknesses of 40nm and 60nm to 78Kr ion irradiation followed by post-irradiation gate stress (PIGS) tests, scrutinizing failure characteristics induced by irradiation. Through TCAD simulations, the internal dynamics of the gate oxide layer are scrutinized, revealing that escalated electric fields and localized energy pulses predominantly precipitate gate dielectric layer damage. The study concludes that gate oxide thickness markedly impacts latent gate damage, with thinner oxide layers exhibiting heightened susceptibility to electrical breakdown. These findings enrich the comprehension of SiC power device reliability in radiation-rich environments, furnishing invaluable insights for aerospace applications.

ABSTRACT. This paper presents a physics-informed stochastic process for remaining useful life prediction of power modules, which uses high-order Markov chains to capture dependencies in health indicator evolution. Coupling with the domain restricted Paris’ law, which gives the growth rate of the degradation, it creates a fully comprehensive model with respect to the module lifetime. This coupling offers higher expressivity and lower costs compared to classical and purely simulation-based physics models, while requiring less data and offering more interpretability than their data-driven counterparts. This makes extrapolation over unseen test conditions possible, by using the Markov chain stochastic model to link the Paris’ law simulation results at the reference temperature, to those at different temperatures. The fracture mechanics theory on which the model is based, as well as its mathematical formulation are also presented. This model can be adapted to any application where prior knowledge is available by substituting Paris’ law by said information and applying the ensuing relationships on variables.

ABSTRACT. As a crucial electronic component in DC systems, predicting the Remaining Useful Life (RUL) of DC contactors can significantly enhance the operational reliability of the systems they are part of. Current methods for RUL prediction, which are based on single data points or traditional machine learning, face issues such as the selection of features that are inconvenient to monitor, high application costs, and low accuracy. In response, this paper proposes a method for predicting the RUL of DC contactors using Long Short-Term Memory (LSTM) neural networks. A specific DC contactor is examined as a case study to demonstrate the feasibility of applying this method. The advantage of the proposed method lies in its requirement for only the collection of current signals throughout the full lifecycle of the DC contactor to predict its RUL, resulting in low application costs. Compared to RUL prediction methods based on traditional Back Propagation Neural Networks (BPNN), this method achieves higher accuracy. Moreover, by considering key structural parameters that affect the lifespan of DC contactors, the method provides guidance for contactor design and exhibits better generalization capabilities in the predictive model.

ABSTRACT. The Dynamic High-Temperature Operating Life (DHTOL) test, as defined by the JEDEC standard JEP180.01, serves as a crucial metric for validating the long-term switching reliability of Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) in power management applications. Despite the standardized testing framework, the variability in switching test conditions across manufacturers complicates the direct comparison of GaN HEMTs' long-term switching reliability, even within specific applications. In this study, we adopt a holistic approach encompassing both technological considerations and application demands to assess the long-term switching reliability of two commercially available Enhancement-mode p-GaN HEMTs: the Schottky and Ohmic gate p-GaN HEMTs. Our primary objective is to identify the most reliable p-GaN HEMT under identical long-term hard switching stress conditions. Our analysis focuses on monitoring the degradation of the dynamic on-state resistance (dRds(ON)) as a fundamental parameter indicative of long-term switching reliability and observing long-term degradation. The findings of this study offer valuable insights into selecting the most suitable p-GaN HEMT for power conversion applications on a large scale. By elucidating the comparative long-term reliability performance of Schottky and Ohmic gate p-GaN HEMTs, our research contributes to enhancing the reliability and efficiency of power management systems utilizing GaN HEMTs.

ABSTRACT. In this study, a creep tester was developed for durability and quality assessment of solder joints. It is designed to apply normal and thermal stress simultaneously in the direction of gravity and adjust its magnitude accordingly. This test device allows the observation of creep changes in various solder joints under thermal–mechanical combined stress. Using the device, creep quality assessment was conducted on 97.5Pb2.5Sn solder joints—a high-temperature melting solder exceeding 300 °C. As the thermal stress reached 230 °C and the normal loads increased to 4.9, 9.8, and 14.7 N, the failure time decreased according to a power-law distribution. Application of normal stress in the range of 1.5–3.0 N/mm² was found to be suitable as a test method for the device under test. Creep quality assessment of Ag paste using a similar experimental setup revealed that the appropriate test method involved applying a normal stress of 1.5 N/mm² at 230 °C. The results of this study confirm the effectiveness of the developed creep tester utilising both normal and thermal stress for creep quality assessment of solder joints.

ABSTRACT. The present study investigated the heat-resistant durability of both AlN- and Si3N4 cored active metal brazing (AMB) substrates to demonstrate which material can be a better option for use in silicon carbide (SiC) power applications. The interfacial degradation behaviors, peeling strengths, and fracture modes of the AlN- and Si3N4-AMB substrates were carried out after thermal shock cycling tests. As a result, the microstructure investigation, the two types of substrates had differences in the composition of the BFM layer. It is noteworthy that AlN and Si3N4 AMB substrates subjected to repeated thermal shock of Δ190 °C for up to 1,000 cycles represented different failure modes in the peel strength test, and there was also a large difference in peel strength. Namely, these substrates have fundamental differences in thermal shock durability. Nevertheless, cracks between the AMB layer and the ceramic layer were equally caused on the edge side of both the AlN and Si3N4 cases after the thermal shock test. These cracks are the underlying principles that can explain the load-extension plots seen in the peel strength test. This study systematically discussed the heat-resistant reliability of AMB substrates with AlN and Si3N4 as cores for application to next-generation SiC power devices.

ABSTRACT. SiC MOSFET, as a new wide-bandwidth semiconductor device can significantly improve the efficiency, power density and reliability of power electronic converters, and the junction temperature monitoring is of great significance to improve the reliability of devices and systems. In this study, the linear relationship between the maximum value of the rate of change of the drain current during the process of opening and the junction temperature is pointed out for the first time, and the correctness of the theory is verified experimentally. This temperature-sensitive electrical parameter can be used for non-invasive on-line monitoring of the junction temperature of SiC MOSFET, and there is no need to add an additional measurement circuit.

ABSTRACT. This paper presents a novel methodology for the rapid long-term reliability assessment of planar InGaAs/InP avalanche photodiodes (APDs). To quickly obtain degradation data of highly reliable APD devices, hybrid stress which is both thermal and electrical stresses were applied simultaneously via the accelerated step-stress test (ASST) methodology. The details of the structure of tested APDs, experimental setup, and ASST conditions were explained. Based on the results, a significant increase in dark current with applied stress was observed while the breakdown voltage remains almost stable. The expected mean time to failure for each stress condition using ASST data were then extracted. Finally, based on the modified Eyring model, the activation energy and predicted lifetime under practical use condition are extrapolated.

ABSTRACT. Hybrid Switch (HyS) is consisted of a high-current Si-insulated gate bipolar transistor (IGBT) and a low-current Silicon Carbide (SiC)-MOSFET connected in parallel, which has been widely studied due to their high efficiency and low cost. In general, to realize the zero-voltage conduction of IGBTs, the switching timing of the Hys is usually chosen to turn on the SiC earlier or at the same instant. However, HyS will have current overcurrent stress problem, resulting in the maximum current rating being limited. In this article, an active drive circuit is proposed to suppress the SiC MOSFET current overshoot by extracting part of the driving current during the SiC current rise phase, so as to ensure the operational reliability of the hybrid switches. A double-pulse test platform was built to verify the proposed driver circuit under different load current conditions. The experimental results show that compared with the conventional driver circuit, the driver circuit proposed in this paper suppresses the current overshoot of the SiC by 38.3%, 28.4%, and 22% in the heavy-load, medium-load, and light-load conditions, respectively. The peak current of the SiC is within the limit of the safe operating area, while the increased switching loss is within the acceptable range.

ABSTRACT. This paper presents a detailed static characteristic model based on the EKV (Enz Krummenacher and Vittoz) model for 1200 V SiC MOSFETs in power electronic applications, with a specific focus on Ids(Vgs) at different temperatures. The study explores the nuanced behavior parameters in the model and provides a subset of results in this publication. Additionally, the methodology of parameter fitting for the model is elaborated upon, providing insights into the process of refining the model to match real-world behaviors. The forthcoming paper will extend the analysis into dynamic simulations, encompassing factors such as MOSFET capacitances, internal diode characteristics, and the impact of parasitic elements in the printed circuit board (PCB). This sequential approach allows for a comprehensive exploration, with the current research acting as a foundational step. This, in turn, sets the stage for more exhaustive discussions in subsequent publications. Notably, the model incorporates the physical behavior of the device and can facilitates the integration of drift models for specific parameters, such as threshold voltage Vth, on state resistance (Rds,on). This integration can be crucial for establishing models for predictive maintenance of converters equipped with SiC MOSFETs.

ABSTRACT. This work investigates the ruggedness of paralleled SiC MOSFETs tested under unclamped inductive switching (UIS) conditions. More specifically, the maximum avalanche energy (EAV) sustainable by individual and paralleled MOSFETs integrated in a multi-chip power module (PM) is quantified. Circuital electrothermal (ET) simulations are carried out by resorting to a physics-based electrical model of a commercial SiC power MOSFET coupled with a dynamic thermal feedback block (TFB) extracted through FANTASTIC. The impact on the ruggedness of the system of (i) mutual heating mechanisms between transistors and (ii) technological mismatches in breakdown voltage (BV) values is analyzed.

ABSTRACT. Radiation testing is an essential part of the qualification of electronic systems. Radiation standards use 60Co as a standard source to qualify systems under radiation. However, its operation requires strict security and radioprotection measures in addition to more expensive maintenance. Then, alternative sources and methodologies must be explored. In this work, we present a comparative study between the use of filtered high-energy X-rays and 60Co to perform TID testing in a 32-bit 28nm FDSOI DSP.

ABSTRACT. In this study, we developed an integrated analysis methodology for the reliability testing of light-emitting diodes (LEDs), leveraging real-time microscopic visualization with simultaneous electrical and optical analyses during stress tests to monitor degradation. In-house fabricated InGaN/GaN micro-sized LEDs (μLEDs) were used as prototypes. This approach also serves as a fault localization tool to pinpoint the locations of degradation through analysis of light intensity variations at individual image pixels. Furthermore, complementing this with physical failure analysis, electrical characterization and spectrum analysis of the LEDs provides a comprehensive understanding of the failure mechanisms, thereby facilitating the evaluation of LED reliability.

ABSTRACT. Smart spark plugs (SSP) with sensing capabilities become increasingly important for real-time monitoring and diagnostics in internal combustion engines. However, the deployment of numerous electronic devices and the complexity of the system can lead to numerous failures that must be investigated. This research presents a categorization of various failures using a machine learning (ML) technique. The method entails the collecting of sensor data both during the testing phase of SSP and upon returning after failure. ML model uses features retrieved from these data, such as voltage levels, charge times, current levels, etc. The model is refined using a training and validation method to successfully identify diverse failures, such as electric discharge on the transformer secondary winding, damping diode breakdown, and short circuit between windings. The significant challenge of this work is the limited number of failure samples since the device works under normal conditions in major times and only conducts the failure at minor times. Hence, an upsampling technique was applied to improve this imbalanced dataset. The classification algorithm's performance is measured in terms of accuracy, precision, recall, and F1-score. The results enable to identify any problem symptoms during acceptance testing and classify the probability of a certain failure.

ABSTRACT. The operation of electronic devices in hostile environment has been investigated. Issues due to Extremely Low Temperature (i.e., Cryogenic temperature) and operation in cryogenics liquids (liquid argon, LAr, or liquid nitrogen, LN2) are presented and discussed.

ABSTRACT. This article presents a methodology for designing compact single event transient (SET) sensitive test structures targeting frequencies up to 300 MHz. These structures are derived from a typical product architecture with minor modifications and inherit product properties, like masking effects, that can impart SET robustness. Our observations prove that even when there are significant SETs generated in the circuit, their contribution to the soft error rate might be negligible in the target frequency range for a given technology. Additionally, we demonstrate how the test structure design can influence the frequency dependence of soft error rate and can lead to misinterpretation of the measurement data when not correctly considered.

ABSTRACT. Accurately modelling the lifetime of a power module is a major concern in wind power applications. Their lifetime is modelled via empirical laws fitted to data from power cycling tests. Typical models are parametrized with respect to junction temperatures, even though some module types are limited by the substrate solder. For such a model, a reparametrization with respect to substrate solder temperatures is carried out and the influence investigated. The thermal behavior of a PrimePack2™.XT is studied in depth, utilizing reduced order models. Lifetime calculations of a junction-based and a substrate solder model through a mission profile show that the latter yields a significantly better lifetime. A shift in the substrate solder temperature towards beneficial temperature ratios during the operation is identified as the root cause for this.

ABSTRACT. The lifetime assessment of power electronics based on mission profiles is increasingly applied to obtain realistic lifetime predictions, considering application-close operational scenarios. Generally, mission profile-based lifetime is calculated by individual temperature cycles disassembled from the mission profiles using certain counting methods. Among different methods, the rainflow counting (RC) method is the most common algorithmic procedure for determining damage-relevant events in power electronics. However, the conventional RC method does not consider the transient effect on damage caused by time-dependent material properties, especially at high temperatures during power module operation. In this paper, we investigate the validity of using the RC method for mission profile-based lifetime assessment of power modules. Through finite element (FE) modeling, we explicitly calculate the transient effect driven by the mission profile. We demonstrate the difference in lifetime assessment between the conventional RC method and FE simulation.

ABSTRACT. Reliability prediction based on physical of failure (PoF) is an emergent and high-precision method, which significantly improves the practical application value of reliability engineering. The construction form of PoF model and the accuracy of parameter identification of full specification PoF models are the key factors establishing a complete reliability prediction model library. However, the existing methods ignore the influence of the distribution characteristics of PoF model, the literature does not consider the effects of material properties, structural dimensions and process parameters which is defined as manufacturing parameters on the PoF model coefficients, resulting in poor reliability prediction accuracy and low efficiency. In view of the above problems, a new reliability prediction method is proposed in the paper, which makes full use of PoF technology and comprehensively considers the quality consistency of manufacturing parameters. Firstly, the expression of PoF model considering quality consistency is constructed to characterize the quality fluctuation of manufacturing parameters. Then, the coefficient regression model between manufacturing parameters and model coefficients is established based on long short term memory (LSTM), and the reliability prediction model of electronic components is established. Finally, the effectiveness of proposed method was verified by a case study of electromagnetic relay.

ABSTRACT. Complex electronic systems have the characteristics of multi-level circuits and multiple redundancies, making it difficult to accurately simulate the system working state using existing reliability modeling methods. This paper proposes a multi-level reliability prediction model that extracts failure precursor parameters as model inputs. Firstly, construct the circuit-level multiple stress simulation model. Secondly, input the degradation and failure information and determine the system failure precursor parameters based on Sobol sensitivity analysis. Finally, a dynamic system model is established to calculate the comprehensive evaluation reliability of the system, with failure precursor parameters as inputs. A case study on a certain power supply system is discussed, which improved the simulation ability of the system working state while ensured the prediction accuracy. This paper also provides methods for the combination of physical of failure models and system-level reliability prediction.

ABSTRACT. In this paper, a behavioural model is proposed and validated for establishing the conducted emission characteristics of SiP (system-in-package) chips. The model is based on S-parameter extraction and conducted emission measurement data, and is used to construct the main internal active currents of the SiP chip by analyzing the main noise source modules and considering the actual transmission paths of noise signals in the system. The results show that the simulation results of the constructed model are in good agreement with the measurement results. This method circumvents the limitations of the traditional ICEM-CE modeling technique and is able to accurately predict the conduction emission of SiP chips. Which has a wide range of potential applications in evaluating the EMC characteristics of advanced packaged chips.

ABSTRACT. The excessive use of electronic equipment can accelerate the aging of circuit cables, resulting in arc faults. This paper presents a framework for detecting series arc faults based on spectrogram and deep residual network. The signal is converted into a spectrogram, which describes its time-frequency characteristics in the form of an image. Then, a deep residual network model is used to recognize the spectrogram and determine the type of arc fault. Finally, the current data is used to demonstrate the effectiveness and accuracy of the proposed method.

ABSTRACT. DC-link capacitors in inverters have a shorter lifetime than the other devices, and thus degrade reliability of the inverters. The inverters are usually fed by three-phase supply voltages; however, the three-phase voltages are frequently imbalanced due to the connection of single-phase power sources and loads, such as renewable energy, which places additional stress on the DC-link capacitors. This paper proposes a condition monitoring method of a dc-link capacitor without additional current sensor in an inverter system under imbalanced three-phase supply voltage. This inverter system employs a front-end six-pulse diode rectifier with a dc reactor. The method is based on an analysis of the rectifier output ripple voltage including the uncharacteristic harmonics that results from imbalanced supply voltage, which is valid in a practical imbalance ratio around 5%. Experimental results obtained from a 200-V 1.5-kW laboratory system confirmed that both the capacitance and ESR were monitored even though the supply voltage was imbalanced.

ABSTRACT. DC-link capacitors in power convertors have a shorter lifetime than other devices, which is an obstacle to reliability improvement and downsizing of the converters. The lifetime of the capacitor depends on the amount of its ripple current because a larger amount of ripple current results in a larger amount of internal temperature rise. This paper presents theoretical analysis and experimental verification of current sharing among parallel-connected dc-link capacitors. The analysis is obtained by current transfer function of each capacitor, and reveals that resonance among the capacitors and stray inductances drastically increases the root-mean-square (RMS) value of the capacitor current. This fact also implies that the sum of the RMS currents of the all the capacitors becomes much larger than the ripple current flowing out of a converter. In addition, the analysis shows that the closest and farthest capacitors to the converter tend to have a larger current than the middle capacitors. Experimental circuit consisting of chopper circuits rated at 500 V and 20 A with SiC MOSFETs is designed and constructed to test the capacitors with a high switching frequency of 10-200 kHz. Experimental results have confirmed the validity of the theoretical analysis.

ABSTRACT. In this paper, we demonstrate that accelerated aging tests of power electronic components (specifically N-MOSFETs in our case) have an adverse effect on the conducted emissions (common mode) in a 3-phase inverter used to drive an induction motor. To achieve this, we conduct electric accelerated aging tests while operating the power transistors to measure their conducted emissions before and after aging. A comparison between measurements in the time and frequency domains is presented to deduce the effect of aging on the MOSFETs. Experimental results show that after aging, there is an increase in the amplitude of conducted electromagnetic interference (EMI). Furthermore, this increase leads to parameter degradation that has not been investigated in EMI tests.

ABSTRACT. DC-link capacitors in power electronic systems are subjected to varying electrical load and environmental conditions. Conventional lifetime tests are using mainly constant operating conditions like temperature humidity and voltage as stress factors. Most tests are not applying a current load. This work describes a test setup applying a realistic current and voltage load to a capacitor with DC voltage bias up to 1000 V and high AC current load up to 500 A. Multiple topologies are compared and a prototype of the chosen switched inductor topology is presented. This enables lifetime tests with an application-oriented current loads.

ABSTRACT. By comparing the reliability of 150 nm AlGaN/GaN HEMTs with PtAu gates to devices with NiPtAu gates, it was found that PtAu gates are more stable in terms of gate leakage current increase under HTRB step stress test and show smaller spread of the extrapolated lifetime values during long-term DC stress tests. An activation energy of 1.37 eV (1.15 eV) and a lifetime of 107 h (5∙104 h) at Tch = 175°C and Vd = 30V (Vd = 15 V) has been extrapolated for devices with PtAu SiN assisted gate (100 nm T-gate). The faster degradation of the T-gate is possibly caused by a higher lateral electric field at the gate foot. By TEM cross sectioning and EDX mapping analysis of aged devices, the degradation of NiPtAu gate devices was attributed to a stress-induced local oxidation of the SiN passivation on the drain side of the gate foot.

ABSTRACT. The influence of different Aluminum concentration in the AlGaN back-barrier on short-channel and dispersion effects of 0.45 m-gate AlGaN/GaN HEMTs has been studied. Four samples have been tested, one as reference without back-barrier but with a Fe-doped GaN buffer, and three with an AlGaN back barrier with respectively 0.5%, 1% and 1.5% Aluminum. Back-barrier devices have lower current collapse with respect to the reference, the latter being affected by trapping at Fe-induced defects and at deep levels induced by residual C. Devices with 1.5% Al show subthreshold characteristics comparable with those of reference, but 50% lower current collapse. 1% Al backbarrier devices show very low drain-source leakage in pinch-off conditions and as a consequence the lowest dispersion effects.

ABSTRACT. In this study, we investigate the non-linear (NL) behavior of AlN/GaN HEMT under gain compression technologies when submitted to 10 GHz single-tone RF-step stress, crucial for millimeter-wave power application robustness. We evaluate AlN/GaN transistors, targeting high-power amplifiers with operating frequencies above 30 GHz. We present here an original method that includes, in a unique NL expression, the varying self-biasing effect caused by step-stress sequences. This methodology serves as a tool for comparative analysis across various technological variants and transistor geometries post RF stress. The step-stress are conducted on HEMT in transistor saturated mode and in diode configuration alone, to assess the physical origins and location of the critical SOA of these devices. We identify the mechanism of failure as stemming from the degradation of the Schottky gate when subjected to critical RF power levels, due to its constrained capacity to handle power signals exceeding 18 dBm. Furthermore, we highlight the remarkable RF robustness of this technology, achieving gain compression of around 10 dB without degradation.

ABSTRACT. This article focuses on the comprehensive evaluation of performance and robustness in microwave AlGaN/GaN HEMTs. The study investigates whether the degradation mechanisms observed during DC aging test align with those observed during RF aging test. A time-domain load-pull setup (1.8 GHz – 18 GHz) is utilized to measure key parameters during RF stresses and characterize the devices, revealing that RF aging test produces different degradations than DC aging test. These findings shed light on the behavior of HEMTs when subjected to an RF signal, highlighting the importance of considering both DC and RF measurements for device operability and safety in real-world applications.