ABSTRACT. Online estimation of the health status of power electronic modules is a critical concern in predicting the remaining useful life for predictive maintenance objectives. Traditional aging indicators have limited suitability for on-line monitoring due to their intricate and expensive procedures, often necessitating junction temperature estimation. This study introduces a novel electrical aging indicator tailored for bond-wire contact degradation, offering ease of online implementation and temperature independence. This indicator stems from experimental and theoretical investigations on the behavior of the zero-temperature coefficient (ZTC) of I-V characteristics of IGBT modules with top-metal interconnect degradation. The results show that the degradation of the bond-wire contacts has an effect on the ZCT point with a strong impact on the current and very little on the voltage. Leveraging this result enables the development of an online monitoring approach, the methodology of which is demonstrated through power cycling tests. Both traditional and new aging indicators show strong correlations with aging. In addition, the proposed new indicator has a better sensitivity to the degradation.

ABSTRACT. This paper focuses on the effects of load sequence on the reliability of insulated gate bipolar transistors (IGBTs). Precisely, the effect of junction temperature swing (∆Tj) is investigated in low ranges. A series of power cycling tests have been done; first, two tests with a single (∆Tj) conditions are performed in order to serve as test reference. Then, combined power cycling tests with two-level of (∆Tj) are conducted sequentially. The crack propagation for both combined tests specimens is analysed. Results show that a sequencing in (∆Tj) of the high-low stress level leads to crack retardation and then a crack acceleration after a number of cycles. In addition, the crack propagation of the low-high stress level follows the same evolution of the high stress crack propagation. These results were correlated to the microstructure parameters using Electron Backscatter Diffraction (EBSD) technique with a focus on the effect of residual stress. Local misorientation, grain size and grain boundaries evolution at the sites of crack propagation confirmed the phenomenon observed for the crack propagation for both combined tests.

ABSTRACT. This paper reports a demonstration of a new sensor device structure designed to increase the current change for detecting power cycle degradation. In a previous study, a low-cost and high-accuracy sensor device was proposed, which can be integrated into power device chip. The sensor device consists of a Schottky barrier MISFET. Power cycling degradation is detected by a decrease in the drain current of the SB-MISFET, as repetitive mechanical stress increases the interface state density of the MIS gate. The sensor devices demonstrated the basic operation of a decrease in drain current due to repetitive mechanical stress. However, the change in current was only 4 to 5 times smaller than initial current. In this study, it is clarified that this current change is limited by leakage current, and a new structure is proposed to suppress this leakage current. The proposed structure achieved a current change 12 to 13 times smaller than the initial current, due to the leakage current 1/8 times smaller compared to the conventional structure.

ABSTRACT. This work offers a comprehensive study on the temperature determination and development via temperature sensitive parameters (TSEPs) during repetitive switching events. Obtained information are discussed and judged with respect to accuracy for different device technologies. This evaluation is extended by the aspect of artificial front-side ageing for different emitter-pad designs. For two different designs investigated, no decreased switching robustness could be verified, even beyond the AQG 324 lifetime border, that is defined by a certain forward voltage drop increase.

ABSTRACT. This study investigates the reliability of the reading operation in 1S1R devices based on Ovonic Threshold Switching (OTS) selector and Phase Change Memory (PCM) co-integrated in a Double-Patterned Self-Aligned (DPSA) structure targeting Crossbar applications. Upon reading, the SET state can face a threshold voltage (Vth) increase of more than 20% dependently on the reading current and on the number of reading operations, which can lead to a soft failure. We separate the contributions to this increase coming respectively from OTS and PCM, finally providing an assessment protocol for the reading reliability. We show how the reading performances allow to determine the maximum Crossbar array size depending on the target voltage Read Window Margin and current Memory Window.

ABSTRACT. This study investigates the material properties, electrical characteristics, and reliability / lifetime aspects of ZrAlxOy dielectric films deposited by atomic layer deposition (ALD) for MIM decoupling capacitors in advanced CMOS technology. Through experimental investigation, including structural and electrical characterization, the impact of Al concentration on capacitance behavior, leakage current, and breakdown characteristics in both 2D and 3D configurations is explored. Results indicate that higher Al concentrations contribute to higher field linearity and reduced leakage in both topologies, while thinner dielectrics exhibit a power-law relationship with breakdown temperature. Notably, 3D samples demonstrate a breakdown behavior less influenced by chemical composition. Lifetime analyses reveal excellent reliability in 2D devices with the highest Al concentration, necessitating higher Al concentrations to improve reliability, especially in challenging deep 3D topologies. These findings underscore the importance of material composition and its relation to reliability ensuring stable and long-term performance.

ABSTRACT. The effect of vertical scaling of Cu interconnect for the efficiency of power consumption on a chip on BEOL reliability was investigated in 12nm DDR5 DRAM with 4 metal layers. The hydrostatic stress gradient which drives SM failure was calculated using the finite element method, and it decreased in the scaled interconnect, thus leading to an improvement in the SM reliability. The TDDB lifetime was also enhanced by the decrease in electric field between scaled Cu interconnects, which was demonstrated by both of the simulation and measurement. Although scaled interconnect could deteriorate the EM lifetime due to the increase in grain boundary, controlling the barrier metal thickness and utilizing advanced capping layer have compensated for the EM deterioration. As a result, 12nm DDR5 DRAM meets 125℃ BEOL reliability criteria while implementing low power through vertical scaling of Cu interconnect.

ABSTRACT. In this work, we investigate how individual gate oxide defects impact the reliable operation of nanoscale transistors, focusing on different body bias (BB) conditions. During our examination based on measure-stress-measure (MSM) measurements, we identified significant impact in both time-zero and time-dependent variabilities upon the appliance of BB. Increased time-zero and time-dependent variabilities are observed when a reverse body bias (RBB) is applied. These observations likely arise from the different impacts of random dopant distributions (RDD) induced by the modulation of the depletion region thickness due to BB. The dependence of both time-zero and time-dependent variability on BB conditions shows that BB can be used to efficiently improve the reliability of devices by fine-tuning BB.

ABSTRACT. The present work attempts to investigate in depth the electrical properties of thin HfO2 dielectric films for potential application in RF-MEMS capacitive switches. The dielectric films were deposited with Atomic Layer Deposition method at different temperatures leading from amorphous to polycrystalline materials. The electrical assessment was performed on Metal Insulator Metal devices. The breakdown voltage was found to depend on the deposition temperature. The samples were characterized by obtaining Current-Voltage characteristics, impedance analysis. Surface potential decay and Thermally Stimulated Depolarisation Current method.