ABSTRACT. In recent years the generation of the temperature swing for power cycling tests (PCT) in silicon carbide MOSFETs requires higher currents which may lead to overloading of the chip contact and module load terminals. In this work the periodic lowering of the gate voltage to generate higher power losses (gate voltage modulation) and its influence on the homogeneity of the temperature distribution on the MOSFET die, proposed in [1], is studied in a SiC MOSFET by the means of a parameter study. The results show no significant homogenisation of temperature distribution due to the gate voltage modulation compared to the temperature distribution at the same power for a static gate voltage.

ABSTRACT. The Short-circuit (SC) capability of power SiC MOSFETs is a key feature in applications as it allows device protection strategies: by detecting short-circuit situations (generally on the voltage across the device), it is possible to switch-off the device without damage on condition that maximum short-circuit time is not exceeded. Short-circuit capability of the device is defined by a Short-circuit Withstand Time (TSCWT) at a given operation point. End users are expecting a minimum robustness of the device in short-circuit which is expressed by a Short-circuit Time (TSC) long enough to allow detection and protection, and repetition of a given number of SC events without damage. A test methodology for short-circuit assessment based on experimental analysis is proposed in this paper.

ABSTRACT. As a screening test recipe, burst unclamped inductive switching (UIS) test is proposed to improve breakdown voltage uniformity. One of the critical disadvantages of GaN-HEMTs is its lack of the UIS withstanding capability, because there is no removal structure of holes, which generated by the avalanche breakdown. Hence, at the screening in the mass-production, measurement of the avalanche breakdown voltage cannot be employed to reject low breakdown voltage devices due to catastrophic failure, and conventional static drain leakage current measurements are insufficient. This paper reports a screening test of GaN-HEMTs by repetitive overvoltage stress using burst UIS test. The experimental results show the repetitive overvoltage stress was needed to reject outliers with low breakdown voltage and optimum test current avoided to generate new outliers.

ABSTRACT. This work presents an investigation of the drain current saturation (ID-SAT) effect on the short-circuit (SC) robustness of 650 V normally-off gallium nitride (GaN) high electron mobility transistors (HEMTs). SC tests were performed on devices at a drain-source voltage (VDS) of 400 V, varying parameters such as the gate resistance (RG), the on-state gate-source voltage (VGS), and the parasitic source inductance (LS) of the device under test (DUT). As expected, variation on the maximum of ID-SAT was observed by varying these parameters. The results indicate a possible dependence between ID-SAT and SC robustness. Indeed, devices exhibit a relatively long SC withstanding time (SCWT) under non-repetitive SC events. However, under repetitive SCs with very short durations, the DUT generally fails after a few SC cycles depending on maximum saturation current value. This suggests that maximum ID-SAT within a very short time (≤ 500 ns) causes enough damage to the DUT rather than thermal accumulated SC stress over hundreds of microseconds.

ABSTRACT. The paper discusses enhancements in quantitative thermal lock-in analysis through spatial phase evaluation for defect localization in complex microelectronic components. It addresses the challenges of increasing integration density and diverse material composition in microelectronics. The primary focus is on improving sensitivity and spatial resolution in lock-in thermography by analysing lateral phase distribution to compensate for thermal spreading effects. Experimental results demonstrate significant improvements in precision and accuracy of defect localization and depth estimation. The paper highlights the potential application of the proposed method in 3D-integrated microelectronic devices.

ABSTRACT. Advanced packaging in electronics involves integrating semiconductor devices and sensors into a unified package, often employing complex 3D structures for enhanced performance and efficiency. As electronic components become smaller and more densely packed, conventional 2D X-ray radiography is not sufficient for inspection. Here we demonstrate the use of nano-CT with a high bandwidth memory (HBM) example illustrating the potential of fast detection of sub-micron voids and cracks in microbumps. Using a 30 s overview scan at 2.6 µm voxel size for navigation, a region is selected for a high-resolution scan with a voxel size of 600 nm to analyse 20 µm microbumps in between DRAM layers. The results show how high-resolution nano-CT can effectively be used for fast failure analysis and R&D as well as important feedback to production ramp up and yield improvements of advanced packaging technologies.

ABSTRACT. Gold-plated electrical contacts are now widely used in electrical and electronic systems to provide high-quality and high-reliability connections. Many studies have been carried out on failure analysis of gold-plated contacts in high temperature environments. Fuzz button contacts are however less study. In this paper, the experimental method is developed to analyze the influences of high environmental temperature on the performance of gold-plating fuzz button contacts. The result shows that the natural length and compression force of fuzz button contacts were shortened and decreased after the elevated temperature tests respectively, and the quantitative analysis of test samples microstructural changes is conducted by characterization methods such as optical microscopy, scanning electron microscopy (SEM) and focused ion beam (FIB) technology, it is found that a large No. of twin structures disappear, precipitated phase size increases, dislocations density decreases, thus the ability of fuzz button contacts to resist plastic deformation decreases, resulting in stress relaxation.

ABSTRACT. In this study we introduce an extended sample preparation workflow to enhance two-dimensional charge carrier quantification via scanning spreading resistance microscopy for failure analysis and electrical device characterization. This is achieved by means of embedding a novel partial-staircase doping profile close to the area of interest prior to cross-sectioning the device. We subsequently demonstrate that this approach enhances quantification reliability while reducing analysis time.

ABSTRACT. The failure mechanism of GaN HEMTs in the high voltage regime where the short circuit withstand time (SCWT) is smaller than 1 μs is not fully understood. A bipolar failure mechanism has previously been suggested implying that intentional hole injection would play a major role in device robustness. In this work, we study the role of hole injection in the failure mechanism of p-GaN HEMTs at 600 V. SCWT is compared in three device types: 1) a normally-ON (NON) p-GaN HEMT without intentional hole injection, 2) a NON p-GaN hybrid-drain embedded HEMT where holes are injected from the hybrid-drain and 3) a normally-OFF p-GaN HEMT with hole injection from the gate. For the same drain switching current and 600 V drain voltage no significant changes in the median SCWT have been found. This implies that intentional hole injection is not a major controlling factor in the bipolar failure mechanism of p-GaN HEMTs.

ABSTRACT. Power cycling tests (PCTs) are important to evaluate the lifetime of power electronic devices. Discrete SiC MOSFETs with improved packaging and interconnection technology have proven a high reliability but also show a certain spread in lifetime. For testing those in an appropriate test duration, a high acceleration factor in the test is required. In this paper a PCT with hybrid testing of the body diode and channel in reverse direction of discrete SiC MOSFETs was performed. Depending on the channel contribution, this allows a reduced load cur-rent and still a positive temperature coefficient. With this strategy similar failures like in standard PCTs were observed. The test results are compared with standard PCTs in forward and body diode mode only. A compara-ble lifetime to the reference test is achieved for an operating regime with a positive temperature coefficient.

ABSTRACT. This paper investigates the time-dependent gate degradation of Schottky-type p-GaN gate transistors by the application of constant electrical stress until the breakdown of the device, indicated by a sudden increase in the gate leakage current. Tests are performed at voltage levels outside the datasheet limits to accelerate the occurrence of failure. To understand the impact of temperature on the failure mechanism, tests encompass temperature ranges from -55 °C to 80 °C, within datasheet recommendations. Results demonstrate that the lower the temperature, the shorter the lifetime indicating a negative activation energy; results also present a non-constant activation energy within the range of tested temperatures, demonstrating a complex temperature dependence of the failure mechanism that might not be unique other this temperature range. A very low lifetime of only one day were estimated at -55 °C at the nominal datasheet voltage . The validity of the projection was experimentally confirmed. This underline the importance of further investigating the gate behaviour at low temperatures, as it could be critical for certain applications. Additionally, this challenges the standard gate reliability tests typically performed at the maximum temperature rating of the device, which do not appear to represent the worst-case condition for the gate lifetime.

ABSTRACT. In this work, discrete SiC MOSFETs with an RDS(ON) of 60 mΩ and a blocking capability of 1200 V have been subjected to thermal shock tests and additional power cycling tests to study interactions between the failure mechanisms in both tests. In this context, an Rth,jc (thermal resistance: junction - case) increase of up to 55 %, confirmed by found solder degradation in cross sections, can be noted after the thermal shock test. However, bond wire degradation remains the dominant cause of failure after the power cycling test, even if the solder layer of the test specimens was previously pre-damaged.

ABSTRACT. Spacecraft is a complex and precise system that works in unmanned and harsh space environments for a long time. To ensure its high reliability and high stability operation, a large number of sensors are usually deployed on it to monitor its status in real-time. However, because components are affected by factors such as wear, aging, impact, sensors are prone to failure, which in turn brings potential danger to the high-reliability operation of aerospace on-orbit. Therefore, this paper proposes a method to improve the reliability of spacecraft sensors based on temporal digital twins. Firstly, mean filtering is used to process the collected original data to reduce the impact of noise on digital twin modelling. Secondly, the processed data is used to build a digital twin of the sensor based on the transformer model. Then, by comparing the output of the model with the measured values of the sensor, the sensor reliability assessment and data recovery are achieved, thus improving the reliability of the sensor. Finally, this paper verifies the effectiveness of this method using spacecraft power sensor data.

ABSTRACT. For independent DC microgrid, there is no support from the power grid and the dynamic behaviours in the microgrid easily causes the stability problem. Due to the multi-converter structure and the nonlinearity of the independent DC microgrid, the stability analysis faces big challenge. In this paper, a Floquet theory stability analysis method is proposed for a PV-storage independent DC microgrid, its time-domain model is firstly established, including photovoltaic (PV) cells model, energy storage batteries model, DC-DC converters model and loads model; secondly, the stability of the whole independent DC microgrid system is analyzed by using Floquet theory; finally, the correctness and effectiveness of the proposed method is verified by the circuit simulation. Therefore, this proposed stability method in this paper provides a fast way to accurate analyze the independent DC microgrid.

ABSTRACT. With the continuous increase in power density in modern power converter, there is a growing focus on thermal system design, as its performance is a key factor influencing power density and determining the reliability of power converter. As the main heat dissipation component in the power conversion field, the heatsink plays a significant role in improving the reliability of power converters. However, it is difficult to forecast the accurate thermal performance of the device in field use. Thus, the purpose of this work is to present and propose a methodology for optimizing heatsink designs that are based on high-performance computing and machine learning. The developed ML-based surrogate models can predict the thermal performances of the optimization heatsink without a complicated analytical model.

ABSTRACT. The problem of counterfeiting in electronics is not recent but still critical today. Identifying counterfeit devices can be challenging because not everything that seems suspect is necessarily fake. The paper deals with the non-destructive detection of counterfeiting in electronics by using only electrical measurements. This approach paves the way for machine learning classification-assisted counterfeit detection through electrical measurements. Physical de-processing provides the final confirmation.

ABSTRACT. Alumina thin films are often used as barriers in HF etch processes in modern microelectronics. In various microelectronic applications, films deposited on driving electrodes, such as those made of alumina, might be responsible for various charging effects leading to the degradation of microelectronic devices. This necessitates high-quality alumina layers with a low density of defects and interface states. In the present study, we compare the electrical properties of alumina layers deposited with different oxidants (ozone and water) using atomic layer deposition. Capacitance-voltage measurements reveal that all as-deposited alumina layers contain negatively charged defects, but their concentration is significantly higher in layers prepared with ozone. The origin of these defects will be discussed. Furthermore, we demonstrate that the density of interface states in layers prepared with ozone is also significantly higher compared to those prepared with water. However, this can be optimized by varying the deposition temperature or the flow of O3. Such defects also influence current-voltage characteristics, which are also analysed in this study.

ABSTRACT. This paper presents a method to enhance the prediction accuracy of SiON pMOSFET degradation under AC stress. The degradation occurring in the preceding stage (pre-ON or OFF-state) is analyzed by extract the Vth degradation profile, which influences the subsequent stage (post-OFF or ON-state). As a result, the negative charge generated by stress in the pre-OFF-state increased the gate oxide field in the post-ON-state, accelerating the degradation of the post-ON-state. This phenomenon became more localized at the drain edge. The positive charge generated by pre-ON-state non-uniformly altered the electric field between the gate and channel, accelerating degradation due to post-OFF-state, especially at the source and drain region. Furthermore, integrating post-ON and OFF-state degradation models for each channel region during the effective period of AC stress improved the accuracy of Vth degradation modeling for SiON pMOSFETs under various duty ratios of AC stress.

ABSTRACT. This paper gives insight into investigation of the p-channel and n-channel power VDMOS transistors under NBT stressing. Experiments were conducted with the goal to determine how the NBT stressed devices later operate under normal operating conditions. Induced self-heating is recorded using thermographic camera. Based on the experimental results, the analysis has been done to determine the level of the degradation of the devices under normal operating conditions.

ABSTRACT. Combination of Wafer Level Packaging (WLP) process with Non-Evaporated Getter (NEG) integration ensures the high-level vacuum hermetic packaging required by resonator based MEMS such as accelerometers or gyroscopes. In this paper, we report a new characterization method to measure the NEG sorption efficiency under the replicated WLP process conditions, so as to ensure that the integration of NEG is well adapted to the overall MEMS fabrication process. Our approach is validated by measuring quality factor (Q-factor) of hermetic packaged resonators, demonstrating a 80-fold Q-factor increase through NEG integration

ABSTRACT. This study presents novel methodologies for the reverse engineering and failure analysis of semiconductor devices, focusing on overcoming the limitations of traditional Focused Ion Beam (FIB) techniques. Central to our approach are two innovative methods: high-precision volumetric imaging via 3D reconstruction from laser-delayered surface profiles and a hybrid delayering technique combining ultrashort pulsed laser removal with FIB polishing. These methods address the challenges of slow delayering processes and uneven layer exposure by enabling faster material removal, minimizing thermal damage, and ensuring precise surface preparation for imaging. The effectiveness of these approaches is demonstrated through detailed imaging of embedded chip circuitry in two advanced technology chips. Our findings highlight significant advancements in the speed, accuracy, and efficiency of semiconductor device analysis, promising to streamline reverse engineering efforts and enhance failure analysis processes.

ABSTRACT. In conventional analysis flows, the accuracy of subsystem selection for subsequent analysis is often compromised by the reliance on preliminary retests which offer only partial coverage. This limitation is further exacerbated in ultracompact systems, where the scope for electrical characterization is inherently restricted, and the ability to analyse each subsystem is constrained by the need to avoid irreversible sample preparations. In this paper, we introduce a novel analysis flow that significantly enhances the success rate of failure analysis. This improved methodology incorporates low-invasive sample preparation techniques alongside dedicated electrical analysis, thereby minimizing the risk of sample degradation. By employing a deductive sequential process, this innovative approach systematically refines the analysis steps based on initial retest data, consequently enabling the derivation of definitive conclusions with greater precision and reliability. This refined analytical strategy represents a substantial advancement in the field, offering a robust failure analysis flow for accurate fault isolation in complex systems where traditional methods fall short.

ABSTRACT. In recent years, the unique material parameters of Gallium Nitride (GaN) have led to a significant increase in its applications across various industries. When combined with aluminum gallium nitride (AlGaN), these materials find extensive use in High Electron Mobility Transistors (HEMTs) designed for high-temperature, high-frequency, and high-power applications. However, the absence of a GaN substrate and the utilization of alternatives such as silicon carbide (SiC) can introduce defects that, along with thermal and electrical overstress, may alter the behavior or even damage such devices. In this study, we investigate a GaN device that has been damaged by electrical overstress using electrical probing techniques including Electron Beam-Induced Current (EBIC), Electron Beam Absorbed Current (EBAC), and Electron Beam Induced Resistance Change (EBIRCH). We compare the results obtained from the damaged device with those from an intact device to gain insights into the effects of electrical overstress on GaN-based devices.

ABSTRACT. There is an increasing concern regarding a Schottky Barrier Diode (SBD) embedded on certain devices which is affecting its performance and causing the device to fail on various parameters. This failure leads to a very significant yield loss that needs to be improved. This paper aims to investigate the root cause of the failure by means of a detailed failure analysis with the collaboration of different teams such as Design, Application, and Process team to possibly suggest a corrective action.

ABSTRACT. Nowadays, electrification trends, especially in the automotive market, are driving the need for high power electronics. In the past years, Silicon Carbide (SiC) and Gallium Nitride (GaN) microelectronics solutions have been introduced on the market as they have clear benefits for such application (its key benefits include delivering higher voltage operation, wider temperature ranges and increased switching frequencies) [1]. These Wide Band Gap (WBG) technologies are relatively new, thus, quality control and reliability understanding are critical topics to make sure they will remain sustainable [2].

In this paper, we will present 3 Failure Analysis use cases (2 presented in this abstract) and workflows related to power device technologies. In collaboration with our Fault Isolation tool equipment supplier, we have extended the well-known OBIRCh [3] and Photoemission [4] techniques to high voltage devices in a safe and industrial environment, keeping the right level of sensitivity for detecting fault on wide band gap devices. These newly developed HV-O.B.I.R.Ch. (High Voltage - Optical Beam Induced Resistance Change) and HV-Em. Mi ((High Voltage – Photon Emission) analysis have been implemented on our Meridian S Platform. This solution allows addressing our current High Power devices roadmap up to 3kV.

ABSTRACT. This paper proposes a submodule (SM) capacitor stress balancing control of a modular multilevel converter used for a battery energy storage system. The proposed control adaptively adjusts the capacitor current according to online capacitor parameter monitoring results in order to improve capacitor lifetime. Experimental results of the proposed control show a suppression of the SM capacitor current by 30.0%. Reliability analyses reveal that the proposed method improves the lifetime of the MMC 6.04 times as long as existing control.

ABSTRACT. This paper analyzes the potential issues and mechanisms concerning the reliability of assembly in CSOP (Ceramic Small Outline Package) packaged devices, and the relevant failure cases are presented. The reliability of CSOP packaged devices is assessed through experimental and simulation analyses. To address high reliability application scenarios, it is recommended to perform the lead forming on CSOP devices and conduct assembly validation to ensure the reliability of the assembly. Furthermore, it is suggested to revise or establish standards pertaining to CSOP assembly requirements to further enhance device application reliability.

ABSTRACT. In this work, we present novel 3D-printable plastic direct coolers for power modules. The main objective of the work is to identify highly efficient solutions for heat extraction in terms of both thermal resistance and temperature uniformity, in order to reduce as much as possible the thermomechanical stresses that can lead to power module failures. The study relies on finite element modeling to guide the design toward optimal solutions. An ad hoc test bench was built to test the effectiveness of prototypes.

ABSTRACT. Over the years packaging types of semiconductor devices have continued to evolve. One of the most complex package types in the Renesas portfolio is the System in Package or SIP. The SIP package presented in this paper features a thin die, copper pillars, a substrate, passive components, it is overmolded and has an exposed die. The large number of interfaces and components can lead to numerous potential failure locations. The failures addressed in this study are a result of humidity-related qualification processes. Due to the intricacies of the SIP package, following the FA procedure of standard integrated circuit packages resulted in an analysis period of 2-3 weeks. As a result, an altogether new failure analysis approach was necessary.

ABSTRACT. In this work, a Finite Element (FE) thermal model is presented to further understand the mechanism of surge current-induced failure of press-pack devices. The model is set up with the results of electrical measurements taken during diode tests to identify the surge current at which the failure occurs. The tests were carried out with an ad hoc bench specifically designed to have surge currents with different energies to be dissipated in the diode under test using the Integral Resonant Sliding Mode Control (IRSMC) technique.

ABSTRACT. Sintered silver has become an effective alternative to die attach materials for wide-bandgap semiconductor power modules. Although sintered silver shows excellent thermal conductivity and long-term stability, pores in sintered silver can seriously affect the mechanical performance and overall fatigue life of power modules. In this work, combining the Gaussian filter technique and macro finite element (FE) analysis, the porous microstructure model of die attach sintered silver is established and input as the topology information for materials property assignment of sintered silver and investigating the fatigue behavior of SiC power modules. The thermal transfer and mechanical behavior of the power modules with different thicknesses of die attach layers are examined, and the fatigue lifetime of the different power modules is evaluated. The results show that the simulated porous microstructure of sintered silver has a good agreement with the experimental observation; the stress and viscoplastic dissipation density are higher for the power modules with smaller thickness of sintered silver die attach layer and significantly concentrated near the interface between SiC and sintered silver. With the increase of the thickness of the sintered silver, the accumulated viscoplastic dissipation energy is reduced, and the fatigue life of the power module is improved.

ABSTRACT. As the application of Cu wire in demanding automotive electronics sector increases, its reliability in higher and higher temperature is a topic of frequent discussion ever. To respond these demands, extended research was done to define a deeper knowledge base for understanding pitting corrosion effects in packaging materials leading to new possibilities for improved material developments. The results led to a new type of Pd coated Cu (PCC) wire, which realizes a significant improvement against pitting corrosion even at extreme temperatures up to 250°C while maintaining low resistivity as good as a 4N gold wire.

ABSTRACT. We present an investigation on the impact of device encapsulation on the Time-Dependent Dielectric Breakdown (TDDB) in polymeric dielectrics for galvanic isolators. By means of experimental and numerical analyses, we highlight the importance of device package to prolong TDDB lifetime and improve device reliability. Results point out that not only device contact termination but also device encapsulation are key aspects to consider to push the performance and the reliability of modern galvanic isolators to their ultimate limits.

ABSTRACT. After decades of improvement, the reliability of Printed Circuit Boards (PCB) is well known and standardised. However, the standards are based on outdated material properties and old experiments and thus, they contain a large safety margin, when modern insulation materials are applied. This work focuses on the insulation properties and reliability of solder stop under high humidity and high voltages. It could be shown that significantly more robust systems can be achieved than the standards specify. This leads the way for further volume reductions.

ABSTRACT. In this paper, a new 130V SGT-MOS structure is proposed to enhance the resistance of single-event burnout by numerical simulations. The simulation shows that as the trench depth decreases, the impact ionization on the path of heavy ion decreases significantly due to lateral drift, which reduces the probability of triggering parasitic NPN transistor by hole carriers, and thus changes the SEB sensitive position of the device. Apart from optimizing trench depth, Schottky source contact and N buffer layer are also added to reduce the peak electric field region, which effectively improves the SEB threshold voltage. This research can guide all power devices with a split-gate design and has great potential in space and aerospace power applications.

ABSTRACT. This article presents a model for device failure of power rectifiers during surge current events. A possible failure cause of those devices are exceeding surge currents. Therefore, the detailed understanding of the device behavior under surge conditions and the related failure mode is essential to achieve and maintain a stable device performance. In this work, the IFSM failure mode is investigated in terms of experimental determination of the failure temperature for rectifier diodes. The failure locations of the stressed devices are determined on the chip and electro-thermal simulations are run to model the temperature distribution. The simulated temperature distribution matches with the analyzed failure locations. The failure can be explained by local thermal runaway for PN as well as Schottky diodes, if hole injection from the PN junction or the Schottky contact is taken into account.

ABSTRACT. In this paper, the performance degradation under repetitive short circuits was investigated for the Si and GaN separately in cascode GaN devices. To avoid the self-sustained oscillations during short circuits, a modified short-circuit test platform is proposed to conduct the test safely. To characterize the static performance of the Si and GaN parts separately, a new decapsulation method is proposed on a commercial cascode GaN device. Considering the trap effect on GaN devices, a fair test procedure is designed to avoid the influence brought by the fluctuation of the GaN threshold voltage. The performance degradation was analysed after going through repetitive short-circuit tests at 100 V/10 us, revealing the reliability of the Si and GaN parts separately.

ABSTRACT. SiC MOSFETs are crucial for efficient power conversion in electric vehicles, especially in the traction inverters operating on 800-V battery architectures. Their unipolar nature offers significantly lower switching losses compared to bipolar Si IGBTs. However, achieving high efficiency without compromising reliability remains a challenge. This study investigates the impact of driving waveforms on the SiC MOSFET switching loss and overshoot. Unlike conventional gate drivers, our approach involves a closed-loop amplifier combined with a push-pull circuit, enabling controllable gate driving waveforms through strategically placing a low-pass filter before the amplifier, so called the pre-RC method. Compared to the conventional method of placing RG in front of the gate, the pre-RC method shows notable decrease in switching loss for the trising shorter than about 0.4 µs. The lower switching loss can be attributed to the larger |dVGS/dt| at around the Vth of the SiC MOSFET. However, the larger |dVGS/dt| also leads to the larger VGS overshoot. This work demonstrates that a well balance between the switching loss and overshoot can be found by optimizing the driving waveform.

ABSTRACT. In this paper, the power cycling reliability of cascode GaN devices is comprehensively studied. A new decapsulation method is proposed where the mid-point of the cascode GaN device can be easily accessed without damaging the chip or influencing the device performance. Based on this, the power cycling tests were conducted. The performance degradation of the Si MOSFET, the normally-on GaN, and the cascode GaN is investigated independently. At last, the end-of-life power cycling tests were conducted under two different temperature swings to study the device lifetime. Based on the obtained experimental data, a simple lifetime model is given using the Coffin-Manson fitting.

ABSTRACT. In this article, two planar SnO/β-Ga2O3 and SnO/κ-Ga2O3 p-n heterojunctions with the same dimensions are considered as cases of study. The device electrical and thermal properties were simulated by the Synopsys Sentaurus-TCAD suite, taking as parameters the applied forward bias, contact resistance (Rcon), and considering differently doped regions fabricated under the metal-semiconductor contacts. The distribution of the electric current density and thermal load across the metal-semiconductor interface has been evaluated before and after the modulation of doping in these regions (size of the regions and their dopant concentration). This preliminary study sheds light on the advantages and constraints of planar diodes constructed with κ- and β-Ga2O3 for power electronics applications, providing useful hints for limiting the current crowding and improve heat dissipation, which can significantly influence the reliability of a power device, and ultimately reduce the intrinsic energy loss during device operation.

ABSTRACT. This paper investigates the reliability of SiC MOSFETs through gate-oxide degradation tests. A condition monitoring circuit is developed to calculate short circuit peak current, which serves as a degradation-sensitive parameter. The results of gate-oxide degradation tests demonstrate a significant change in the gate threshold voltage of MOSFETs. Furthermore, the short circuit tests validate that the shift in gate threshold voltage resulting from gate-oxide degradation can lead to a 20% variation in short-circuit peak current.

ABSTRACT. Photovoltaics (PV) modules are guaranteed for 25 or 30 years, but severe climatic events, like hail, can cause premature damage. This paper presents a real case study to demonstrate the relevance of hail testing even beyond what currently required by the standards; to demonstrate the presence of latent damage even in absence of broken glass, and to discuss related risks. A residential photovoltaic system in Padova, Italy, was studied after exposure to a storm with hailstones four times larger than those used in standard (IEC 61215) tests: forward bias electroluminescence (EL) and infrared radiation (IR) investigations were conducted in dark to minimize the external environmental impacts. Complete glass breakage PV modules results in the fragmentation of the solar cells, leading to non-uniformity in current flow and thermal radiation, necessitating replacement. Hail-induced damage is detectable even when the protective glass of the modules withstood the mechanical impact of hail (latent or invisible damage). These defect results in reduced EL intensity and higher IR radiation, posing safety and efficiency concerns for the PV module. Results underline the necessity of inspecting the entire PV system following hailstorms, to detect and promptly replacing any latent damaged modules, even in absence of glass breakage.

ABSTRACT. In this paper, we introduce a compact model tailored for silicon carbide MPS diodes in the form of a SPICE-compatible subcircuit. The model is designed to (i) describe the undesired snapback mechanism, which is likely to occur in unoptimized diodes with narrow width of the PiN portion and/or excessively thick drift layer, (ii) capture the dependence of geometry-related parameters upon cell width, as well as width of the individual PiN and Schottky portions, (iii) account for the impact of temperature on the related parameters; in addition, the thermal equivalent of the Ohm’s law is exploited to allow for static and dynamic electrothermal simulations within SPICE-like tools. The proposed subcircuit is adopted to analyze imbalances occurring in paralleled snapback-affected MPS diodes subjected to current surge events.

ABSTRACT. Modern solid-state lighting systems allowed to enhance the energy efficiency of light sources, improve quality and reduce the related costs; however, the reliability of light-emitting diodes (LEDs) is a critical aspect, especially in systems where high powers/small footprints are required. In this paper, the long-term reliability of high-power LEDs for outdoor lighting is analyzed. LEDs were mounted on metal-core printed circuit boards (PCBs), 8 LEDs per PCB, and stressed for 8000 h near their absolute maximum current, at different ambient temperatures (45, 65, 85, 105 °C). LEDs were characterized individually by means of I-V characterizations and power spectral density measurements. LEDs stressed at the lowest temperatures showed almost no degradation, whereas LEDs stressed at 85 and 105 °C showed an initial gradual degradation, followed by a catastrophic degradation, due to silicone cracking and darkening. X-ray imaging and shear tests highlighted a solder degradation. Remarkably, negligible thermal resistance variation was measured, however, junction temperature increased during the stress. The increased temperature was attributed to gradual silicone degradation, that increased silicone lens light absorption in a positive feedback loop, leading to the cracking/darkening of the lens.

ABSTRACT. RISC-V soft processors are becoming popular in various fields, including safety-critical ones, thanks to their open-source nature and flexibility. Despite the rapid progress in the reliability analysis of these devices, all the mitigation techniques are usually adopted to the whole soft-processor architecture. In this study, we aim to identify the internal components of the RISC-V architecture that are particularly prone to errors, and then investigate how the reliability of the design is affected when mitigation strategies, such as Triple Modular Redundancy (TMR), are applied selectively just to them. The proposed approach has been applied to RISC-V architecture, NEORV32 which is implemented on Zynq 7020 SoC on a PYNQ-Z2 board. While more vulnerable modules of NEORV32 were identified through accurate reliability analysis, implementing selective TMR in these modules shows achieving satisfactory reliability levels while reducing the overall space requirements compared to a complete TMR design.

ABSTRACT. Lithium-ion batteries (LIB) have been widely used in electrical vehicles for the past decade due to their profitable qualities like low self-discharge, high power and energy density, long life wide operating temperature range, and lack of memory effect. For stable operation, it is crucial to focus on the state of health of LIB, which is a challenging task. This article presents an investigation of the impact on the LIB cycle life of different current patterns (constant and pulsed) to be used during balancing. This investigation is carried out using a simple and cost-effective method that aims to measure directly the battery capacity using the Ampere-hour (AH) integration. Constant current and pulsed current cycles have been used to represent the typical battery current patterns used during active cell balancing; the surface temperature of the cells has been recorded as well.

ABSTRACT. This work shows the single-event upset (SEU) results of Xilinx 16nm FinFET UltraScale+ Filed-Programmable Gate Array (FPGA) device in geo-stationary transfer orbit (GTO). SEUs results for each month, different SEUs shown by sub-satellite location, distribution of multibit errors results and different event rates are provided in this paper. The on-orbit results show that the percentage of multibit errors in 16 nm FPGA device have slightly increased compared to 90nm FPGA. This phenomenon proves that as process technology transitions to FinFET, not only does the probability of multibit error events occurring increase, but also the distribution among SEU expands. The SEU and SEE rates are calculated as 7.05×10-8 and 4.72×10-8 upset/bit/day respectively.

ABSTRACT. We introduce a pioneering testing procedure designed to anticipate the fundamental causes of degradation and failure in GaN HEMT devices and systems, with a focus on enhancing the accuracy of reliability predictions. Our approach involves the utilization of tailor-made circuits to evaluate packaged GaN HEMT devices. Through this methodology, these devices are subjected to a comprehensive array of stress conditions, including high voltage reverse bias (HVRB) and high voltage gate bias (HVGB), concurrently. Our investigations yield insights into the activation energy (Ea) values pertaining to both Vds degradation and Vgs degradation scenarios. By gaining a deeper understanding of the degradation and malfunction mechanisms in GaN-based devices, our research facilitates the prediction of their reliability based on performance, thereby addressing the critical need to anticipate the dependability of GaN-based hardware.

ABSTRACT. Novel reliability tests are being developed for power semiconductor devices, especially for those based on wide band-gap materials, such as silicon carbide (SiC), in electric vehicles field. More specifically, because of the automotive environment and higher permissible slew rates in SiC devices, it is important to assess reliability in harsh conditions. Potentially related to this test, incomplete ionization of the dopants and edge termination fails are reported for SiC devices, in consequence of fast transients, but aging phenomena and parameters drift have not been deeply investigated. The purpose of this work is to evaluate the DRB test in detail, with a reliability perspective

ABSTRACT. This paper investigates reliability of SiC-MOSFETs under high current-stress operations typically used in circuit breakers and/or grid applications. This paper introduces an evaluation system for assessing the grid's fault current and tests the degradation of SiC-MOSFETs under both forward and reverse overcurrent conditions. The experimental results clarify that limited saturation current and degradation in reverse conduction characteristics restrict the operational range and overcurrent capability of SiC-MOSFETs in grid applications.

ABSTRACT. This manuscript evaluates the heat dissipation capabilities of Wide Band-Gap (WBG) and Ultra-Wide Band-Gap (UWBG) power semiconductors or modules in comparison with traditional Silicon (Si)-based technologies. Despite the necessity for a power semiconductor module to efficiently convey electrical power with minimal losses, substantial current flow within a module often results in power dissipation in the form of thermal energy. This thermal output, especially under high-temperature conditions, is a primary cause of failure in power semiconductor modules. To address these challenges, next-generation power semiconductor modules are leveraging WBG and UWBG materials like Silicon Carbide (SiC), Gallium Nitride (GaN), Gallium Oxide (Ga2O3), and diamond to supersede Si, the conventional semiconductor material. These WBG and UWBG components are poised to meet the advanced performance demands of modern power applications. Nevertheless, their exceptionally high power densities necessitate advanced thermal management strategies to ensure optimal operation. The thermal conductivity of WBG and UWBG materials surpasses that of Si-based technologies. While the thermal conductivity at the chip level is critical, assessing the thermal efficiency of the entire system is essential. This research employs thermal simulation to investigate the heat dissipation performance of WBG and UWBG power modules.

ABSTRACT. The parallelling of power semiconductor devices is essential for desired current ratings and the system is prone to the current unbalancing due to parameter variations. SiC devices with significant variable threshold voltage due to manufacturing yield and temperature distribution have a consequential possibility of dynamic current unbalancing. This paper presents the peak detection-based current balancing of parallel-connected SiC devices to minimize the turn-on and turn-off current unbalancing. PCB current sensors are used for the measurement and feedback of the signal for this peak detection-based current balancing mechanism.

ABSTRACT. As Radio Frequency (RF) GaN HEMTs can show a low voltage level in the Human Body Model (HBM) ESD classification, the sample size, the batch-to-batch variation, the test methodology and the test set-ups can influence the classification level. For example, low sample sizes per voltage level can lead to a higher classification level and using a step stress approach for classification can lead to a lower classification level. Two GaN HEMTs processed in the same technology with different power ratings were investigated with (i) step stress testing, and (ii) with testing at one voltage level, using different test set-ups and different wafer and assembly batches. A lognormal distribution gives a good fit for the HBM failure voltages acquired from step stress testing and can quantify the differences between GaN HEMTs, test set-ups and different batches. The failure percentages observed with one level testing can be significantly lower than what is expected based on the step stress HBM failure distribution. Furthermore, the spread observed in the HBM failure distributions acquired by testing at one voltage level is significantly larger than the spread observed in the HBM failure distribution as determined by step stress testing.

ABSTRACT. In contemporary society, power electronics technology stands as a pivotal driver for industrial and technological progress. This paper focusing particularly on high-power density applications like electric vehicles and renewable energy, where enhancing power density is paramount for efficiency and energy conservation. Silicon carbide (SiC) chips, prized for their superior performance and resilience, dominate these applications. However, while silver sintering technology offers excellent thermal conductivity and reliability in interconnection, its prohibitive cost impedes wider adoption. To address this, the study proposes a novel sintering application for packaging systems, aiming to enhance thermal performance and reliability. The investigation explores large-area copper sintering technology as a promising alternative, with a focus on TPAK structures and large-area sintering packaging interconnections. Through experimental analysis involving copper film transfer and copper paste printing techniques, the study evaluates sintering performance and proposes design improvements. By introducing organic escape channels, the study achieves a reduction in organic residues, enhancing the density and strength of sintered layers. This research contributes to advancing interconnection solutions in high-power density applications, fostering technological progress and application development.

ABSTRACT. Main failure mechanisms of NTC thermistor were investigated. Reliability design was executed for NTC thermistor including field conditions and failure mechanisms to simulate field operating condition. Finally, life model and acceleration model for NTC thermistor were predicted. Failure mechanisms were analyzed using FE-SEM. Electrical characteristics such as beta constant and junction temperature were measured. Accelerated life tests were done. Accelerated life test reveals that main factors for accelerating are temperature (~100 times scale) and voltage (~10 times scale) and humidity has little influence. As results of failure analysis, main failure mechanisms are electromigration and diffusion. Acceleration life test tells that life distribution is Weibull distribution with shape parameter 3.8 and acceleration model is temperature-voltage model with activation energy 0.65e V and material constant 6.4. The results of accelerated life test and failure analysis coincides well in that voltage accelerates electromigration and temperature accelerates diffusion. This failure analysis and accelerated life test were done to bead type NTC thermistor. Therefore, there is no guarantee of accuracy for other types

ABSTRACT. In the space environment, electronic devices are affected by both radiation and electromagnetic interference (EMI) , which can lead to failure very easily. In order to improve the stability and reliability of the chip working in harsh environment, this paper investigates the synergistic effect of total ionizing dose (TID) and EMI in SRAM. The experimental results show that the TID radiation degrades the performance of the circuit, but has different effects on the electromagnetic susceptibility (EMS) of different functional pins. The electromagnetic immunity level of the power pin is significantly reduced, while the write enable and address pins show a slight increase and decrease, respectively. Additionally an appropriate back-gate bias voltage compensates for the transistor threshold voltage shift caused by the TID effect, which can recover the EMS performance of the chip.

ABSTRACT. The impact of mold compound on the power cycling capability of semiconductor devices is a decisive factor for their lifetime. In this work, the influence of mold compound was experimentally investigated on double side cooled modules (DSC). Half-bridge modules with SiC MOSFETs were tested under similar conditions. As there are no load bond wires in the analysed DSC modules, particular attention was paid to the resulting failure modes. The DSC modules with mold compound showed only slight traces of ageing after the test procedure. In the DSC modules without mold compound, previously defined end of life (EoL) criteria were reached and the failure analysis showed clear signs of ageing due to the power cycling test (PCT). A positive impact of the mold compound on the DSC module was concluded.

ABSTRACT. In this work, the dynamic Ron effects on the efficiency and conduction loss in GaN-based AC-DC flyback converter was evaluated. Compared to the static on-resistance, the dynamic Ron of single p-GaN gate HEMT shows a significant increase under hard switching via a double pulse test. In addition, the dynamic Ron shows a further increase when the pulse time increases, indicating that the real dynamic Ron in the continuous switching system may not be totally revealed by a single pulse test. On the other hand, the combo IC operated in the system indicates that the substantial increase of dynamic Ron (>188% increases) in p-GaN gate HEMTs have the limited impacts on 1) the conduction loss (<9%) in p-GaN gate HEMTs and 2) the system efficiency (>92%) in GaN-based AC-DC flyback converter.

ABSTRACT. In this paper we analyze the OFF-state performance of vertical GaN-on-Si Trench MOSFETs in terms of breakdown voltage and stability of the threshold voltage. We proved that the devices fail in OFF-state due to the breakdown of the unprotected gate oxide. Then, by means of a series of fast VTH transient experiments, we demonstrate that the OFF-state threshold instability is given by the trapping of electrons at deep levels in the p-GaN body layer, transported by the rather high drain current leakage. The interpretation was supported by deep level spectroscopy measurements, carried out on p-n junctions located on the same wafer.

ABSTRACT. Investigating interface defects at dielectrics/III-nitride interface is vital for deeper understanding of threshold voltage shifts in GaN-based MIS or MOS FETs and the dynamic RDS, on in HEMTs. While some researchers use the deviation of the measured capacitance of a stressed curve in relation to an ideal reference curve to quantitatively assess the interface state density, Dit, there is a notable absence of comprehensive discourse regarding the influence of measurement parameters, such as measurement time, on the extraction of the interface density. In this paper, we have established a correlation between the leftward shift in the measured capacitance-voltage (CV) curve, often associated with effects of UV illumination, and the impact of negative bias stress at elevated temperatures, solely attributed to electron emission from trap states. We demonstrate how the extraction of Dit is impacted by the selection of measurement conditions as sampling rates, measurement time and temperature, and we provide a quantitative interpretation of these effects. We demonstrate that the estimation of Dit can be significantly underestimated, by a factor of 4, for extraction times ranging from 70 ms to 200 s, in comparison to previous studies. The technique is applied for Dit extraction at SiN/GaN interface using a MIS-capacitor.

ABSTRACT. We demonstrate the existence of two different degradation mechanisms for 100V GaN transistors submitted to off-state stress. When the devices are stressed in strong pinch-off conditions, a high electric field falls on the dielectric between the source field plate and the channel, and a time dependent dielectric breakdown is observed. On the other hand, for weaker pinch-off, the presence of a small sub-threshold leakage current redistributes the potential, reducing the electric field across the oxide and leading to longer TTF. A second degradation mode is then observed, consisting in the gradual increase in off-state current, ascribed to positive charge trapping at defects spots.

ABSTRACT. This work focuses on the extraction of Threshold Voltage Shift due to interface trapping from Charge Pumping (CP) measured curves. The proposed mathematical approach analyzes the peak of the charge pumping curve, proportional to the average interface defects density, for estimating the threshold voltage shift due to interface trapping separately from the shift induced by oxide trapping. The high-frequency nature of CP measurements is therefore exploited for the detection of fast states. The analyzed devices are 4H-SiC n-channel MOSFETs and a custom, on-wafer, in-situ measurement setup is used. Under constant current gate stress, positive and negative charge trapping processes are identified; the role of a) charge trapping in the oxide and b) interface states generation is analyzed and described.

ABSTRACT. The evaluation of the bias temperature instability (BTI) of the threshold voltage (Vth) is important for analyzing the stability of RDS,on and virtual temperature calculation by the VSD-T technique. But before this, the Vth hysteresis should be first analyzed to choose the suitable Vth measurement parameters and eliminate the hysteresis effect on the BTI. This paper investigates the Vth hysteresis of SiC MOSFETs under various measurement conditions. The differences in Vth hysteresis between planar and trench devices are significant. Relevant analytical results can provide the measurement guidance for the BTI evaluation for different types of SiC MOSFETs.

ABSTRACT. We investigate the degradation induced by an OFF state stress condition in normally-on (NON) MIS-HEMTs for power applications. The state of the devices was tracked by considering the shift in the threshold value over time during the stress and the following recovery phase by means of a custom setup. During the transition between stress and recovery, we observed an immediate partial recovery of the VTH (70 %) that occurs in less than 10 us, while the remaining VTH is recovered in about 100 s. With a dedicated analysis, we managed to investigate this ultra-fast recovery transient for the first time, and we observed that the recombination of electrons from 2DEG with ionized donors is responsible for this dynamic.