ABSTRACT. This paper presents a root cause analysis of defective Hall-effect sensor devices with focus on thermo-mechanical simulation. The study identified a complex failure mode caused by chip-package interaction, which has a similar signature to discharging defects such as ESDFOS. However, the study revealed that the defect was induced by local mechanical force applied to IC structures due to the presence of large irregular-shaped filler particles within the mold compound. Extensive failure analysis work was conducted to identify this failure mode. A combination of different failure analysis techniques was used to isolate the defect position, including backside CMP polishing, PFIB trenching of the substrate, SEM PVC imaging and large area FIB cross-sectioning. The study found that large irregularly shaped filler particles, located on top of the chip surface, cause locally high compression stresses onto the IC layers and following initiating cracks in the isolation layers. For further analysis, thermo-mechanical finite element analysis (FEA) was applied to verify the mechanical load condition for these large irregular-shaped filler particles. As a result of the FEA, thermo-mechanical strain due to epoxy shrinkage during the molding process could be identified as a root-cause in combination of large irregular-shaped filler particles.

ABSTRACT. This study was carried out to understand the high-temperature stability of Ag nano-porous sheet bonded joints which were designed with an Ag metallization layer directly plated on the Cu die and substrate during thermal aging. The Ag plated layer deformation and CuxO penetration between Ag plated layer and Cu substrate formed during thermal aging at 250 °C from 125h, which continuously grew up to 500h. The growing CuxO phase penetrated between the Ag plating and Cu, leading to voids that developed into a delamination layer over time. The delamination and continuous voids formed between CuxO and Cu had a critical effect on reducing the bonding strength. In this study, we thoroughly investigated the issues that may arise during thermal reliability testing at 250 °C when bonding commercial Ag nano-porous sheets directly Ag-plated onto Cu, from the perspective of microstructural development.

ABSTRACT. Driven by applications in the field of electric mobility, power electronics face the challenge of being able to operate at higher power densities. 3D packaged power modules appear as a promising solution, but are difficult to manufacture. Electrodeposited copper allows for flexibility in the module’s design. This paper evaluates a die attachment method based on the thermocompression of electrodeposited porous copper films. A characterization study of this solution, including its behaviour after thermal ageing, is carried out.

ABSTRACT. This study investigated the long-term thermal reliability of a sintering paste incorporating Ag-coated Cu (Cu@Ag) particles to inhibit copper oxidation. After thermal aging, shear strength increased in Cu@Ag joints under inert and air atmospheres, showing different microstructures. In an inert atmosphere, a Cu-Cu sintering network emerged, while in air, atmosphere facilitated the formation of a Cu2O network encasing the Cu@Ag particles within the sintered joint. Subsequent analyses of the sintered joint microstructures, post long-term thermal reliability testing and differentiated by pressurization and non-pressurization in air, unveiled further disparities. Pressurized samples exhibited a dense sintering network within the joint microstructure that restricted oxygen access to copper, leading to a thin Cu2O shell encapsulating the copper particles. Conversely, non-pressurized samples featured a porous sintering network, enabling direct contact between copper and oxygen during thermal aging and the formation of a significant Cu2O bulk network. The fracture modes also varied between the pressurized and non-pressurized samples, with ductile fracture observed in the former and brittle fracture in the latter. Based on these findings, this study proposes an optimal microstructure for the Cu@Ag paste, promoting the use of a Cu@Ag sintering paste as a cost-effective and antioxidative approach for enhancing thermal reliability.

ABSTRACT. InGaN/GaN multiple quantum well (MQWs) solar cells are promising devices for application in harsh environments; however, understanding their degradation kinetics can be complicated by the high periodicity of the active region (AR). To overcome this issue, we carried out an experiment on structures with only two quantum wells, having different indium concentrations, that were submitted to an optical power step stress at 55 °C. First, preliminary device characterization indicates that the QW near the p-side of the device strongly contributes to carrier collection. This is explained by the enhanced hole extraction and collection efficiency. Second, during optical power step stress, we observed: a) a decrease in the measured short-circuit current (Isc), especially at high excitation intensities; b) an increase in current conduction below the main diode turn-on voltage, which is ascribed to the increase amount of traps in the active region of the devices. The degradation leads to a reduction in the extraction and collection efficiency of photogenerated carriers, as evidenced by the decrease of the open circuit voltage (Voc), which is the parameter most significantly affected by degradation. Results give insight for the optimization of InGaN/GaN-based solar cells structure, that can be used to improve performance and reliability.

ABSTRACT. This study investigates the optically-induced degradation of Cu(InGa)Se2 (CIGS) solar cells subjected to monochromatic laser irradiation. We employ semi-transparent CIGS devices fabricated on fluorine-doped SnO2 (FTO)-coated glass substrates. Prior to laser exposure, we characterized the electrical properties under dark and illumination conditions to establish pre-stress parameters. Utilizing a one-diode model, we determined that defect-assisted carrier transport dominates within the space charge region. Continuous stress to constant optical power resulted in the degradation of electrical parameters, particularly a decrease in open-circuit voltage (Voc). Analysis of the dark current-voltage (I-V) characteristics revealed that the changes in saturation current and ideality factor followed a square-root dependence on stress time. This behavior is attributed to the diffusion of Na ions towards the junction. Conversely, the decrease in Voc (correlated with the turn-on voltage decrease in dark I-V curves) is interpreted as light-induced defect generation that enhances leakage current at the CdS/CIGS interface.

ABSTRACT. Catastrophic optical damage (COD) is a degradation mode of laser diodes. The power threshold to COD can be reduced by laser aging, but also it can be modified by the operation conditions, e.g. the cavity temperature, and technological aspects, e.g. the packaging stress. We analyze here the influence of the temperature of the cavity and the packaging stress on the local heat sources responsible for the COD. The study is based on the modeling of the thermomechanical mechanism for COD using finite element methods. The results evidence a reduction of the power threshold to COD when one considers these additional factors.

ABSTRACT. In this study, the degradation model of InGaAs/InP avalanche photodiodes (APDs) by accelerated life test (ALT) is proposed using technology computer-aided design (TCAD). Degradation through life testing can be categorized into three types: (1) increasing dark current, (2) decreasing breakdown voltage, and (3) simultaneous changes of (1) and (2). Based on the hypothesis of two possible degradation mechanisms, we focused on key degradation parameters such as interface trap density (Nint) and the α of the Gaussian function representing doping distribution. Increasing Nint leads to leakage current at the SiNx/InP surface. Additionally, decreasing breakdown voltage indicated catastrophic degradation, where the increment of α in TCAD simulations suggested the degradation due to Zn penetration. Based on the results, it contributes to the understanding of degradation processes in InGaAs/InP APDs and also provides valuable insights for the analysis of device structures with the similar accelerated aging effect.

ABSTRACT. This study deals with the development of a wide-frequency-band characterization for failure analysis of power modules, focusing on a specific IGBT packaging. It is highlighted that different characteristics of the IGBT and the packaging can be distinguished depending on the frequency band analyzed, enabling the detection of potential failure modes. Particularly, for the power bond-wire lift-off mechanism, the paper emphasizes the importance of considering high-frequency analysis above 200 MHz. It is enabled through the definition of a failure indicator, demonstrating the ability to highlight partial failures as well as to localize them.

ABSTRACT. SiC is used as a new generation of power semiconductors to meet the increasing demands of modern electrified automotive powertrains. The state of the art are Al-plated SiC semiconductors, which are bonded with Al bond wires. The known failure is a crack along the interface near the area between the Al bond foot and the Al metallization. In this study, an Al-free system with a fully copper-plated structure is used. The investigated SiC MOSFET is electroplated with 30 μm Cu and contacted on top with 300 μm Cu bond wires. The degradation mode of the copper bond wire as a top contact for copper-plated SiC is to be analyzed, because limited results on the typical failure modes and mechanisms are available in the literature. The components are stressed in different configurations and measured by active power cycling tests. The investigations revealed a different degradation mode depending on the degree of oxidation of the copper during the test. In the case of oxidation exclusion, the propagation and direction of cracks differs from the variant with strong oxidation. The experimental data of the excluded oxidation variant are then analyzed using finite element simulations, focusing on the applied thermo-mechanical stress.

ABSTRACT. Copper has pervasively replaced gold as preferred wire bonding material in Integrated Circuits (IC) plastic packaging. Different types of wires are available today in the market, with specific annealing treatments, coating and doping solutions aimed at optimizing bondability and reliability performances of the joints. In this study, the electrical resistance drift of packaged daisy chains has been analyzed to compare the lifetime potential of pure and alloyed copper wires under accelerated High Temperature Storage (HTS). Two aluminum-based bond-pads with different composition and thickness have been included in the experimental matrix. The results obtained through this statistically efficient and non-destructive methodology have been correlated with more “classical” readout data based on wire pull test, polished cross sections for Inter-Metallic Compounds (IMC) thickness measurement and TEM lamellas for phases stoichiometry characterization. Comparative analysis of the drift plots has pointed out a specific electrical signature for the consumption of the aluminum source under the IMC joint, confirmed by a Finite Element Method (FEM) simulation. A systematic delay in the IMC evolution has been demonstrated in all the samples with alloyed copper wires, correlating their lower ohmic drift with a lower thickness and a different composition of the IMC phases growing during HTS.

ABSTRACT. A comparative study of wire bond degradation under accelerated power cycling (PC) and a recently developed highly accelerated mechanical lifetime testing method (Bamfit) in commercial IGBT modules with thick Al wire bonds is presented. The mechanical fatigue life curve of wire bonds was determined in the range of 1e5 and 1e8 loading cycles with different displacement amplitudes (∆x). A nominal junction temperature difference of ∆Tj = 60 K was selected for PC tests which resulted in wire bond lift-off failure at a reasonable testing time of Nf~ 3e5 loading cycles under the given testing conditions. Finite element simulations (FEM) were used to calculate the equivalent interfacial stresses in the wire bonds at different ∆Tj and ∆x. Furthermore, interrupted PC and Bamfit tests were conducted at different stages of the lifetime to study the extent of interfacial degradation of wire bonds under both loading conditions. Based on the quantitative assessment of the wire bond degradation using static shear tests and computer tomography, a model for prediction of the remaining lifetime of wire bonds under accelerated mechanical fatigue tests and power cycling is proposed.

ABSTRACT. The introduction of robust interconnects such as copper wire and metallization, and silver sinter die technology have significantly increased the reliability of insulated gate bipolar transistor (IGBT) power devices. As a result, the reliability testing duration has increased, and it is particularly challenging to investigate the degradation mechanism in the wire bonds. To shorten the testing time, and to test the failure modes in the wire bonds an isothermal accelerated mechanical fatigue interconnect test has been introduced. This mechanical fatigue test attempts to mimic thermomechanical stresses caused during power cycling. In this work, an in-depth microstructure investigation of the failure mode in copper top interconnects after power cycling and after mechanical fatigue testing were carried out. It was found that the crack propagation path for both tests was similar. The mechanical test is seen to alter the microstructure of the wire bond, particularly around the wire and metallization interface

ABSTRACT. The talk will illustrate the issues for the use of non-volatile memories in space, emphasizing the effects due to the harsh radiation environment. Total ionizing dose and single event effects will be discussed for a variety of technologies, from 3D NAND Flash to magnetoresistive memories. Trade-offs in the selection of rad-hard devices versus commercial-off-the-shelf will be presented from the point of view of radiation hardness, capacity, and performance. A perspective on memory evolution scaling and new space trends will complete the presentation.

ABSTRACT. Edge AI brings the benefits of AI, such as neural networks for computer vision analyses, to low-power edge computing platforms. However, application and resource constraints leading to inadequate protection can make edge devices vulnerable to environmental factors, such as cosmic rays. These factors can cause bit flips that affect the reliability of the neural network inferences computed using these edge devices. To address this issue, we developed the C-SMART preprocessor that adds a theoretically analysed condition on top of the SMART technique for obtaining both reliability and performance benefits. SMART is a reliability improvement technique introduced in our previous work, which involves skipping the multiply-accumulate operations performed on the zero-valued inputs to the layers of the neural network. We demonstrated C-SMART with a commercial bare-metal system containing an ARM microprocessor by exposing the system to real-world, atmospheric-like neutron radiation using the ChipIr facility in Oxfordshire, UK. We also conducted timing measurements for performance analysis. Our experiments with C-SMART for inference with a neural network revealed a reliability boost against soft errors by more than 26%, simultaneously improving performance by more than 35%. We foresee these benefits in various COTS devices by integrating C-SMART with compilers and NN generators.

ABSTRACT. The behavior of a 350 V Enhancement Mode GaN power HEMT during heavy ion irradiation is presented. A new experimental setup has been developed to increase the sensitivity of the measurement. It allowed the measurement of the charge collected at the terminals following the impact with energetic particles to be extended by almost an order of magnitude. The results obtained, interpreted with the aid of two-dimensional finite element simulations, demonstrate that the tested devices exhibit very different behavior from those previously characterized. They do not show significant charge amplification and are not subject to single-event gate failure. Furthermore, device failure occurs when the ion hits its drain.

ABSTRACT. A conventional silicon-controlled rectifier integrated into a laterally diffused MOSFET(SCR-LDMOS) is studied through TCAD simulations in order to obtain the maximum holding voltage without increasing the area consumption or degrading the power-to-failure robustness. A reference device with 150V trigger voltage, 3V holding voltage and an approximate thermal breakdown at 30 mA/μm is adopted. Different configurations of the drain-side region are compared, with the best solution showing a 5x improvement on the holding condition without a significant variation on the other figures of merit.